Module efr32x12p::prs
[−]
[src]
PRS
Modules
| ch0_ctrl |
Channel Control Register |
| ch10_ctrl |
Channel Control Register |
| ch11_ctrl |
Channel Control Register |
| ch1_ctrl |
Channel Control Register |
| ch2_ctrl |
Channel Control Register |
| ch3_ctrl |
Channel Control Register |
| ch4_ctrl |
Channel Control Register |
| ch5_ctrl |
Channel Control Register |
| ch6_ctrl |
Channel Control Register |
| ch7_ctrl |
Channel Control Register |
| ch8_ctrl |
Channel Control Register |
| ch9_ctrl |
Channel Control Register |
| ctrl |
Control Register |
| dmareq0 |
DMA Request 0 Register |
| dmareq1 |
DMA Request 1 Register |
| peek |
PRS Channel Values |
| routeloc0 |
I/O Routing Location Register |
| routeloc1 |
I/O Routing Location Register |
| routeloc2 |
I/O Routing Location Register |
| routepen |
I/O Routing Pin Enable Register |
| swlevel |
Software Level Register |
| swpulse |
Software Pulse Register |
Structs
| CH0_CTRL |
Channel Control Register |
| CH10_CTRL |
Channel Control Register |
| CH11_CTRL |
Channel Control Register |
| CH1_CTRL |
Channel Control Register |
| CH2_CTRL |
Channel Control Register |
| CH3_CTRL |
Channel Control Register |
| CH4_CTRL |
Channel Control Register |
| CH5_CTRL |
Channel Control Register |
| CH6_CTRL |
Channel Control Register |
| CH7_CTRL |
Channel Control Register |
| CH8_CTRL |
Channel Control Register |
| CH9_CTRL |
Channel Control Register |
| CTRL |
Control Register |
| DMAREQ0 |
DMA Request 0 Register |
| DMAREQ1 |
DMA Request 1 Register |
| PEEK |
PRS Channel Values |
| ROUTELOC0 |
I/O Routing Location Register |
| ROUTELOC1 |
I/O Routing Location Register |
| ROUTELOC2 |
I/O Routing Location Register |
| ROUTEPEN |
I/O Routing Pin Enable Register |
| RegisterBlock |
Register block |
| SWLEVEL |
Software Level Register |
| SWPULSE |
Software Pulse Register |