Module efr32x12p::lesense [] [src]

LESENSE

Modules

altexconf

Alternative excite pin configuration

biasctrl

Bias Control Register

buf0_data

Scan results

buf10_data

Scan results

buf11_data

Scan results

buf12_data

Scan results

buf13_data

Scan results

buf14_data

Scan results

buf15_data

Scan results

buf1_data

Scan results

buf2_data

Scan results

buf3_data

Scan results

buf4_data

Scan results

buf5_data

Scan results

buf6_data

Scan results

buf7_data

Scan results

buf8_data

Scan results

buf9_data

Scan results

bufdata

Result buffer data register

ch0_eval

Scan configuration

ch0_interact

Scan configuration

ch0_timing

Scan configuration

ch10_eval

Scan configuration

ch10_interact

Scan configuration

ch10_timing

Scan configuration

ch11_eval

Scan configuration

ch11_interact

Scan configuration

ch11_timing

Scan configuration

ch12_eval

Scan configuration

ch12_interact

Scan configuration

ch12_timing

Scan configuration

ch13_eval

Scan configuration

ch13_interact

Scan configuration

ch13_timing

Scan configuration

ch14_eval

Scan configuration

ch14_interact

Scan configuration

ch14_timing

Scan configuration

ch15_eval

Scan configuration

ch15_interact

Scan configuration

ch15_timing

Scan configuration

ch1_eval

Scan configuration

ch1_interact

Scan configuration

ch1_timing

Scan configuration

ch2_eval

Scan configuration

ch2_interact

Scan configuration

ch2_timing

Scan configuration

ch3_eval

Scan configuration

ch3_interact

Scan configuration

ch3_timing

Scan configuration

ch4_eval

Scan configuration

ch4_interact

Scan configuration

ch4_timing

Scan configuration

ch5_eval

Scan configuration

ch5_interact

Scan configuration

ch5_timing

Scan configuration

ch6_eval

Scan configuration

ch6_interact

Scan configuration

ch6_timing

Scan configuration

ch7_eval

Scan configuration

ch7_interact

Scan configuration

ch7_timing

Scan configuration

ch8_eval

Scan configuration

ch8_interact

Scan configuration

ch8_timing

Scan configuration

ch9_eval

Scan configuration

ch9_interact

Scan configuration

ch9_timing

Scan configuration

chen

Channel enable Register

cmd

Command Register

ctrl

Control Register

curch

Current channel index

decctrl

Decoder control Register

decstate

Current decoder state

evalctrl

LESENSE evaluation control

idleconf

GPIO Idle phase configuration

ien

Interrupt Enable Register

if_

Interrupt Flag Register

ifc

Interrupt Flag Clear Register

ifs

Interrupt Flag Set Register

perctrl

Peripheral Control Register

prsctrl

PRS control register

ptr

Result buffer pointers

routepen

I/O Routing Register

scanres

Scan result register

sensorstate

Decoder input register

st0_tconfa

State transition configuration A

st0_tconfb

State transition configuration B

st10_tconfa

State transition configuration A

st10_tconfb

State transition configuration B

st11_tconfa

State transition configuration A

st11_tconfb

State transition configuration B

st12_tconfa

State transition configuration A

st12_tconfb

State transition configuration B

st13_tconfa

State transition configuration A

st13_tconfb

State transition configuration B

st14_tconfa

State transition configuration A

st14_tconfb

State transition configuration B

st15_tconfa

State transition configuration A

st15_tconfb

State transition configuration B

st16_tconfa

State transition configuration A

st16_tconfb

State transition configuration B

st17_tconfa

State transition configuration A

st17_tconfb

State transition configuration B

st18_tconfa

State transition configuration A

st18_tconfb

State transition configuration B

st19_tconfa

State transition configuration A

st19_tconfb

State transition configuration B

st1_tconfa

State transition configuration A

st1_tconfb

State transition configuration B

st20_tconfa

State transition configuration A

st20_tconfb

State transition configuration B

st21_tconfa

State transition configuration A

st21_tconfb

State transition configuration B

st22_tconfa

State transition configuration A

st22_tconfb

State transition configuration B

st23_tconfa

State transition configuration A

st23_tconfb

State transition configuration B

st24_tconfa

State transition configuration A

st24_tconfb

State transition configuration B

st25_tconfa

State transition configuration A

st25_tconfb

State transition configuration B

st26_tconfa

State transition configuration A

st26_tconfb

State transition configuration B

st27_tconfa

State transition configuration A

st27_tconfb

State transition configuration B

st28_tconfa

State transition configuration A

st28_tconfb

State transition configuration B

st29_tconfa

State transition configuration A

st29_tconfb

State transition configuration B

st2_tconfa

State transition configuration A

st2_tconfb

State transition configuration B

st30_tconfa

State transition configuration A

st30_tconfb

State transition configuration B

st31_tconfa

State transition configuration A

st31_tconfb

State transition configuration B

st3_tconfa

State transition configuration A

st3_tconfb

State transition configuration B

st4_tconfa

State transition configuration A

st4_tconfb

State transition configuration B

st5_tconfa

State transition configuration A

st5_tconfb

State transition configuration B

st6_tconfa

State transition configuration A

st6_tconfb

State transition configuration B

st7_tconfa

State transition configuration A

st7_tconfb

State transition configuration B

st8_tconfa

State transition configuration A

st8_tconfb

State transition configuration B

st9_tconfa

State transition configuration A

st9_tconfb

State transition configuration B

status

Status Register

syncbusy

Synchronization Busy Register

timctrl

Timing Control Register

Structs

ALTEXCONF

Alternative excite pin configuration

BIASCTRL

Bias Control Register

BUF0_DATA

Scan results

BUF10_DATA

Scan results

BUF11_DATA

Scan results

BUF12_DATA

Scan results

BUF13_DATA

Scan results

BUF14_DATA

Scan results

BUF15_DATA

Scan results

BUF1_DATA

Scan results

BUF2_DATA

Scan results

BUF3_DATA

Scan results

BUF4_DATA

Scan results

BUF5_DATA

Scan results

BUF6_DATA

Scan results

BUF7_DATA

Scan results

BUF8_DATA

Scan results

BUF9_DATA

Scan results

BUFDATA

Result buffer data register

CH0_EVAL

Scan configuration

CH0_INTERACT

Scan configuration

CH0_TIMING

Scan configuration

CH10_EVAL

Scan configuration

CH10_INTERACT

Scan configuration

CH10_TIMING

Scan configuration

CH11_EVAL

Scan configuration

CH11_INTERACT

Scan configuration

CH11_TIMING

Scan configuration

CH12_EVAL

Scan configuration

CH12_INTERACT

Scan configuration

CH12_TIMING

Scan configuration

CH13_EVAL

Scan configuration

CH13_INTERACT

Scan configuration

CH13_TIMING

Scan configuration

CH14_EVAL

Scan configuration

CH14_INTERACT

Scan configuration

CH14_TIMING

Scan configuration

CH15_EVAL

Scan configuration

CH15_INTERACT

Scan configuration

CH15_TIMING

Scan configuration

CH1_EVAL

Scan configuration

CH1_INTERACT

Scan configuration

CH1_TIMING

Scan configuration

CH2_EVAL

Scan configuration

CH2_INTERACT

Scan configuration

CH2_TIMING

Scan configuration

CH3_EVAL

Scan configuration

CH3_INTERACT

Scan configuration

CH3_TIMING

Scan configuration

CH4_EVAL

Scan configuration

CH4_INTERACT

Scan configuration

CH4_TIMING

Scan configuration

CH5_EVAL

Scan configuration

CH5_INTERACT

Scan configuration

CH5_TIMING

Scan configuration

CH6_EVAL

Scan configuration

CH6_INTERACT

Scan configuration

CH6_TIMING

Scan configuration

CH7_EVAL

Scan configuration

CH7_INTERACT

Scan configuration

CH7_TIMING

Scan configuration

CH8_EVAL

Scan configuration

CH8_INTERACT

Scan configuration

CH8_TIMING

Scan configuration

CH9_EVAL

Scan configuration

CH9_INTERACT

Scan configuration

CH9_TIMING

Scan configuration

CHEN

Channel enable Register

CMD

Command Register

CTRL

Control Register

CURCH

Current channel index

DECCTRL

Decoder control Register

DECSTATE

Current decoder state

EVALCTRL

LESENSE evaluation control

IDLECONF

GPIO Idle phase configuration

IEN

Interrupt Enable Register

IF

Interrupt Flag Register

IFC

Interrupt Flag Clear Register

IFS

Interrupt Flag Set Register

PERCTRL

Peripheral Control Register

PRSCTRL

PRS control register

PTR

Result buffer pointers

ROUTEPEN

I/O Routing Register

RegisterBlock

Register block

SCANRES

Scan result register

SENSORSTATE

Decoder input register

ST0_TCONFA

State transition configuration A

ST0_TCONFB

State transition configuration B

ST10_TCONFA

State transition configuration A

ST10_TCONFB

State transition configuration B

ST11_TCONFA

State transition configuration A

ST11_TCONFB

State transition configuration B

ST12_TCONFA

State transition configuration A

ST12_TCONFB

State transition configuration B

ST13_TCONFA

State transition configuration A

ST13_TCONFB

State transition configuration B

ST14_TCONFA

State transition configuration A

ST14_TCONFB

State transition configuration B

ST15_TCONFA

State transition configuration A

ST15_TCONFB

State transition configuration B

ST16_TCONFA

State transition configuration A

ST16_TCONFB

State transition configuration B

ST17_TCONFA

State transition configuration A

ST17_TCONFB

State transition configuration B

ST18_TCONFA

State transition configuration A

ST18_TCONFB

State transition configuration B

ST19_TCONFA

State transition configuration A

ST19_TCONFB

State transition configuration B

ST1_TCONFA

State transition configuration A

ST1_TCONFB

State transition configuration B

ST20_TCONFA

State transition configuration A

ST20_TCONFB

State transition configuration B

ST21_TCONFA

State transition configuration A

ST21_TCONFB

State transition configuration B

ST22_TCONFA

State transition configuration A

ST22_TCONFB

State transition configuration B

ST23_TCONFA

State transition configuration A

ST23_TCONFB

State transition configuration B

ST24_TCONFA

State transition configuration A

ST24_TCONFB

State transition configuration B

ST25_TCONFA

State transition configuration A

ST25_TCONFB

State transition configuration B

ST26_TCONFA

State transition configuration A

ST26_TCONFB

State transition configuration B

ST27_TCONFA

State transition configuration A

ST27_TCONFB

State transition configuration B

ST28_TCONFA

State transition configuration A

ST28_TCONFB

State transition configuration B

ST29_TCONFA

State transition configuration A

ST29_TCONFB

State transition configuration B

ST2_TCONFA

State transition configuration A

ST2_TCONFB

State transition configuration B

ST30_TCONFA

State transition configuration A

ST30_TCONFB

State transition configuration B

ST31_TCONFA

State transition configuration A

ST31_TCONFB

State transition configuration B

ST3_TCONFA

State transition configuration A

ST3_TCONFB

State transition configuration B

ST4_TCONFA

State transition configuration A

ST4_TCONFB

State transition configuration B

ST5_TCONFA

State transition configuration A

ST5_TCONFB

State transition configuration B

ST6_TCONFA

State transition configuration A

ST6_TCONFB

State transition configuration B

ST7_TCONFA

State transition configuration A

ST7_TCONFB

State transition configuration B

ST8_TCONFA

State transition configuration A

ST8_TCONFB

State transition configuration B

ST9_TCONFA

State transition configuration A

ST9_TCONFB

State transition configuration B

STATUS

Status Register

SYNCBUSY

Synchronization Busy Register

TIMCTRL

Timing Control Register