efm32tg11b_pac/efm32tg11b120/pcnt0/
ifs.rs

1#[doc = "Register `IFS` writer"]
2pub struct W(crate::W<IFS_SPEC>);
3impl core::ops::Deref for W {
4    type Target = crate::W<IFS_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl core::ops::DerefMut for W {
11    #[inline(always)]
12    fn deref_mut(&mut self) -> &mut Self::Target {
13        &mut self.0
14    }
15}
16impl From<crate::W<IFS_SPEC>> for W {
17    #[inline(always)]
18    fn from(writer: crate::W<IFS_SPEC>) -> Self {
19        W(writer)
20    }
21}
22#[doc = "Field `UF` writer - Set UF Interrupt Flag"]
23pub type UF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFS_SPEC, bool, O>;
24#[doc = "Field `OF` writer - Set OF Interrupt Flag"]
25pub type OF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFS_SPEC, bool, O>;
26#[doc = "Field `DIRCNG` writer - Set DIRCNG Interrupt Flag"]
27pub type DIRCNG_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFS_SPEC, bool, O>;
28#[doc = "Field `AUXOF` writer - Set AUXOF Interrupt Flag"]
29pub type AUXOF_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFS_SPEC, bool, O>;
30#[doc = "Field `TCC` writer - Set TCC Interrupt Flag"]
31pub type TCC_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFS_SPEC, bool, O>;
32#[doc = "Field `OQSTERR` writer - Set OQSTERR Interrupt Flag"]
33pub type OQSTERR_W<'a, const O: u8> = crate::BitWriter<'a, u32, IFS_SPEC, bool, O>;
34impl W {
35    #[doc = "Bit 0 - Set UF Interrupt Flag"]
36    #[inline(always)]
37    #[must_use]
38    pub fn uf(&mut self) -> UF_W<0> {
39        UF_W::new(self)
40    }
41    #[doc = "Bit 1 - Set OF Interrupt Flag"]
42    #[inline(always)]
43    #[must_use]
44    pub fn of(&mut self) -> OF_W<1> {
45        OF_W::new(self)
46    }
47    #[doc = "Bit 2 - Set DIRCNG Interrupt Flag"]
48    #[inline(always)]
49    #[must_use]
50    pub fn dircng(&mut self) -> DIRCNG_W<2> {
51        DIRCNG_W::new(self)
52    }
53    #[doc = "Bit 3 - Set AUXOF Interrupt Flag"]
54    #[inline(always)]
55    #[must_use]
56    pub fn auxof(&mut self) -> AUXOF_W<3> {
57        AUXOF_W::new(self)
58    }
59    #[doc = "Bit 4 - Set TCC Interrupt Flag"]
60    #[inline(always)]
61    #[must_use]
62    pub fn tcc(&mut self) -> TCC_W<4> {
63        TCC_W::new(self)
64    }
65    #[doc = "Bit 5 - Set OQSTERR Interrupt Flag"]
66    #[inline(always)]
67    #[must_use]
68    pub fn oqsterr(&mut self) -> OQSTERR_W<5> {
69        OQSTERR_W::new(self)
70    }
71    #[doc = "Writes raw bits to the register."]
72    #[inline(always)]
73    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
74        self.0.bits(bits);
75        self
76    }
77}
78#[doc = "Interrupt Flag Set Register\n\nThis register you can [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [ifs](index.html) module"]
79pub struct IFS_SPEC;
80impl crate::RegisterSpec for IFS_SPEC {
81    type Ux = u32;
82}
83#[doc = "`write(|w| ..)` method takes [ifs::W](W) writer structure"]
84impl crate::Writable for IFS_SPEC {
85    type Writer = W;
86    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
87    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
88}
89#[doc = "`reset()` method sets IFS to value 0"]
90impl crate::Resettable for IFS_SPEC {
91    const RESET_VALUE: Self::Ux = 0;
92}
efm32tg11b_pac/efm32tg11b120/pcnt0/ifs.rs

efm32tg11b_pac/efm32tg11b120/pcnt0/
ifs.rs
