Module efm32pg1b_pac::ldma

Linked Direct Memory Access

Modules

• ch0_cfg
  Channel Configuration Register
• ch0_ctrl
  Channel Descriptor Control Word Register
• ch0_dst
  Channel Descriptor Destination Data Address Register
• ch0_link
  Channel Descriptor Link Structure Address Register
• ch0_loop
  Channel Loop Counter Register
• ch0_reqsel
  Channel Peripheral Request Select Register
• ch0_src
  Channel Descriptor Source Data Address Register
• ch1_cfg
  Channel Configuration Register
• ch1_ctrl
  Channel Descriptor Control Word Register
• ch1_dst
  Channel Descriptor Destination Data Address Register
• ch1_link
  Channel Descriptor Link Structure Address Register
• ch1_loop
  Channel Loop Counter Register
• ch1_reqsel
  Channel Peripheral Request Select Register
• ch1_src
  Channel Descriptor Source Data Address Register
• ch2_cfg
  Channel Configuration Register
• ch2_ctrl
  Channel Descriptor Control Word Register
• ch2_dst
  Channel Descriptor Destination Data Address Register
• ch2_link
  Channel Descriptor Link Structure Address Register
• ch2_loop
  Channel Loop Counter Register
• ch2_reqsel
  Channel Peripheral Request Select Register
• ch2_src
  Channel Descriptor Source Data Address Register
• ch3_cfg
  Channel Configuration Register
• ch3_ctrl
  Channel Descriptor Control Word Register
• ch3_dst
  Channel Descriptor Destination Data Address Register
• ch3_link
  Channel Descriptor Link Structure Address Register
• ch3_loop
  Channel Loop Counter Register
• ch3_reqsel
  Channel Peripheral Request Select Register
• ch3_src
  Channel Descriptor Source Data Address Register
• ch4_cfg
  Channel Configuration Register
• ch4_ctrl
  Channel Descriptor Control Word Register
• ch4_dst
  Channel Descriptor Destination Data Address Register
• ch4_link
  Channel Descriptor Link Structure Address Register
• ch4_loop
  Channel Loop Counter Register
• ch4_reqsel
  Channel Peripheral Request Select Register
• ch4_src
  Channel Descriptor Source Data Address Register
• ch5_cfg
  Channel Configuration Register
• ch5_ctrl
  Channel Descriptor Control Word Register
• ch5_dst
  Channel Descriptor Destination Data Address Register
• ch5_link
  Channel Descriptor Link Structure Address Register
• ch5_loop
  Channel Loop Counter Register
• ch5_reqsel
  Channel Peripheral Request Select Register
• ch5_src
  Channel Descriptor Source Data Address Register
• ch6_cfg
  Channel Configuration Register
• ch6_ctrl
  Channel Descriptor Control Word Register
• ch6_dst
  Channel Descriptor Destination Data Address Register
• ch6_link
  Channel Descriptor Link Structure Address Register
• ch6_loop
  Channel Loop Counter Register
• ch6_reqsel
  Channel Peripheral Request Select Register
• ch6_src
  Channel Descriptor Source Data Address Register
• ch7_cfg
  Channel Configuration Register
• ch7_ctrl
  Channel Descriptor Control Word Register
• ch7_dst
  Channel Descriptor Destination Data Address Register
• ch7_link
  Channel Descriptor Link Structure Address Register
• ch7_loop
  Channel Loop Counter Register
• ch7_reqsel
  Channel Peripheral Request Select Register
• ch7_src
  Channel Descriptor Source Data Address Register
• chbusy
  DMA Channel Busy Register
• chdone
  DMA Channel Linking Done Register (Single-Cycle RMW)
• chen
  DMA Channel Enable Register (Single-Cycle RMW)
• ctrl
  DMA Control Register
• dbghalt
  DMA Channel Debug Halt Register
• ien
  Interrupt Enable Register
• if_
  Interrupt Flag Register
• ifc
  Interrupt Flag Clear Register
• ifs
  Interrupt Flag Set Register
• linkload
  DMA Channel Link Load Register
• reqclear
  DMA Channel Request Clear Register
• reqdis
  DMA Channel Request Disable Register
• reqpend
  DMA Channel Requests Pending Register
• status
  DMA Status Register
• swreq
  DMA Channel Software Transfer Request Register
• sync
  DMA Synchronization Trigger Register (Single-Cycle RMW)

Structs

• RegisterBlock
  Register block

Type Aliases

• Ch0Cfg
  CH0_CFG (rw) register accessor: Channel Configuration Register
• Ch0Ctrl
  CH0_CTRL (rw) register accessor: Channel Descriptor Control Word Register
• Ch0Dst
  CH0_DST (rw) register accessor: Channel Descriptor Destination Data Address Register
• Ch0Link
  CH0_LINK (rw) register accessor: Channel Descriptor Link Structure Address Register
• Ch0Loop
  CH0_LOOP (rw) register accessor: Channel Loop Counter Register
• Ch0Reqsel
  CH0_REQSEL (rw) register accessor: Channel Peripheral Request Select Register
• Ch0Src
  CH0_SRC (rw) register accessor: Channel Descriptor Source Data Address Register
• Ch1Cfg
  CH1_CFG (rw) register accessor: Channel Configuration Register
• Ch1Ctrl
  CH1_CTRL (rw) register accessor: Channel Descriptor Control Word Register
• Ch1Dst
  CH1_DST (rw) register accessor: Channel Descriptor Destination Data Address Register
• Ch1Link
  CH1_LINK (rw) register accessor: Channel Descriptor Link Structure Address Register
• Ch1Loop
  CH1_LOOP (rw) register accessor: Channel Loop Counter Register
• Ch1Reqsel
  CH1_REQSEL (rw) register accessor: Channel Peripheral Request Select Register
• Ch1Src
  CH1_SRC (rw) register accessor: Channel Descriptor Source Data Address Register
• Ch2Cfg
  CH2_CFG (rw) register accessor: Channel Configuration Register
• Ch2Ctrl
  CH2_CTRL (rw) register accessor: Channel Descriptor Control Word Register
• Ch2Dst
  CH2_DST (rw) register accessor: Channel Descriptor Destination Data Address Register
• Ch2Link
  CH2_LINK (rw) register accessor: Channel Descriptor Link Structure Address Register
• Ch2Loop
  CH2_LOOP (rw) register accessor: Channel Loop Counter Register
• Ch2Reqsel
  CH2_REQSEL (rw) register accessor: Channel Peripheral Request Select Register
• Ch2Src
  CH2_SRC (rw) register accessor: Channel Descriptor Source Data Address Register
• Ch3Cfg
  CH3_CFG (rw) register accessor: Channel Configuration Register
• Ch3Ctrl
  CH3_CTRL (rw) register accessor: Channel Descriptor Control Word Register
• Ch3Dst
  CH3_DST (rw) register accessor: Channel Descriptor Destination Data Address Register
• Ch3Link
  CH3_LINK (rw) register accessor: Channel Descriptor Link Structure Address Register
• Ch3Loop
  CH3_LOOP (rw) register accessor: Channel Loop Counter Register
• Ch3Reqsel
  CH3_REQSEL (rw) register accessor: Channel Peripheral Request Select Register
• Ch3Src
  CH3_SRC (rw) register accessor: Channel Descriptor Source Data Address Register
• Ch4Cfg
  CH4_CFG (rw) register accessor: Channel Configuration Register
• Ch4Ctrl
  CH4_CTRL (rw) register accessor: Channel Descriptor Control Word Register
• Ch4Dst
  CH4_DST (rw) register accessor: Channel Descriptor Destination Data Address Register
• Ch4Link
  CH4_LINK (rw) register accessor: Channel Descriptor Link Structure Address Register
• Ch4Loop
  CH4_LOOP (rw) register accessor: Channel Loop Counter Register
• Ch4Reqsel
  CH4_REQSEL (rw) register accessor: Channel Peripheral Request Select Register
• Ch4Src
  CH4_SRC (rw) register accessor: Channel Descriptor Source Data Address Register
• Ch5Cfg
  CH5_CFG (rw) register accessor: Channel Configuration Register
• Ch5Ctrl
  CH5_CTRL (rw) register accessor: Channel Descriptor Control Word Register
• Ch5Dst
  CH5_DST (rw) register accessor: Channel Descriptor Destination Data Address Register
• Ch5Link
  CH5_LINK (rw) register accessor: Channel Descriptor Link Structure Address Register
• Ch5Loop
  CH5_LOOP (rw) register accessor: Channel Loop Counter Register
• Ch5Reqsel
  CH5_REQSEL (rw) register accessor: Channel Peripheral Request Select Register
• Ch5Src
  CH5_SRC (rw) register accessor: Channel Descriptor Source Data Address Register
• Ch6Cfg
  CH6_CFG (rw) register accessor: Channel Configuration Register
• Ch6Ctrl
  CH6_CTRL (rw) register accessor: Channel Descriptor Control Word Register
• Ch6Dst
  CH6_DST (rw) register accessor: Channel Descriptor Destination Data Address Register
• Ch6Link
  CH6_LINK (rw) register accessor: Channel Descriptor Link Structure Address Register
• Ch6Loop
  CH6_LOOP (rw) register accessor: Channel Loop Counter Register
• Ch6Reqsel
  CH6_REQSEL (rw) register accessor: Channel Peripheral Request Select Register
• Ch6Src
  CH6_SRC (rw) register accessor: Channel Descriptor Source Data Address Register
• Ch7Cfg
  CH7_CFG (rw) register accessor: Channel Configuration Register
• Ch7Ctrl
  CH7_CTRL (rw) register accessor: Channel Descriptor Control Word Register
• Ch7Dst
  CH7_DST (rw) register accessor: Channel Descriptor Destination Data Address Register
• Ch7Link
  CH7_LINK (rw) register accessor: Channel Descriptor Link Structure Address Register
• Ch7Loop
  CH7_LOOP (rw) register accessor: Channel Loop Counter Register
• Ch7Reqsel
  CH7_REQSEL (rw) register accessor: Channel Peripheral Request Select Register
• Ch7Src
  CH7_SRC (rw) register accessor: Channel Descriptor Source Data Address Register
• Chbusy
  CHBUSY (r) register accessor: DMA Channel Busy Register
• Chdone
  CHDONE (rw) register accessor: DMA Channel Linking Done Register (Single-Cycle RMW)
• Chen
  CHEN (rw) register accessor: DMA Channel Enable Register (Single-Cycle RMW)
• Ctrl
  CTRL (rw) register accessor: DMA Control Register
• Dbghalt
  DBGHALT (rw) register accessor: DMA Channel Debug Halt Register
• Ien
  IEN (rw) register accessor: Interrupt Enable Register
• If
  IF (r) register accessor: Interrupt Flag Register
• Ifc
  IFC (w) register accessor: Interrupt Flag Clear Register
• Ifs
  IFS (w) register accessor: Interrupt Flag Set Register
• Linkload
  LINKLOAD (w) register accessor: DMA Channel Link Load Register
• Reqclear
  REQCLEAR (w) register accessor: DMA Channel Request Clear Register
• Reqdis
  REQDIS (rw) register accessor: DMA Channel Request Disable Register
• Reqpend
  REQPEND (r) register accessor: DMA Channel Requests Pending Register
• Status
  STATUS (r) register accessor: DMA Status Register
• Swreq
  SWREQ (w) register accessor: DMA Channel Software Transfer Request Register
• Sync
  SYNC (rw) register accessor: DMA Synchronization Trigger Register (Single-Cycle RMW)