efm32pg_pac/efm32pg1b200/cmu/
adcctrl.rs

1#[doc = "Register `ADCCTRL` reader"]
2pub struct R(crate::R<ADCCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<ADCCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<ADCCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<ADCCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `ADCCTRL` writer"]
17pub struct W(crate::W<ADCCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<ADCCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<ADCCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<ADCCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `ADC0CLKSEL` reader - ADC0 Clock Select"]
38pub type ADC0CLKSEL_R = crate::FieldReader<u8, ADC0CLKSEL_A>;
39#[doc = "ADC0 Clock Select\n\nValue on reset: 0"]
40#[derive(Clone, Copy, Debug, PartialEq, Eq)]
41#[repr(u8)]
42pub enum ADC0CLKSEL_A {
43    #[doc = "0: ADC0 is not clocked"]
44    DISABLED = 0,
45    #[doc = "1: AUXHFRCO is clocking ADC0"]
46    AUXHFRCO = 1,
47    #[doc = "2: HFXO is clocking ADC0"]
48    HFXO = 2,
49    #[doc = "3: HFSRCCLK is clocking ADC0"]
50    HFSRCCLK = 3,
51}
52impl From<ADC0CLKSEL_A> for u8 {
53    #[inline(always)]
54    fn from(variant: ADC0CLKSEL_A) -> Self {
55        variant as _
56    }
57}
58impl ADC0CLKSEL_R {
59    #[doc = "Get enumerated values variant"]
60    #[inline(always)]
61    pub fn variant(&self) -> ADC0CLKSEL_A {
62        match self.bits {
63            0 => ADC0CLKSEL_A::DISABLED,
64            1 => ADC0CLKSEL_A::AUXHFRCO,
65            2 => ADC0CLKSEL_A::HFXO,
66            3 => ADC0CLKSEL_A::HFSRCCLK,
67            _ => unreachable!(),
68        }
69    }
70    #[doc = "Checks if the value of the field is `DISABLED`"]
71    #[inline(always)]
72    pub fn is_disabled(&self) -> bool {
73        *self == ADC0CLKSEL_A::DISABLED
74    }
75    #[doc = "Checks if the value of the field is `AUXHFRCO`"]
76    #[inline(always)]
77    pub fn is_auxhfrco(&self) -> bool {
78        *self == ADC0CLKSEL_A::AUXHFRCO
79    }
80    #[doc = "Checks if the value of the field is `HFXO`"]
81    #[inline(always)]
82    pub fn is_hfxo(&self) -> bool {
83        *self == ADC0CLKSEL_A::HFXO
84    }
85    #[doc = "Checks if the value of the field is `HFSRCCLK`"]
86    #[inline(always)]
87    pub fn is_hfsrcclk(&self) -> bool {
88        *self == ADC0CLKSEL_A::HFSRCCLK
89    }
90}
91#[doc = "Field `ADC0CLKSEL` writer - ADC0 Clock Select"]
92pub type ADC0CLKSEL_W<'a, const O: u8> =
93    crate::FieldWriterSafe<'a, u32, ADCCTRL_SPEC, u8, ADC0CLKSEL_A, 2, O>;
94impl<'a, const O: u8> ADC0CLKSEL_W<'a, O> {
95    #[doc = "ADC0 is not clocked"]
96    #[inline(always)]
97    pub fn disabled(self) -> &'a mut W {
98        self.variant(ADC0CLKSEL_A::DISABLED)
99    }
100    #[doc = "AUXHFRCO is clocking ADC0"]
101    #[inline(always)]
102    pub fn auxhfrco(self) -> &'a mut W {
103        self.variant(ADC0CLKSEL_A::AUXHFRCO)
104    }
105    #[doc = "HFXO is clocking ADC0"]
106    #[inline(always)]
107    pub fn hfxo(self) -> &'a mut W {
108        self.variant(ADC0CLKSEL_A::HFXO)
109    }
110    #[doc = "HFSRCCLK is clocking ADC0"]
111    #[inline(always)]
112    pub fn hfsrcclk(self) -> &'a mut W {
113        self.variant(ADC0CLKSEL_A::HFSRCCLK)
114    }
115}
116#[doc = "Field `ADC0CLKINV` reader - Invert Clock Selected By ADC0CLKSEL"]
117pub type ADC0CLKINV_R = crate::BitReader<bool>;
118#[doc = "Field `ADC0CLKINV` writer - Invert Clock Selected By ADC0CLKSEL"]
119pub type ADC0CLKINV_W<'a, const O: u8> = crate::BitWriter<'a, u32, ADCCTRL_SPEC, bool, O>;
120impl R {
121    #[doc = "Bits 4:5 - ADC0 Clock Select"]
122    #[inline(always)]
123    pub fn adc0clksel(&self) -> ADC0CLKSEL_R {
124        ADC0CLKSEL_R::new(((self.bits >> 4) & 3) as u8)
125    }
126    #[doc = "Bit 8 - Invert Clock Selected By ADC0CLKSEL"]
127    #[inline(always)]
128    pub fn adc0clkinv(&self) -> ADC0CLKINV_R {
129        ADC0CLKINV_R::new(((self.bits >> 8) & 1) != 0)
130    }
131}
132impl W {
133    #[doc = "Bits 4:5 - ADC0 Clock Select"]
134    #[inline(always)]
135    #[must_use]
136    pub fn adc0clksel(&mut self) -> ADC0CLKSEL_W<4> {
137        ADC0CLKSEL_W::new(self)
138    }
139    #[doc = "Bit 8 - Invert Clock Selected By ADC0CLKSEL"]
140    #[inline(always)]
141    #[must_use]
142    pub fn adc0clkinv(&mut self) -> ADC0CLKINV_W<8> {
143        ADC0CLKINV_W::new(self)
144    }
145    #[doc = "Writes raw bits to the register."]
146    #[inline(always)]
147    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
148        self.0.bits(bits);
149        self
150    }
151}
152#[doc = "ADC Control Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [adcctrl](index.html) module"]
153pub struct ADCCTRL_SPEC;
154impl crate::RegisterSpec for ADCCTRL_SPEC {
155    type Ux = u32;
156}
157#[doc = "`read()` method returns [adcctrl::R](R) reader structure"]
158impl crate::Readable for ADCCTRL_SPEC {
159    type Reader = R;
160}
161#[doc = "`write(|w| ..)` method takes [adcctrl::W](W) writer structure"]
162impl crate::Writable for ADCCTRL_SPEC {
163    type Writer = W;
164    const ZERO_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
165    const ONE_TO_MODIFY_FIELDS_BITMAP: Self::Ux = 0;
166}
167#[doc = "`reset()` method sets ADCCTRL to value 0"]
168impl crate::Resettable for ADCCTRL_SPEC {
169    const RESET_VALUE: Self::Ux = 0;
170}
efm32pg_pac/efm32pg1b200/cmu/adcctrl.rs

efm32pg_pac/efm32pg1b200/cmu/
adcctrl.rs
