efm32gg12b830_pac/qspi0/
flashcmdctrl.rs

1#[doc = "Register `FLASHCMDCTRL` reader"]
2pub struct R(crate::R<FLASHCMDCTRL_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<FLASHCMDCTRL_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<FLASHCMDCTRL_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<FLASHCMDCTRL_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `FLASHCMDCTRL` writer"]
17pub struct W(crate::W<FLASHCMDCTRL_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<FLASHCMDCTRL_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<FLASHCMDCTRL_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<FLASHCMDCTRL_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `CMDEXEC` writer - Execute the Command"]
38pub type CMDEXEC_W<'a> = crate::BitWriter<'a, u32, FLASHCMDCTRL_SPEC, bool, 0>;
39#[doc = "Field `CMDEXECSTATUS` reader - Command Execution in Progress"]
40pub type CMDEXECSTATUS_R = crate::BitReader<bool>;
41#[doc = "Field `STIGMEMBANKEN` reader - STIG Memory Bank Enable Bit"]
42pub type STIGMEMBANKEN_R = crate::BitReader<bool>;
43#[doc = "Field `STIGMEMBANKEN` writer - STIG Memory Bank Enable Bit"]
44pub type STIGMEMBANKEN_W<'a> = crate::BitWriter<'a, u32, FLASHCMDCTRL_SPEC, bool, 2>;
45#[doc = "Field `NUMDUMMYCYCLES` reader - Number of Dummy Cycles"]
46pub type NUMDUMMYCYCLES_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `NUMDUMMYCYCLES` writer - Number of Dummy Cycles"]
48pub type NUMDUMMYCYCLES_W<'a> = crate::FieldWriter<'a, u32, FLASHCMDCTRL_SPEC, u8, u8, 5, 7>;
49#[doc = "Field `NUMWRDATABYTES` reader - Number of Write Data Bytes"]
50pub type NUMWRDATABYTES_R = crate::FieldReader<u8, u8>;
51#[doc = "Field `NUMWRDATABYTES` writer - Number of Write Data Bytes"]
52pub type NUMWRDATABYTES_W<'a> = crate::FieldWriter<'a, u32, FLASHCMDCTRL_SPEC, u8, u8, 3, 12>;
53#[doc = "Field `ENBWRITEDATA` reader - Write Data Enable"]
54pub type ENBWRITEDATA_R = crate::BitReader<bool>;
55#[doc = "Field `ENBWRITEDATA` writer - Write Data Enable"]
56pub type ENBWRITEDATA_W<'a> = crate::BitWriter<'a, u32, FLASHCMDCTRL_SPEC, bool, 15>;
57#[doc = "Field `NUMADDRBYTES` reader - Number of Address Bytes"]
58pub type NUMADDRBYTES_R = crate::FieldReader<u8, u8>;
59#[doc = "Field `NUMADDRBYTES` writer - Number of Address Bytes"]
60pub type NUMADDRBYTES_W<'a> = crate::FieldWriter<'a, u32, FLASHCMDCTRL_SPEC, u8, u8, 2, 16>;
61#[doc = "Field `ENBMODEBIT` reader - Mode Bit Enable"]
62pub type ENBMODEBIT_R = crate::BitReader<bool>;
63#[doc = "Field `ENBMODEBIT` writer - Mode Bit Enable"]
64pub type ENBMODEBIT_W<'a> = crate::BitWriter<'a, u32, FLASHCMDCTRL_SPEC, bool, 18>;
65#[doc = "Field `ENBCOMDADDR` reader - Command Address Enable"]
66pub type ENBCOMDADDR_R = crate::BitReader<bool>;
67#[doc = "Field `ENBCOMDADDR` writer - Command Address Enable"]
68pub type ENBCOMDADDR_W<'a> = crate::BitWriter<'a, u32, FLASHCMDCTRL_SPEC, bool, 19>;
69#[doc = "Field `NUMRDDATABYTES` reader - Number of Read Data Bytes"]
70pub type NUMRDDATABYTES_R = crate::FieldReader<u8, u8>;
71#[doc = "Field `NUMRDDATABYTES` writer - Number of Read Data Bytes"]
72pub type NUMRDDATABYTES_W<'a> = crate::FieldWriter<'a, u32, FLASHCMDCTRL_SPEC, u8, u8, 3, 20>;
73#[doc = "Field `ENBREADDATA` reader - Read Data Enable"]
74pub type ENBREADDATA_R = crate::BitReader<bool>;
75#[doc = "Field `ENBREADDATA` writer - Read Data Enable"]
76pub type ENBREADDATA_W<'a> = crate::BitWriter<'a, u32, FLASHCMDCTRL_SPEC, bool, 23>;
77#[doc = "Field `CMDOPCODE` reader - Command Opcode"]
78pub type CMDOPCODE_R = crate::FieldReader<u8, u8>;
79#[doc = "Field `CMDOPCODE` writer - Command Opcode"]
80pub type CMDOPCODE_W<'a> = crate::FieldWriter<'a, u32, FLASHCMDCTRL_SPEC, u8, u8, 8, 24>;
81impl R {
82    #[doc = "Bit 1 - Command Execution in Progress"]
83    #[inline(always)]
84    pub fn cmdexecstatus(&self) -> CMDEXECSTATUS_R {
85        CMDEXECSTATUS_R::new(((self.bits >> 1) & 1) != 0)
86    }
87    #[doc = "Bit 2 - STIG Memory Bank Enable Bit"]
88    #[inline(always)]
89    pub fn stigmembanken(&self) -> STIGMEMBANKEN_R {
90        STIGMEMBANKEN_R::new(((self.bits >> 2) & 1) != 0)
91    }
92    #[doc = "Bits 7:11 - Number of Dummy Cycles"]
93    #[inline(always)]
94    pub fn numdummycycles(&self) -> NUMDUMMYCYCLES_R {
95        NUMDUMMYCYCLES_R::new(((self.bits >> 7) & 0x1f) as u8)
96    }
97    #[doc = "Bits 12:14 - Number of Write Data Bytes"]
98    #[inline(always)]
99    pub fn numwrdatabytes(&self) -> NUMWRDATABYTES_R {
100        NUMWRDATABYTES_R::new(((self.bits >> 12) & 7) as u8)
101    }
102    #[doc = "Bit 15 - Write Data Enable"]
103    #[inline(always)]
104    pub fn enbwritedata(&self) -> ENBWRITEDATA_R {
105        ENBWRITEDATA_R::new(((self.bits >> 15) & 1) != 0)
106    }
107    #[doc = "Bits 16:17 - Number of Address Bytes"]
108    #[inline(always)]
109    pub fn numaddrbytes(&self) -> NUMADDRBYTES_R {
110        NUMADDRBYTES_R::new(((self.bits >> 16) & 3) as u8)
111    }
112    #[doc = "Bit 18 - Mode Bit Enable"]
113    #[inline(always)]
114    pub fn enbmodebit(&self) -> ENBMODEBIT_R {
115        ENBMODEBIT_R::new(((self.bits >> 18) & 1) != 0)
116    }
117    #[doc = "Bit 19 - Command Address Enable"]
118    #[inline(always)]
119    pub fn enbcomdaddr(&self) -> ENBCOMDADDR_R {
120        ENBCOMDADDR_R::new(((self.bits >> 19) & 1) != 0)
121    }
122    #[doc = "Bits 20:22 - Number of Read Data Bytes"]
123    #[inline(always)]
124    pub fn numrddatabytes(&self) -> NUMRDDATABYTES_R {
125        NUMRDDATABYTES_R::new(((self.bits >> 20) & 7) as u8)
126    }
127    #[doc = "Bit 23 - Read Data Enable"]
128    #[inline(always)]
129    pub fn enbreaddata(&self) -> ENBREADDATA_R {
130        ENBREADDATA_R::new(((self.bits >> 23) & 1) != 0)
131    }
132    #[doc = "Bits 24:31 - Command Opcode"]
133    #[inline(always)]
134    pub fn cmdopcode(&self) -> CMDOPCODE_R {
135        CMDOPCODE_R::new(((self.bits >> 24) & 0xff) as u8)
136    }
137}
138impl W {
139    #[doc = "Bit 0 - Execute the Command"]
140    #[inline(always)]
141    pub fn cmdexec(&mut self) -> CMDEXEC_W {
142        CMDEXEC_W::new(self)
143    }
144    #[doc = "Bit 2 - STIG Memory Bank Enable Bit"]
145    #[inline(always)]
146    pub fn stigmembanken(&mut self) -> STIGMEMBANKEN_W {
147        STIGMEMBANKEN_W::new(self)
148    }
149    #[doc = "Bits 7:11 - Number of Dummy Cycles"]
150    #[inline(always)]
151    pub fn numdummycycles(&mut self) -> NUMDUMMYCYCLES_W {
152        NUMDUMMYCYCLES_W::new(self)
153    }
154    #[doc = "Bits 12:14 - Number of Write Data Bytes"]
155    #[inline(always)]
156    pub fn numwrdatabytes(&mut self) -> NUMWRDATABYTES_W {
157        NUMWRDATABYTES_W::new(self)
158    }
159    #[doc = "Bit 15 - Write Data Enable"]
160    #[inline(always)]
161    pub fn enbwritedata(&mut self) -> ENBWRITEDATA_W {
162        ENBWRITEDATA_W::new(self)
163    }
164    #[doc = "Bits 16:17 - Number of Address Bytes"]
165    #[inline(always)]
166    pub fn numaddrbytes(&mut self) -> NUMADDRBYTES_W {
167        NUMADDRBYTES_W::new(self)
168    }
169    #[doc = "Bit 18 - Mode Bit Enable"]
170    #[inline(always)]
171    pub fn enbmodebit(&mut self) -> ENBMODEBIT_W {
172        ENBMODEBIT_W::new(self)
173    }
174    #[doc = "Bit 19 - Command Address Enable"]
175    #[inline(always)]
176    pub fn enbcomdaddr(&mut self) -> ENBCOMDADDR_W {
177        ENBCOMDADDR_W::new(self)
178    }
179    #[doc = "Bits 20:22 - Number of Read Data Bytes"]
180    #[inline(always)]
181    pub fn numrddatabytes(&mut self) -> NUMRDDATABYTES_W {
182        NUMRDDATABYTES_W::new(self)
183    }
184    #[doc = "Bit 23 - Read Data Enable"]
185    #[inline(always)]
186    pub fn enbreaddata(&mut self) -> ENBREADDATA_W {
187        ENBREADDATA_W::new(self)
188    }
189    #[doc = "Bits 24:31 - Command Opcode"]
190    #[inline(always)]
191    pub fn cmdopcode(&mut self) -> CMDOPCODE_W {
192        CMDOPCODE_W::new(self)
193    }
194    #[doc = "Writes raw bits to the register."]
195    #[inline(always)]
196    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
197        self.0.bits(bits);
198        self
199    }
200}
201#[doc = "Flash Command Control Register (STIG)\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [flashcmdctrl](index.html) module"]
202pub struct FLASHCMDCTRL_SPEC;
203impl crate::RegisterSpec for FLASHCMDCTRL_SPEC {
204    type Ux = u32;
205}
206#[doc = "`read()` method returns [flashcmdctrl::R](R) reader structure"]
207impl crate::Readable for FLASHCMDCTRL_SPEC {
208    type Reader = R;
209}
210#[doc = "`write(|w| ..)` method takes [flashcmdctrl::W](W) writer structure"]
211impl crate::Writable for FLASHCMDCTRL_SPEC {
212    type Writer = W;
213}
214#[doc = "`reset()` method sets FLASHCMDCTRL to value 0"]
215impl crate::Resettable for FLASHCMDCTRL_SPEC {
216    #[inline(always)]
217    fn reset_value() -> Self::Ux {
218        0
219    }
220}
efm32gg12b830_pac/qspi0/flashcmdctrl.rs

efm32gg12b830_pac/qspi0/
flashcmdctrl.rs
