efm32gg12b830_pac/qspi0/
devinstrwrconfig.rs

1#[doc = "Register `DEVINSTRWRCONFIG` reader"]
2pub struct R(crate::R<DEVINSTRWRCONFIG_SPEC>);
3impl core::ops::Deref for R {
4    type Target = crate::R<DEVINSTRWRCONFIG_SPEC>;
5    #[inline(always)]
6    fn deref(&self) -> &Self::Target {
7        &self.0
8    }
9}
10impl From<crate::R<DEVINSTRWRCONFIG_SPEC>> for R {
11    #[inline(always)]
12    fn from(reader: crate::R<DEVINSTRWRCONFIG_SPEC>) -> Self {
13        R(reader)
14    }
15}
16#[doc = "Register `DEVINSTRWRCONFIG` writer"]
17pub struct W(crate::W<DEVINSTRWRCONFIG_SPEC>);
18impl core::ops::Deref for W {
19    type Target = crate::W<DEVINSTRWRCONFIG_SPEC>;
20    #[inline(always)]
21    fn deref(&self) -> &Self::Target {
22        &self.0
23    }
24}
25impl core::ops::DerefMut for W {
26    #[inline(always)]
27    fn deref_mut(&mut self) -> &mut Self::Target {
28        &mut self.0
29    }
30}
31impl From<crate::W<DEVINSTRWRCONFIG_SPEC>> for W {
32    #[inline(always)]
33    fn from(writer: crate::W<DEVINSTRWRCONFIG_SPEC>) -> Self {
34        W(writer)
35    }
36}
37#[doc = "Field `WROPCODE` reader - Write Opcode"]
38pub type WROPCODE_R = crate::FieldReader<u8, u8>;
39#[doc = "Field `WROPCODE` writer - Write Opcode"]
40pub type WROPCODE_W<'a> = crate::FieldWriter<'a, u32, DEVINSTRWRCONFIG_SPEC, u8, u8, 8, 0>;
41#[doc = "Field `WELDIS` reader - WEL Disable"]
42pub type WELDIS_R = crate::BitReader<bool>;
43#[doc = "Field `WELDIS` writer - WEL Disable"]
44pub type WELDIS_W<'a> = crate::BitWriter<'a, u32, DEVINSTRWRCONFIG_SPEC, bool, 8>;
45#[doc = "Field `ADDRXFERTYPESTDMODE` reader - Address Transfer Type for Standard SPI Modes"]
46pub type ADDRXFERTYPESTDMODE_R = crate::FieldReader<u8, u8>;
47#[doc = "Field `ADDRXFERTYPESTDMODE` writer - Address Transfer Type for Standard SPI Modes"]
48pub type ADDRXFERTYPESTDMODE_W<'a> =
49    crate::FieldWriter<'a, u32, DEVINSTRWRCONFIG_SPEC, u8, u8, 2, 12>;
50#[doc = "Field `DATAXFERTYPEEXTMODE` reader - Data Transfer Type for Standard SPI Modes"]
51pub type DATAXFERTYPEEXTMODE_R = crate::FieldReader<u8, u8>;
52#[doc = "Field `DATAXFERTYPEEXTMODE` writer - Data Transfer Type for Standard SPI Modes"]
53pub type DATAXFERTYPEEXTMODE_W<'a> =
54    crate::FieldWriter<'a, u32, DEVINSTRWRCONFIG_SPEC, u8, u8, 2, 16>;
55#[doc = "Field `DUMMYWRCLKCYCLES` reader - Dummy Write Clock Cycles"]
56pub type DUMMYWRCLKCYCLES_R = crate::FieldReader<u8, u8>;
57#[doc = "Field `DUMMYWRCLKCYCLES` writer - Dummy Write Clock Cycles"]
58pub type DUMMYWRCLKCYCLES_W<'a> = crate::FieldWriter<'a, u32, DEVINSTRWRCONFIG_SPEC, u8, u8, 5, 24>;
59impl R {
60    #[doc = "Bits 0:7 - Write Opcode"]
61    #[inline(always)]
62    pub fn wropcode(&self) -> WROPCODE_R {
63        WROPCODE_R::new((self.bits & 0xff) as u8)
64    }
65    #[doc = "Bit 8 - WEL Disable"]
66    #[inline(always)]
67    pub fn weldis(&self) -> WELDIS_R {
68        WELDIS_R::new(((self.bits >> 8) & 1) != 0)
69    }
70    #[doc = "Bits 12:13 - Address Transfer Type for Standard SPI Modes"]
71    #[inline(always)]
72    pub fn addrxfertypestdmode(&self) -> ADDRXFERTYPESTDMODE_R {
73        ADDRXFERTYPESTDMODE_R::new(((self.bits >> 12) & 3) as u8)
74    }
75    #[doc = "Bits 16:17 - Data Transfer Type for Standard SPI Modes"]
76    #[inline(always)]
77    pub fn dataxfertypeextmode(&self) -> DATAXFERTYPEEXTMODE_R {
78        DATAXFERTYPEEXTMODE_R::new(((self.bits >> 16) & 3) as u8)
79    }
80    #[doc = "Bits 24:28 - Dummy Write Clock Cycles"]
81    #[inline(always)]
82    pub fn dummywrclkcycles(&self) -> DUMMYWRCLKCYCLES_R {
83        DUMMYWRCLKCYCLES_R::new(((self.bits >> 24) & 0x1f) as u8)
84    }
85}
86impl W {
87    #[doc = "Bits 0:7 - Write Opcode"]
88    #[inline(always)]
89    pub fn wropcode(&mut self) -> WROPCODE_W {
90        WROPCODE_W::new(self)
91    }
92    #[doc = "Bit 8 - WEL Disable"]
93    #[inline(always)]
94    pub fn weldis(&mut self) -> WELDIS_W {
95        WELDIS_W::new(self)
96    }
97    #[doc = "Bits 12:13 - Address Transfer Type for Standard SPI Modes"]
98    #[inline(always)]
99    pub fn addrxfertypestdmode(&mut self) -> ADDRXFERTYPESTDMODE_W {
100        ADDRXFERTYPESTDMODE_W::new(self)
101    }
102    #[doc = "Bits 16:17 - Data Transfer Type for Standard SPI Modes"]
103    #[inline(always)]
104    pub fn dataxfertypeextmode(&mut self) -> DATAXFERTYPEEXTMODE_W {
105        DATAXFERTYPEEXTMODE_W::new(self)
106    }
107    #[doc = "Bits 24:28 - Dummy Write Clock Cycles"]
108    #[inline(always)]
109    pub fn dummywrclkcycles(&mut self) -> DUMMYWRCLKCYCLES_W {
110        DUMMYWRCLKCYCLES_W::new(self)
111    }
112    #[doc = "Writes raw bits to the register."]
113    #[inline(always)]
114    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
115        self.0.bits(bits);
116        self
117    }
118}
119#[doc = "Device Write Instruction Configuration Register\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [devinstrwrconfig](index.html) module"]
120pub struct DEVINSTRWRCONFIG_SPEC;
121impl crate::RegisterSpec for DEVINSTRWRCONFIG_SPEC {
122    type Ux = u32;
123}
124#[doc = "`read()` method returns [devinstrwrconfig::R](R) reader structure"]
125impl crate::Readable for DEVINSTRWRCONFIG_SPEC {
126    type Reader = R;
127}
128#[doc = "`write(|w| ..)` method takes [devinstrwrconfig::W](W) writer structure"]
129impl crate::Writable for DEVINSTRWRCONFIG_SPEC {
130    type Writer = W;
131}
132#[doc = "`reset()` method sets DEVINSTRWRCONFIG to value 0x02"]
133impl crate::Resettable for DEVINSTRWRCONFIG_SPEC {
134    #[inline(always)]
135    fn reset_value() -> Self::Ux {
136        0x02
137    }
138}
efm32gg12b830_pac/qspi0/devinstrwrconfig.rs

efm32gg12b830_pac/qspi0/
devinstrwrconfig.rs
