[−][src]Module efm32gg11b820::ldma
LDMA
Modules
| ch0_cfg | Channel Configuration Register |
| ch0_src | Channel Descriptor Source Data Address Register |
| ch0_dst | Channel Descriptor Destination Data Address Register |
| ch0_loop | Channel Loop Counter Register |
| ch0_ctrl | Channel Descriptor Control Word Register |
| ch0_link | Channel Descriptor Link Structure Address Register |
| ch0_reqsel | Channel Peripheral Request Select Register |
| ch1_reqsel | Channel Peripheral Request Select Register |
| ch1_cfg | Channel Configuration Register |
| ch1_loop | Channel Loop Counter Register |
| ch1_ctrl | Channel Descriptor Control Word Register |
| ch1_src | Channel Descriptor Source Data Address Register |
| ch1_dst | Channel Descriptor Destination Data Address Register |
| ch1_link | Channel Descriptor Link Structure Address Register |
| ch2_reqsel | Channel Peripheral Request Select Register |
| ch2_cfg | Channel Configuration Register |
| ch2_loop | Channel Loop Counter Register |
| ch2_ctrl | Channel Descriptor Control Word Register |
| ch2_src | Channel Descriptor Source Data Address Register |
| ch2_dst | Channel Descriptor Destination Data Address Register |
| ch2_link | Channel Descriptor Link Structure Address Register |
| ch3_reqsel | Channel Peripheral Request Select Register |
| ch3_cfg | Channel Configuration Register |
| ch3_loop | Channel Loop Counter Register |
| ch3_ctrl | Channel Descriptor Control Word Register |
| ch3_src | Channel Descriptor Source Data Address Register |
| ch3_dst | Channel Descriptor Destination Data Address Register |
| ch3_link | Channel Descriptor Link Structure Address Register |
| ch4_reqsel | Channel Peripheral Request Select Register |
| ch4_cfg | Channel Configuration Register |
| ch4_loop | Channel Loop Counter Register |
| ch4_ctrl | Channel Descriptor Control Word Register |
| ch4_src | Channel Descriptor Source Data Address Register |
| ch4_dst | Channel Descriptor Destination Data Address Register |
| ch4_link | Channel Descriptor Link Structure Address Register |
| ch5_reqsel | Channel Peripheral Request Select Register |
| ch5_cfg | Channel Configuration Register |
| ch5_loop | Channel Loop Counter Register |
| ch5_ctrl | Channel Descriptor Control Word Register |
| ch5_src | Channel Descriptor Source Data Address Register |
| ch5_dst | Channel Descriptor Destination Data Address Register |
| ch5_link | Channel Descriptor Link Structure Address Register |
| ch6_reqsel | Channel Peripheral Request Select Register |
| ch6_cfg | Channel Configuration Register |
| ch6_loop | Channel Loop Counter Register |
| ch6_ctrl | Channel Descriptor Control Word Register |
| ch6_src | Channel Descriptor Source Data Address Register |
| ch6_dst | Channel Descriptor Destination Data Address Register |
| ch6_link | Channel Descriptor Link Structure Address Register |
| ch7_reqsel | Channel Peripheral Request Select Register |
| ch7_cfg | Channel Configuration Register |
| ch7_loop | Channel Loop Counter Register |
| ch7_ctrl | Channel Descriptor Control Word Register |
| ch7_src | Channel Descriptor Source Data Address Register |
| ch7_dst | Channel Descriptor Destination Data Address Register |
| ch7_link | Channel Descriptor Link Structure Address Register |
| ch8_reqsel | Channel Peripheral Request Select Register |
| ch8_cfg | Channel Configuration Register |
| ch8_loop | Channel Loop Counter Register |
| ch8_ctrl | Channel Descriptor Control Word Register |
| ch8_src | Channel Descriptor Source Data Address Register |
| ch8_dst | Channel Descriptor Destination Data Address Register |
| ch8_link | Channel Descriptor Link Structure Address Register |
| ch9_reqsel | Channel Peripheral Request Select Register |
| ch9_cfg | Channel Configuration Register |
| ch9_loop | Channel Loop Counter Register |
| ch9_ctrl | Channel Descriptor Control Word Register |
| ch9_src | Channel Descriptor Source Data Address Register |
| ch9_dst | Channel Descriptor Destination Data Address Register |
| ch9_link | Channel Descriptor Link Structure Address Register |
| ch10_reqsel | Channel Peripheral Request Select Register |
| ch10_cfg | Channel Configuration Register |
| ch10_loop | Channel Loop Counter Register |
| ch10_ctrl | Channel Descriptor Control Word Register |
| ch10_src | Channel Descriptor Source Data Address Register |
| ch10_dst | Channel Descriptor Destination Data Address Register |
| ch10_link | Channel Descriptor Link Structure Address Register |
| ch11_reqsel | Channel Peripheral Request Select Register |
| ch11_cfg | Channel Configuration Register |
| ch11_loop | Channel Loop Counter Register |
| ch11_ctrl | Channel Descriptor Control Word Register |
| ch11_src | Channel Descriptor Source Data Address Register |
| ch11_dst | Channel Descriptor Destination Data Address Register |
| ch11_link | Channel Descriptor Link Structure Address Register |
| ch12_reqsel | Channel Peripheral Request Select Register |
| ch12_cfg | Channel Configuration Register |
| ch12_loop | Channel Loop Counter Register |
| ch12_ctrl | Channel Descriptor Control Word Register |
| ch12_src | Channel Descriptor Source Data Address Register |
| ch12_dst | Channel Descriptor Destination Data Address Register |
| ch12_link | Channel Descriptor Link Structure Address Register |
| ch13_reqsel | Channel Peripheral Request Select Register |
| ch13_cfg | Channel Configuration Register |
| ch13_loop | Channel Loop Counter Register |
| ch13_ctrl | Channel Descriptor Control Word Register |
| ch13_src | Channel Descriptor Source Data Address Register |
| ch13_dst | Channel Descriptor Destination Data Address Register |
| ch13_link | Channel Descriptor Link Structure Address Register |
| ch14_reqsel | Channel Peripheral Request Select Register |
| ch14_cfg | Channel Configuration Register |
| ch14_loop | Channel Loop Counter Register |
| ch14_ctrl | Channel Descriptor Control Word Register |
| ch14_src | Channel Descriptor Source Data Address Register |
| ch14_dst | Channel Descriptor Destination Data Address Register |
| ch14_link | Channel Descriptor Link Structure Address Register |
| ch15_reqsel | Channel Peripheral Request Select Register |
| ch15_cfg | Channel Configuration Register |
| ch15_loop | Channel Loop Counter Register |
| ch15_ctrl | Channel Descriptor Control Word Register |
| ch15_src | Channel Descriptor Source Data Address Register |
| ch15_dst | Channel Descriptor Destination Data Address Register |
| ch15_link | Channel Descriptor Link Structure Address Register |
| ch16_reqsel | Channel Peripheral Request Select Register |
| ch16_cfg | Channel Configuration Register |
| ch16_loop | Channel Loop Counter Register |
| ch16_ctrl | Channel Descriptor Control Word Register |
| ch16_src | Channel Descriptor Source Data Address Register |
| ch16_dst | Channel Descriptor Destination Data Address Register |
| ch16_link | Channel Descriptor Link Structure Address Register |
| ch17_reqsel | Channel Peripheral Request Select Register |
| ch17_cfg | Channel Configuration Register |
| ch17_loop | Channel Loop Counter Register |
| ch17_ctrl | Channel Descriptor Control Word Register |
| ch17_src | Channel Descriptor Source Data Address Register |
| ch17_dst | Channel Descriptor Destination Data Address Register |
| ch17_link | Channel Descriptor Link Structure Address Register |
| ch18_reqsel | Channel Peripheral Request Select Register |
| ch18_cfg | Channel Configuration Register |
| ch18_loop | Channel Loop Counter Register |
| ch18_ctrl | Channel Descriptor Control Word Register |
| ch18_src | Channel Descriptor Source Data Address Register |
| ch18_dst | Channel Descriptor Destination Data Address Register |
| ch18_link | Channel Descriptor Link Structure Address Register |
| ch19_reqsel | Channel Peripheral Request Select Register |
| ch19_cfg | Channel Configuration Register |
| ch19_loop | Channel Loop Counter Register |
| ch19_ctrl | Channel Descriptor Control Word Register |
| ch19_src | Channel Descriptor Source Data Address Register |
| ch19_dst | Channel Descriptor Destination Data Address Register |
| ch19_link | Channel Descriptor Link Structure Address Register |
| ch20_reqsel | Channel Peripheral Request Select Register |
| ch20_cfg | Channel Configuration Register |
| ch20_loop | Channel Loop Counter Register |
| ch20_ctrl | Channel Descriptor Control Word Register |
| ch20_src | Channel Descriptor Source Data Address Register |
| ch20_dst | Channel Descriptor Destination Data Address Register |
| ch20_link | Channel Descriptor Link Structure Address Register |
| ch21_reqsel | Channel Peripheral Request Select Register |
| ch21_cfg | Channel Configuration Register |
| ch21_loop | Channel Loop Counter Register |
| ch21_ctrl | Channel Descriptor Control Word Register |
| ch21_src | Channel Descriptor Source Data Address Register |
| ch21_dst | Channel Descriptor Destination Data Address Register |
| ch21_link | Channel Descriptor Link Structure Address Register |
| ch22_reqsel | Channel Peripheral Request Select Register |
| ch22_cfg | Channel Configuration Register |
| ch22_loop | Channel Loop Counter Register |
| ch22_ctrl | Channel Descriptor Control Word Register |
| ch22_src | Channel Descriptor Source Data Address Register |
| ch22_dst | Channel Descriptor Destination Data Address Register |
| ch22_link | Channel Descriptor Link Structure Address Register |
| ch23_reqsel | Channel Peripheral Request Select Register |
| ch23_cfg | Channel Configuration Register |
| ch23_loop | Channel Loop Counter Register |
| ch23_ctrl | Channel Descriptor Control Word Register |
| ch23_src | Channel Descriptor Source Data Address Register |
| ch23_dst | Channel Descriptor Destination Data Address Register |
| ch23_link | Channel Descriptor Link Structure Address Register |
| chbusy | DMA Channel Busy Register |
| chdone | DMA Channel Linking Done Register (Single-Cycle RMW) |
| chen | DMA Channel Enable Register (Single-Cycle RMW) |
| ctrl | DMA Control Register |
| dbghalt | DMA Channel Debug Halt Register |
| ien | Interrupt Enable Register |
| if_ | Interrupt Flag Register |
| ifc | Interrupt Flag Clear Register |
| ifs | Interrupt Flag Set Register |
| linkload | DMA Channel Link Load Register |
| reqclear | DMA Channel Request Clear Register |
| reqdis | DMA Channel Request Disable Register |
| reqpend | DMA Channel Requests Pending Register |
| status | DMA Status Register |
| swreq | DMA Channel Software Transfer Request Register |
| sync | DMA Synchronization Trigger Register (Single-Cycle RMW) |
Structs
| CH0_CFG | Channel Configuration Register |
| CH0_SRC | Channel Descriptor Source Data Address Register |
| CH0_DST | Channel Descriptor Destination Data Address Register |
| CH0_LOOP | Channel Loop Counter Register |
| CH0_CTRL | Channel Descriptor Control Word Register |
| CH0_LINK | Channel Descriptor Link Structure Address Register |
| CH0_REQSEL | Channel Peripheral Request Select Register |
| CH1_REQSEL | Channel Peripheral Request Select Register |
| CH1_CFG | Channel Configuration Register |
| CH1_LOOP | Channel Loop Counter Register |
| CH1_CTRL | Channel Descriptor Control Word Register |
| CH1_SRC | Channel Descriptor Source Data Address Register |
| CH1_DST | Channel Descriptor Destination Data Address Register |
| CH1_LINK | Channel Descriptor Link Structure Address Register |
| CH2_REQSEL | Channel Peripheral Request Select Register |
| CH2_CFG | Channel Configuration Register |
| CH2_LOOP | Channel Loop Counter Register |
| CH2_CTRL | Channel Descriptor Control Word Register |
| CH2_SRC | Channel Descriptor Source Data Address Register |
| CH2_DST | Channel Descriptor Destination Data Address Register |
| CH2_LINK | Channel Descriptor Link Structure Address Register |
| CH3_REQSEL | Channel Peripheral Request Select Register |
| CH3_CFG | Channel Configuration Register |
| CH3_LOOP | Channel Loop Counter Register |
| CH3_CTRL | Channel Descriptor Control Word Register |
| CH3_SRC | Channel Descriptor Source Data Address Register |
| CH3_DST | Channel Descriptor Destination Data Address Register |
| CH3_LINK | Channel Descriptor Link Structure Address Register |
| CH4_REQSEL | Channel Peripheral Request Select Register |
| CH4_CFG | Channel Configuration Register |
| CH4_LOOP | Channel Loop Counter Register |
| CH4_CTRL | Channel Descriptor Control Word Register |
| CH4_SRC | Channel Descriptor Source Data Address Register |
| CH4_DST | Channel Descriptor Destination Data Address Register |
| CH4_LINK | Channel Descriptor Link Structure Address Register |
| CH5_REQSEL | Channel Peripheral Request Select Register |
| CH5_CFG | Channel Configuration Register |
| CH5_LOOP | Channel Loop Counter Register |
| CH5_CTRL | Channel Descriptor Control Word Register |
| CH5_SRC | Channel Descriptor Source Data Address Register |
| CH5_DST | Channel Descriptor Destination Data Address Register |
| CH5_LINK | Channel Descriptor Link Structure Address Register |
| CH6_REQSEL | Channel Peripheral Request Select Register |
| CH6_CFG | Channel Configuration Register |
| CH6_LOOP | Channel Loop Counter Register |
| CH6_CTRL | Channel Descriptor Control Word Register |
| CH6_SRC | Channel Descriptor Source Data Address Register |
| CH6_DST | Channel Descriptor Destination Data Address Register |
| CH6_LINK | Channel Descriptor Link Structure Address Register |
| CH7_REQSEL | Channel Peripheral Request Select Register |
| CH7_CFG | Channel Configuration Register |
| CH7_LOOP | Channel Loop Counter Register |
| CH7_CTRL | Channel Descriptor Control Word Register |
| CH7_SRC | Channel Descriptor Source Data Address Register |
| CH7_DST | Channel Descriptor Destination Data Address Register |
| CH7_LINK | Channel Descriptor Link Structure Address Register |
| CH8_REQSEL | Channel Peripheral Request Select Register |
| CH8_CFG | Channel Configuration Register |
| CH8_LOOP | Channel Loop Counter Register |
| CH8_CTRL | Channel Descriptor Control Word Register |
| CH8_SRC | Channel Descriptor Source Data Address Register |
| CH8_DST | Channel Descriptor Destination Data Address Register |
| CH8_LINK | Channel Descriptor Link Structure Address Register |
| CH9_REQSEL | Channel Peripheral Request Select Register |
| CH9_CFG | Channel Configuration Register |
| CH9_LOOP | Channel Loop Counter Register |
| CH9_CTRL | Channel Descriptor Control Word Register |
| CH9_SRC | Channel Descriptor Source Data Address Register |
| CH9_DST | Channel Descriptor Destination Data Address Register |
| CH9_LINK | Channel Descriptor Link Structure Address Register |
| CH10_REQSEL | Channel Peripheral Request Select Register |
| CH10_CFG | Channel Configuration Register |
| CH10_LOOP | Channel Loop Counter Register |
| CH10_CTRL | Channel Descriptor Control Word Register |
| CH10_SRC | Channel Descriptor Source Data Address Register |
| CH10_DST | Channel Descriptor Destination Data Address Register |
| CH10_LINK | Channel Descriptor Link Structure Address Register |
| CH11_REQSEL | Channel Peripheral Request Select Register |
| CH11_CFG | Channel Configuration Register |
| CH11_LOOP | Channel Loop Counter Register |
| CH11_CTRL | Channel Descriptor Control Word Register |
| CH11_SRC | Channel Descriptor Source Data Address Register |
| CH11_DST | Channel Descriptor Destination Data Address Register |
| CH11_LINK | Channel Descriptor Link Structure Address Register |
| CH12_REQSEL | Channel Peripheral Request Select Register |
| CH12_CFG | Channel Configuration Register |
| CH12_LOOP | Channel Loop Counter Register |
| CH12_CTRL | Channel Descriptor Control Word Register |
| CH12_SRC | Channel Descriptor Source Data Address Register |
| CH12_DST | Channel Descriptor Destination Data Address Register |
| CH12_LINK | Channel Descriptor Link Structure Address Register |
| CH13_REQSEL | Channel Peripheral Request Select Register |
| CH13_CFG | Channel Configuration Register |
| CH13_LOOP | Channel Loop Counter Register |
| CH13_CTRL | Channel Descriptor Control Word Register |
| CH13_SRC | Channel Descriptor Source Data Address Register |
| CH13_DST | Channel Descriptor Destination Data Address Register |
| CH13_LINK | Channel Descriptor Link Structure Address Register |
| CH14_REQSEL | Channel Peripheral Request Select Register |
| CH14_CFG | Channel Configuration Register |
| CH14_LOOP | Channel Loop Counter Register |
| CH14_CTRL | Channel Descriptor Control Word Register |
| CH14_SRC | Channel Descriptor Source Data Address Register |
| CH14_DST | Channel Descriptor Destination Data Address Register |
| CH14_LINK | Channel Descriptor Link Structure Address Register |
| CH15_REQSEL | Channel Peripheral Request Select Register |
| CH15_CFG | Channel Configuration Register |
| CH15_LOOP | Channel Loop Counter Register |
| CH15_CTRL | Channel Descriptor Control Word Register |
| CH15_SRC | Channel Descriptor Source Data Address Register |
| CH15_DST | Channel Descriptor Destination Data Address Register |
| CH15_LINK | Channel Descriptor Link Structure Address Register |
| CH16_REQSEL | Channel Peripheral Request Select Register |
| CH16_CFG | Channel Configuration Register |
| CH16_LOOP | Channel Loop Counter Register |
| CH16_CTRL | Channel Descriptor Control Word Register |
| CH16_SRC | Channel Descriptor Source Data Address Register |
| CH16_DST | Channel Descriptor Destination Data Address Register |
| CH16_LINK | Channel Descriptor Link Structure Address Register |
| CH17_REQSEL | Channel Peripheral Request Select Register |
| CH17_CFG | Channel Configuration Register |
| CH17_LOOP | Channel Loop Counter Register |
| CH17_CTRL | Channel Descriptor Control Word Register |
| CH17_SRC | Channel Descriptor Source Data Address Register |
| CH17_DST | Channel Descriptor Destination Data Address Register |
| CH17_LINK | Channel Descriptor Link Structure Address Register |
| CH18_REQSEL | Channel Peripheral Request Select Register |
| CH18_CFG | Channel Configuration Register |
| CH18_LOOP | Channel Loop Counter Register |
| CH18_CTRL | Channel Descriptor Control Word Register |
| CH18_SRC | Channel Descriptor Source Data Address Register |
| CH18_DST | Channel Descriptor Destination Data Address Register |
| CH18_LINK | Channel Descriptor Link Structure Address Register |
| CH19_REQSEL | Channel Peripheral Request Select Register |
| CH19_CFG | Channel Configuration Register |
| CH19_LOOP | Channel Loop Counter Register |
| CH19_CTRL | Channel Descriptor Control Word Register |
| CH19_SRC | Channel Descriptor Source Data Address Register |
| CH19_DST | Channel Descriptor Destination Data Address Register |
| CH19_LINK | Channel Descriptor Link Structure Address Register |
| CH20_REQSEL | Channel Peripheral Request Select Register |
| CH20_CFG | Channel Configuration Register |
| CH20_LOOP | Channel Loop Counter Register |
| CH20_CTRL | Channel Descriptor Control Word Register |
| CH20_SRC | Channel Descriptor Source Data Address Register |
| CH20_DST | Channel Descriptor Destination Data Address Register |
| CH20_LINK | Channel Descriptor Link Structure Address Register |
| CH21_REQSEL | Channel Peripheral Request Select Register |
| CH21_CFG | Channel Configuration Register |
| CH21_LOOP | Channel Loop Counter Register |
| CH21_CTRL | Channel Descriptor Control Word Register |
| CH21_SRC | Channel Descriptor Source Data Address Register |
| CH21_DST | Channel Descriptor Destination Data Address Register |
| CH21_LINK | Channel Descriptor Link Structure Address Register |
| CH22_REQSEL | Channel Peripheral Request Select Register |
| CH22_CFG | Channel Configuration Register |
| CH22_LOOP | Channel Loop Counter Register |
| CH22_CTRL | Channel Descriptor Control Word Register |
| CH22_SRC | Channel Descriptor Source Data Address Register |
| CH22_DST | Channel Descriptor Destination Data Address Register |
| CH22_LINK | Channel Descriptor Link Structure Address Register |
| CH23_REQSEL | Channel Peripheral Request Select Register |
| CH23_CFG | Channel Configuration Register |
| CH23_LOOP | Channel Loop Counter Register |
| CH23_CTRL | Channel Descriptor Control Word Register |
| CH23_SRC | Channel Descriptor Source Data Address Register |
| CH23_DST | Channel Descriptor Destination Data Address Register |
| CH23_LINK | Channel Descriptor Link Structure Address Register |
| CHBUSY | DMA Channel Busy Register |
| CHDONE | DMA Channel Linking Done Register (Single-Cycle RMW) |
| CHEN | DMA Channel Enable Register (Single-Cycle RMW) |
| CTRL | DMA Control Register |
| DBGHALT | DMA Channel Debug Halt Register |
| IEN | Interrupt Enable Register |
| IF | Interrupt Flag Register |
| IFC | Interrupt Flag Clear Register |
| IFS | Interrupt Flag Set Register |
| LINKLOAD | DMA Channel Link Load Register |
| REQCLEAR | DMA Channel Request Clear Register |
| REQDIS | DMA Channel Request Disable Register |
| REQPEND | DMA Channel Requests Pending Register |
| RegisterBlock | Register block |
| STATUS | DMA Status Register |
| SWREQ | DMA Channel Software Transfer Request Register |
| SYNC | DMA Synchronization Trigger Register (Single-Cycle RMW) |