1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305
#[doc = "Reader of register HC0_CHAR"] pub type R = crate::R<u32, super::HC0_CHAR>; #[doc = "Writer for register HC0_CHAR"] pub type W = crate::W<u32, super::HC0_CHAR>; #[doc = "Register HC0_CHAR `reset()`'s with value 0"] impl crate::ResetValue for super::HC0_CHAR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `MPS`"] pub type MPS_R = crate::R<u16, u16>; #[doc = "Write proxy for field `MPS`"] pub struct MPS_W<'a> { w: &'a mut W, } impl<'a> MPS_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u16) -> &'a mut W { self.w.bits = (self.w.bits & !0x07ff) | ((value as u32) & 0x07ff); self.w } } #[doc = "Reader of field `EPNUM`"] pub type EPNUM_R = crate::R<u8, u8>; #[doc = "Write proxy for field `EPNUM`"] pub struct EPNUM_W<'a> { w: &'a mut W, } impl<'a> EPNUM_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x0f << 11)) | (((value as u32) & 0x0f) << 11); self.w } } #[doc = "Reader of field `EPDIR`"] pub type EPDIR_R = crate::R<bool, bool>; #[doc = "Write proxy for field `EPDIR`"] pub struct EPDIR_W<'a> { w: &'a mut W, } impl<'a> EPDIR_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); self.w } } #[doc = "Reader of field `LSPDDEV`"] pub type LSPDDEV_R = crate::R<bool, bool>; #[doc = "Write proxy for field `LSPDDEV`"] pub struct LSPDDEV_W<'a> { w: &'a mut W, } impl<'a> LSPDDEV_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); self.w } } #[doc = "Endpoint Type\n\nValue on reset: 0"] #[derive(Clone, Copy, Debug, PartialEq)] #[repr(u8)] pub enum EPTYPE_A { #[doc = "0: Control endpoint."] CONTROL = 0, #[doc = "1: Isochronous endpoint."] ISO = 1, #[doc = "2: Bulk endpoint."] BULK = 2, #[doc = "3: Interrupt endpoint."] INT = 3, } impl From<EPTYPE_A> for u8 { #[inline(always)] fn from(variant: EPTYPE_A) -> Self { variant as _ } } #[doc = "Reader of field `EPTYPE`"] pub type EPTYPE_R = crate::R<u8, EPTYPE_A>; impl EPTYPE_R { #[doc = r"Get enumerated values variant"] #[inline(always)] pub fn variant(&self) -> EPTYPE_A { match self.bits { 0 => EPTYPE_A::CONTROL, 1 => EPTYPE_A::ISO, 2 => EPTYPE_A::BULK, 3 => EPTYPE_A::INT, _ => unreachable!(), } } #[doc = "Checks if the value of the field is `CONTROL`"] #[inline(always)] pub fn is_control(&self) -> bool { *self == EPTYPE_A::CONTROL } #[doc = "Checks if the value of the field is `ISO`"] #[inline(always)] pub fn is_iso(&self) -> bool { *self == EPTYPE_A::ISO } #[doc = "Checks if the value of the field is `BULK`"] #[inline(always)] pub fn is_bulk(&self) -> bool { *self == EPTYPE_A::BULK } #[doc = "Checks if the value of the field is `INT`"] #[inline(always)] pub fn is_int(&self) -> bool { *self == EPTYPE_A::INT } } #[doc = "Write proxy for field `EPTYPE`"] pub struct EPTYPE_W<'a> { w: &'a mut W, } impl<'a> EPTYPE_W<'a> { #[doc = r"Writes `variant` to the field"] #[inline(always)] pub fn variant(self, variant: EPTYPE_A) -> &'a mut W { { self.bits(variant.into()) } } #[doc = "Control endpoint."] #[inline(always)] pub fn control(self) -> &'a mut W { self.variant(EPTYPE_A::CONTROL) } #[doc = "Isochronous endpoint."] #[inline(always)] pub fn iso(self) -> &'a mut W { self.variant(EPTYPE_A::ISO) } #[doc = "Bulk endpoint."] #[inline(always)] pub fn bulk(self) -> &'a mut W { self.variant(EPTYPE_A::BULK) } #[doc = "Interrupt endpoint."] #[inline(always)] pub fn int(self) -> &'a mut W { self.variant(EPTYPE_A::INT) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18); self.w } } #[doc = "Reader of field `MC`"] pub type MC_R = crate::R<u8, u8>; #[doc = "Write proxy for field `MC`"] pub struct MC_W<'a> { w: &'a mut W, } impl<'a> MC_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20); self.w } } #[doc = "Reader of field `DEVADDR`"] pub type DEVADDR_R = crate::R<u8, u8>; #[doc = "Write proxy for field `DEVADDR`"] pub struct DEVADDR_W<'a> { w: &'a mut W, } impl<'a> DEVADDR_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x7f << 22)) | (((value as u32) & 0x7f) << 22); self.w } } #[doc = "Reader of field `ODDFRM`"] pub type ODDFRM_R = crate::R<bool, bool>; #[doc = "Write proxy for field `ODDFRM`"] pub struct ODDFRM_W<'a> { w: &'a mut W, } impl<'a> ODDFRM_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 29)) | (((value as u32) & 0x01) << 29); self.w } } #[doc = "Reader of field `CHDIS`"] pub type CHDIS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CHDIS`"] pub struct CHDIS_W<'a> { w: &'a mut W, } impl<'a> CHDIS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 30)) | (((value as u32) & 0x01) << 30); self.w } } #[doc = "Reader of field `CHENA`"] pub type CHENA_R = crate::R<bool, bool>; #[doc = "Write proxy for field `CHENA`"] pub struct CHENA_W<'a> { w: &'a mut W, } impl<'a> CHENA_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 31)) | (((value as u32) & 0x01) << 31); self.w } } impl R { #[doc = "Bits 0:10 - Maximum Packet Size"] #[inline(always)] pub fn mps(&self) -> MPS_R { MPS_R::new((self.bits & 0x07ff) as u16) } #[doc = "Bits 11:14 - Endpoint Number"] #[inline(always)] pub fn epnum(&self) -> EPNUM_R { EPNUM_R::new(((self.bits >> 11) & 0x0f) as u8) } #[doc = "Bit 15 - Endpoint Direction"] #[inline(always)] pub fn epdir(&self) -> EPDIR_R { EPDIR_R::new(((self.bits >> 15) & 0x01) != 0) } #[doc = "Bit 17 - Low-Speed Device"] #[inline(always)] pub fn lspddev(&self) -> LSPDDEV_R { LSPDDEV_R::new(((self.bits >> 17) & 0x01) != 0) } #[doc = "Bits 18:19 - Endpoint Type"] #[inline(always)] pub fn eptype(&self) -> EPTYPE_R { EPTYPE_R::new(((self.bits >> 18) & 0x03) as u8) } #[doc = "Bits 20:21 - Multi Count (MC) / Error Count"] #[inline(always)] pub fn mc(&self) -> MC_R { MC_R::new(((self.bits >> 20) & 0x03) as u8) } #[doc = "Bits 22:28 - Device Address"] #[inline(always)] pub fn devaddr(&self) -> DEVADDR_R { DEVADDR_R::new(((self.bits >> 22) & 0x7f) as u8) } #[doc = "Bit 29 - Odd Frame"] #[inline(always)] pub fn oddfrm(&self) -> ODDFRM_R { ODDFRM_R::new(((self.bits >> 29) & 0x01) != 0) } #[doc = "Bit 30 - Channel Disable"] #[inline(always)] pub fn chdis(&self) -> CHDIS_R { CHDIS_R::new(((self.bits >> 30) & 0x01) != 0) } #[doc = "Bit 31 - Channel Enable"] #[inline(always)] pub fn chena(&self) -> CHENA_R { CHENA_R::new(((self.bits >> 31) & 0x01) != 0) } } impl W { #[doc = "Bits 0:10 - Maximum Packet Size"] #[inline(always)] pub fn mps(&mut self) -> MPS_W { MPS_W { w: self } } #[doc = "Bits 11:14 - Endpoint Number"] #[inline(always)] pub fn epnum(&mut self) -> EPNUM_W { EPNUM_W { w: self } } #[doc = "Bit 15 - Endpoint Direction"] #[inline(always)] pub fn epdir(&mut self) -> EPDIR_W { EPDIR_W { w: self } } #[doc = "Bit 17 - Low-Speed Device"] #[inline(always)] pub fn lspddev(&mut self) -> LSPDDEV_W { LSPDDEV_W { w: self } } #[doc = "Bits 18:19 - Endpoint Type"] #[inline(always)] pub fn eptype(&mut self) -> EPTYPE_W { EPTYPE_W { w: self } } #[doc = "Bits 20:21 - Multi Count (MC) / Error Count"] #[inline(always)] pub fn mc(&mut self) -> MC_W { MC_W { w: self } } #[doc = "Bits 22:28 - Device Address"] #[inline(always)] pub fn devaddr(&mut self) -> DEVADDR_W { DEVADDR_W { w: self } } #[doc = "Bit 29 - Odd Frame"] #[inline(always)] pub fn oddfrm(&mut self) -> ODDFRM_W { ODDFRM_W { w: self } } #[doc = "Bit 30 - Channel Disable"] #[inline(always)] pub fn chdis(&mut self) -> CHDIS_W { CHDIS_W { w: self } } #[doc = "Bit 31 - Channel Enable"] #[inline(always)] pub fn chena(&mut self) -> CHENA_W { CHENA_W { w: self } } }