Module efm32gg11b::sdio[][src]

Expand description

SDIO

Modules

AUTO CMD12 Error Status and Host Control2 Register

ADMA Error Status Register

ADMA System Address Register

Block Size and Block Count Register

Boot Timeout Control Register

Buffer Data Register

Capabilities Register to Hold Bits 31~0

Capabilities Register to Hold Bits 63~32

Core Configuration 0

Core Configuration 1

Core Configuration Preset Value 0

Core Configuration Preset Value 1

Core Configuration Preset Value 2

Core Configuration Preset Value 3

Clock Control, Timeout Control and Software Register

SD Command Argument Register

Core Control Signals

Force Event Register for Auto CMD Error Status

Host Control1, Power, Block Gap and Wakeup-up Control Register

Normal and Error Interrupt Signal Enable Register

Normal and Error Interrupt Status Register

Normal and Error Interrupt Status Enable Register

Maximum Current Capabilities Register

Present State Register

Preset Value for Initialization and Default Speed Mode

Preset Value for High Speed and SDR12 Modes

Preset Value for SDR25 and SDR50 Modes

Preset Value for SDR104 and DDR50 Modes

Response0 and Response1 Register

Response2 and Response3 Register

Response4 and Response5 Register

Response6 and Response7 Register

I/O LOCATION Register

I/O LOCATION Register

I/O LOCATION Enable Register

SDMA System Address Register

Slot Interrupt Status Register

Transfer Mode and Command Register

Structs

Register block

Type Definitions

AUTO CMD12 Error Status and Host Control2 Register

ADMA Error Status Register

ADMA System Address Register

Block Size and Block Count Register

Boot Timeout Control Register

Buffer Data Register

Capabilities Register to Hold Bits 31~0

Capabilities Register to Hold Bits 63~32

Core Configuration 0

Core Configuration 1

Core Configuration Preset Value 0

Core Configuration Preset Value 1

Core Configuration Preset Value 2

Core Configuration Preset Value 3

Clock Control, Timeout Control and Software Register

SD Command Argument Register

Core Control Signals

Force Event Register for Auto CMD Error Status

Host Control1, Power, Block Gap and Wakeup-up Control Register

Normal and Error Interrupt Signal Enable Register

Normal and Error Interrupt Status Register

Normal and Error Interrupt Status Enable Register

Maximum Current Capabilities Register

Present State Register

Preset Value for Initialization and Default Speed Mode

Preset Value for High Speed and SDR12 Modes

Preset Value for SDR25 and SDR50 Modes

Preset Value for SDR104 and DDR50 Modes

Response0 and Response1 Register

Response2 and Response3 Register

Response4 and Response5 Register

Response6 and Response7 Register

I/O LOCATION Register

I/O LOCATION Register

I/O LOCATION Enable Register

SDMA System Address Register

Slot Interrupt Status Register

Transfer Mode and Command Register