[][src]Module dw1000::ll

Low-level interface to the DW1000

This module implements a register-level interface to the DW1000. Users of this library should typically not need to use this. Please consider using the high-level interface instead.

If you're using the low-level interface because the high-level interface doesn't cover your use case, please consider filing an issue.

NOTE: Many field access methods accept types that have a larger number of bits than the field actually consists of. If you use such a method to pass a value that is too large to be written to the field, it will be silently truncated.

Modules

agc_tune1

AGC Tuning register 1

agc_tune2

AGC Tuning register 2

dev_id

Device identifier

drx_tune2

Digital Tuning Register 2

dx_time

Delayed Send or Receive Time

ec_ctrl

External Clock Sync Counter Config

eui

Extended Unique Identifier

evc_ctrl

Event Counter Control

evc_hpw

Half Period Warning Counter

evc_tpw

TX Power-Up Warning Counter

fs_plltune

Frequency synth - PLL Tuning

lde_cfg1

LDE Configuration Register 1

lde_cfg2

LDE Configuration Register 2

lde_rxantd

RX Antenna Delay

ldotune

LDO voltage tuning parameter

otp_addr

OTP Address

otp_ctrl

OTP Control

otp_rdat

OTP Read Data

panadr

PAN Identifier and Short Address

pmsc_ctrl0

PMSC Control Register 0

pmsc_ctrl1

PMSC Control Register 1

rf_txctrl

Analog TX Control Register

rx_buffer

Receive Data Buffer

rx_finfo

RX Frame Information

rx_time

Receive Time Stamp

sys_cfg

System Configuration

sys_ctrl

System Control Register

sys_mask

System Event Mask Register

sys_state

System State information

sys_status

System Event Status Register

sys_time

System Time Counter

tc_pgdelay

Pulse Generator Delay

tx_antd

TX Antenna Delay

tx_buffer

Transmit Data Buffer

tx_fctrl

TX Frame Control

tx_power

TX Power Control

tx_time

Transmit Time Stamp

Structs

AGC_TUNE1

AGC Tuning register 1

AGC_TUNE2

AGC Tuning register 2

DEV_ID

Device identifier

DRX_TUNE2

Digital Tuning Register 2

DW1000

Entry point to the DW1000 driver's low-level API

DX_TIME

Delayed Send or Receive Time

EC_CTRL

External Clock Sync Counter Config

EUI

Extended Unique Identifier

EVC_CTRL

Event Counter Control

EVC_HPW

Half Period Warning Counter

EVC_TPW

TX Power-Up Warning Counter

FS_PLLTUNE

Frequency synth - PLL Tuning

LDE_CFG1

LDE Configuration Register 1

LDE_CFG2

LDE Configuration Register 2

LDE_RXANTD

RX Antenna Delay

LDOTUNE

LDO voltage tuning parameter

OTP_ADDR

OTP Address

OTP_CTRL

OTP Control

OTP_RDAT

OTP Read Data

PANADR

PAN Identifier and Short Address

PMSC_CTRL0

PMSC Control Register 0

PMSC_CTRL1

PMSC Control Register 1

RF_TXCTRL

Analog TX Control Register

RX_BUFFER

Receive Data Buffer

RX_FINFO

RX Frame Information

RX_TIME

Receive Time Stamp

RegAccessor

Provides access to a register

SYS_CFG

System Configuration

SYS_CTRL

System Control Register

SYS_MASK

System Event Mask Register

SYS_STATE

System State information

SYS_STATUS

System Event Status Register

SYS_TIME

System Time Counter

TC_PGDELAY

Pulse Generator Delay

TX_ANTD

TX Antenna Delay

TX_BUFFER

Transmit Data Buffer

TX_FCTRL

TX Frame Control

TX_POWER

TX Power Control

TX_TIME

Transmit Time Stamp

Enums

Error

An SPI error that can occur when communicating with the DW1000

Traits

Readable

Marker trait for registers that can be read from

Register

Implemented for all registers

Writable

Marker trait for registers that can be written to