List of all items

Structs

• registers::audio_serial_port::asp_ctrl::Asp1Enables1
• registers::audio_serial_port::asp_ctrl::Asp2Enables1
• registers::audio_serial_port::asp_ctrl::AspControl1
• registers::audio_serial_port::asp_ctrl::AspControl2
• registers::audio_serial_port::asp_ctrl::AspControl3
• registers::audio_serial_port::asp_ctrl::AspDataControl1
• registers::audio_serial_port::asp_ctrl::AspDataControl5
• registers::clocking_sample_rates::clock::AsyncClock1
• registers::clocking_sample_rates::clock::AsyncClock2
• registers::clocking_sample_rates::clock::SystemClock1
• registers::clocking_sample_rates::fll::Fll1Control1
• registers::clocking_sample_rates::fll::Fll1Control2
• registers::clocking_sample_rates::fll::Fll1Control3
• registers::clocking_sample_rates::fll::FllGpioClock
• registers::clocking_sample_rates::sample_rate::SampleRate
• registers::digital_core::compression::DrcControl1
• registers::digital_core::compression::DrcControl2
• registers::digital_core::compression::DrcControl3
• registers::digital_core::compression::DrcControl4
• registers::digital_core::equalizer::EqBandCoeff1
• registers::digital_core::equalizer::EqBandCoeff2
• registers::digital_core::equalizer::EqBandPg
• registers::digital_core::equalizer::EqControl1
• registers::digital_core::equalizer::EqControl2
• registers::digital_core::equalizer::EqGain1
• registers::digital_core::equalizer::EqGain2
• registers::digital_core::mixers::FxStatus
• registers::digital_core::mixers::InputSource
• registers::digital_core::sample_rate_control::AspControl1
• registers::digital_core::sample_rate_control::ComfortNoiseGenerator
• registers::digital_core::sample_rate_control::Dsp1SampleRate
• registers::digital_core::sample_rate_control::FxSampleRate
• registers::digital_core::sample_rate_control::InputSampleRateControl
• registers::digital_core::sample_rate_control::OutputControl1
• registers::digital_core::sample_rate_control::PwmDrive1
• registers::digital_core::sample_rate_control::ToneGenerator1
• registers::gpio::gpio_ctrl::GpioCtrl1
• registers::input_signal_path::input_signal_path_config::Input1Control1
• registers::input_signal_path::input_signal_path_control::InControl2
• registers::input_signal_path::input_signal_path_control::InputControl3
• registers::input_signal_path::input_signal_path_enable::InputControl
• registers::output_signal_path::volume_ctrl::Out1LVolume1
• registers::output_signal_path::volume_ctrl::OutputEnable1
• registers::reset::SoftReset
• registers::voltage_regulators::voltage::Ldo2Crtl1
• registers::voltage_regulators::voltage::MicBiasCtrl1
• registers::voltage_regulators::voltage::MicBiasCtrl5

Enums

• registers::audio_serial_port::asp_ctrl::AspBclkMasterSelect
• registers::audio_serial_port::asp_ctrl::AspBclkOutputControl
• registers::audio_serial_port::asp_ctrl::AspBclkRate
• registers::audio_serial_port::asp_ctrl::AspDoutTristateControl
• registers::audio_serial_port::asp_ctrl::AspFormat
• registers::audio_serial_port::asp_ctrl::AspRate
• registers::audio_serial_port::asp_ctrl::Num
• registers::clocking_sample_rates::clock::Fraction
• registers::clocking_sample_rates::clock::Freqency
• registers::clocking_sample_rates::clock::Source
• registers::clocking_sample_rates::fll::DetectorGainSigned
• registers::clocking_sample_rates::fll::DetectorGainUnsigned
• registers::clocking_sample_rates::fll::FractionalMode
• registers::clocking_sample_rates::fll::GpioClockSource
• registers::clocking_sample_rates::fll::Num
• registers::clocking_sample_rates::fll::ReferenceClockDivider
• registers::clocking_sample_rates::fll::ReferenceClockSource
• registers::clocking_sample_rates::sample_rate::Num
• registers::clocking_sample_rates::sample_rate::Select
• registers::digital_core::compression::CompressorSlopeLowerRegion
• registers::digital_core::compression::CompressorSlopeUpperRegion
• registers::digital_core::compression::DrcControl1Reg
• registers::digital_core::compression::DrcControl2Reg
• registers::digital_core::compression::DrcControl3Reg
• registers::digital_core::compression::DrcControl4Reg
• registers::digital_core::compression::GainAttackRate
• registers::digital_core::compression::GainDecayRate
• registers::digital_core::compression::MaxGain
• registers::digital_core::compression::MinGain
• registers::digital_core::compression::NoiseGateMinGain
• registers::digital_core::compression::NoiseGateSlope
• registers::digital_core::compression::QuickReleaseDecayRate
• registers::digital_core::compression::QuickReleaseThreshold
• registers::digital_core::compression::SignalDetectMode
• registers::digital_core::compression::SignalDetectPeakThreshold
• registers::digital_core::equalizer::Band1Mode
• registers::digital_core::equalizer::EqBandCoeff1Reg
• registers::digital_core::equalizer::EqBandCoeff2Reg
• registers::digital_core::equalizer::EqBandGain
• registers::digital_core::equalizer::EqBandPgReg
• registers::digital_core::equalizer::EqGain1Reg
• registers::digital_core::equalizer::EqGain2Reg
• registers::digital_core::mixers::ImportSourceReg
• registers::digital_core::mixers::InputSourceSelect
• registers::digital_core::sample_rate_control::AspControl1Reg
• registers::digital_core::sample_rate_control::Dsp1SampleRateReg
• registers::digital_core::sample_rate_control::InputSampleRateControlReg
• registers::digital_core::sample_rate_control::SampleRate
• registers::digital_core::sample_rate_control::SampleRateInclAsync
• registers::gpio::gpio_ctrl::DebounceTime
• registers::gpio::gpio_ctrl::Direction
• registers::gpio::gpio_ctrl::DriveStrength
• registers::gpio::gpio_ctrl::ExtendedPinFunction
• registers::gpio::gpio_ctrl::Num
• registers::gpio::gpio_ctrl::OutputConfig
• registers::gpio::gpio_ctrl::OutputPolarity
• registers::gpio::gpio_ctrl::PinFunction
• registers::input_signal_path::input_signal_path_config::InputPath1Mode
• registers::input_signal_path::input_signal_path_config::OversampleRateControl
• registers::input_signal_path::input_signal_path_control::Reg
• registers::voltage_regulators::voltage::Ldo2OutputVoltageSelect
• registers::voltage_regulators::voltage::MicBias1Source
• registers::voltage_regulators::voltage::MicBias1VoltageLevel

Traits

• hw_interface::Bus

Functions

• driver::event_handler
• driver::reset
• registers::clocking_sample_rates::clock::system_clock_2
• registers::clocking_sample_rates::fll::fll1_control4

Constants

• spec::CS47L63_ADC1LLP_TRIM
• spec::CS47L63_ADC1L_ANA_CONTROL1
• spec::CS47L63_ADC1L_LP_CONTROL1
• spec::CS47L63_ADC1L_TRIM_RD
• spec::CS47L63_ADC1RLP_TRIM
• spec::CS47L63_ADC1R_ANA_CONTROL1
• spec::CS47L63_ADC1R_LP_CONTROL1
• spec::CS47L63_ADC1R_TRIM_RD
• spec::CS47L63_ADC2LLP_TRIM
• spec::CS47L63_ADC2L_ANA_CONTROL1
• spec::CS47L63_ADC2L_LP_CONTROL1
• spec::CS47L63_ADC2L_TRIM_RD
• spec::CS47L63_ADC2RLP_TRIM
• spec::CS47L63_ADC2R_ANA_CONTROL1
• spec::CS47L63_ADC2R_LP_CONTROL1
• spec::CS47L63_ADC2R_TRIM_RD
• spec::CS47L63_ADC_ANA_CONTROL1
• spec::CS47L63_ADC_ANA_CONTROL2
• spec::CS47L63_ADC_ANA_CONTROL4
• spec::CS47L63_ADC_ANA_CONTROL5
• spec::CS47L63_ADC_CAP_TRIM
• spec::CS47L63_ADC_DAC_CONTROL
• spec::CS47L63_ADC_DITH_CONTROL
• spec::CS47L63_ADC_INTEG_CTRL
• spec::CS47L63_ADC_INTEG_STATUS
• spec::CS47L63_ADC_PGA_CONTROL1
• spec::CS47L63_ADC_PGA_CONTROL2
• spec::CS47L63_ADC_PGA_TEST
• spec::CS47L63_ADC_QUICK_CHARGE1
• spec::CS47L63_ADC_QUICK_CHARGE2
• spec::CS47L63_ADC_TEST1
• spec::CS47L63_ADC_TEST2
• spec::CS47L63_ADC_TEST3
• spec::CS47L63_ADC_TEST4
• spec::CS47L63_ADC_TEST5
• spec::CS47L63_ADC_TEST6
• spec::CS47L63_ADC_TEST7
• spec::CS47L63_ADC_TST1
• spec::CS47L63_ADC_VCO_CAL1
• spec::CS47L63_ADC_VCO_CAL10
• spec::CS47L63_ADC_VCO_CAL11
• spec::CS47L63_ADC_VCO_CAL12
• spec::CS47L63_ADC_VCO_CAL13
• spec::CS47L63_ADC_VCO_CAL14
• spec::CS47L63_ADC_VCO_CAL2
• spec::CS47L63_ADC_VCO_CAL3
• spec::CS47L63_ADC_VCO_CAL4
• spec::CS47L63_ADC_VCO_COUNT1
• spec::CS47L63_ADC_VCO_COUNT2
• spec::CS47L63_ADC_VCO_COUNT3
• spec::CS47L63_ADC_VCO_COUNT4
• spec::CS47L63_ADC_VCO_TRIM1
• spec::CS47L63_ADC_VCO_TRIM2
• spec::CS47L63_ADC_VCO_TRIM3
• spec::CS47L63_ADC_VCO_TRIM4
• spec::CS47L63_ANC_CTRL_1
• spec::CS47L63_ANC_CTRL_10
• spec::CS47L63_ANC_CTRL_11
• spec::CS47L63_ANC_CTRL_12
• spec::CS47L63_ANC_CTRL_13
• spec::CS47L63_ANC_CTRL_2
• spec::CS47L63_ANC_CTRL_3
• spec::CS47L63_ANC_CTRL_4
• spec::CS47L63_ANC_CTRL_5
• spec::CS47L63_ANC_CTRL_6
• spec::CS47L63_ANC_CTRL_7
• spec::CS47L63_ANC_CTRL_8
• spec::CS47L63_ANC_CTRL_9
• spec::CS47L63_ANC_L_CTRL_1
• spec::CS47L63_ANC_L_CTRL_10
• spec::CS47L63_ANC_L_CTRL_11
• spec::CS47L63_ANC_L_CTRL_12
• spec::CS47L63_ANC_L_CTRL_13
• spec::CS47L63_ANC_L_CTRL_14
• spec::CS47L63_ANC_L_CTRL_15
• spec::CS47L63_ANC_L_CTRL_16
• spec::CS47L63_ANC_L_CTRL_17
• spec::CS47L63_ANC_L_CTRL_18
• spec::CS47L63_ANC_L_CTRL_19
• spec::CS47L63_ANC_L_CTRL_2
• spec::CS47L63_ANC_L_CTRL_20
• spec::CS47L63_ANC_L_CTRL_21
• spec::CS47L63_ANC_L_CTRL_22
• spec::CS47L63_ANC_L_CTRL_23
• spec::CS47L63_ANC_L_CTRL_24
• spec::CS47L63_ANC_L_CTRL_25
• spec::CS47L63_ANC_L_CTRL_26
• spec::CS47L63_ANC_L_CTRL_27
• spec::CS47L63_ANC_L_CTRL_28
• spec::CS47L63_ANC_L_CTRL_29
• spec::CS47L63_ANC_L_CTRL_3
• spec::CS47L63_ANC_L_CTRL_30
• spec::CS47L63_ANC_L_CTRL_31
• spec::CS47L63_ANC_L_CTRL_32
• spec::CS47L63_ANC_L_CTRL_33
• spec::CS47L63_ANC_L_CTRL_34
• spec::CS47L63_ANC_L_CTRL_35
• spec::CS47L63_ANC_L_CTRL_36
• spec::CS47L63_ANC_L_CTRL_37
• spec::CS47L63_ANC_L_CTRL_38
• spec::CS47L63_ANC_L_CTRL_39
• spec::CS47L63_ANC_L_CTRL_4
• spec::CS47L63_ANC_L_CTRL_40
• spec::CS47L63_ANC_L_CTRL_41
• spec::CS47L63_ANC_L_CTRL_42
• spec::CS47L63_ANC_L_CTRL_43
• spec::CS47L63_ANC_L_CTRL_44
• spec::CS47L63_ANC_L_CTRL_45
• spec::CS47L63_ANC_L_CTRL_46
• spec::CS47L63_ANC_L_CTRL_47
• spec::CS47L63_ANC_L_CTRL_48
• spec::CS47L63_ANC_L_CTRL_49
• spec::CS47L63_ANC_L_CTRL_5
• spec::CS47L63_ANC_L_CTRL_50
• spec::CS47L63_ANC_L_CTRL_51
• spec::CS47L63_ANC_L_CTRL_52
• spec::CS47L63_ANC_L_CTRL_53
• spec::CS47L63_ANC_L_CTRL_54
• spec::CS47L63_ANC_L_CTRL_55
• spec::CS47L63_ANC_L_CTRL_56
• spec::CS47L63_ANC_L_CTRL_57
• spec::CS47L63_ANC_L_CTRL_58
• spec::CS47L63_ANC_L_CTRL_59
• spec::CS47L63_ANC_L_CTRL_6
• spec::CS47L63_ANC_L_CTRL_60
• spec::CS47L63_ANC_L_CTRL_61
• spec::CS47L63_ANC_L_CTRL_62
• spec::CS47L63_ANC_L_CTRL_63
• spec::CS47L63_ANC_L_CTRL_64
• spec::CS47L63_ANC_L_CTRL_65
• spec::CS47L63_ANC_L_CTRL_66
• spec::CS47L63_ANC_L_CTRL_7
• spec::CS47L63_ANC_L_CTRL_8
• spec::CS47L63_ANC_L_CTRL_9
• spec::CS47L63_ANC_L_CTRL_DEBUG
• spec::CS47L63_ANC_L_FF_IIR1_A1
• spec::CS47L63_ANC_L_FF_IIR1_A2
• spec::CS47L63_ANC_L_FF_IIR1_B0
• spec::CS47L63_ANC_L_FF_IIR1_B1
• spec::CS47L63_ANC_L_FF_IIR1_B2
• spec::CS47L63_ANC_L_FF_IIR2_A1
• spec::CS47L63_ANC_L_FF_IIR2_A2
• spec::CS47L63_ANC_L_FF_IIR2_B0
• spec::CS47L63_ANC_L_FF_IIR2_B1
• spec::CS47L63_ANC_L_FF_IIR2_B2
• spec::CS47L63_ANC_L_FF_IIR_COEFF_UPDATE
• spec::CS47L63_ANC_L_FF_IIR_CONTROL
• spec::CS47L63_ANC_L_FILT_DEBUG
• spec::CS47L63_ANC_SRC
• spec::CS47L63_AOD_PAD_CTRL
• spec::CS47L63_APB_MSTR_DSP_BRIDGE_ERR
• spec::CS47L63_ASP1TX1_INPUT1
• spec::CS47L63_ASP1TX1_INPUT2
• spec::CS47L63_ASP1TX1_INPUT3
• spec::CS47L63_ASP1TX1_INPUT4
• spec::CS47L63_ASP1TX2_INPUT1
• spec::CS47L63_ASP1TX2_INPUT2
• spec::CS47L63_ASP1TX2_INPUT3
• spec::CS47L63_ASP1TX2_INPUT4
• spec::CS47L63_ASP1TX3_INPUT1
• spec::CS47L63_ASP1TX3_INPUT2
• spec::CS47L63_ASP1TX3_INPUT3
• spec::CS47L63_ASP1TX3_INPUT4
• spec::CS47L63_ASP1TX4_INPUT1
• spec::CS47L63_ASP1TX4_INPUT2
• spec::CS47L63_ASP1TX4_INPUT3
• spec::CS47L63_ASP1TX4_INPUT4
• spec::CS47L63_ASP1TX5_INPUT1
• spec::CS47L63_ASP1TX5_INPUT2
• spec::CS47L63_ASP1TX5_INPUT3
• spec::CS47L63_ASP1TX5_INPUT4
• spec::CS47L63_ASP1TX6_INPUT1
• spec::CS47L63_ASP1TX6_INPUT2
• spec::CS47L63_ASP1TX6_INPUT3
• spec::CS47L63_ASP1TX6_INPUT4
• spec::CS47L63_ASP1TX7_INPUT1
• spec::CS47L63_ASP1TX7_INPUT2
• spec::CS47L63_ASP1TX7_INPUT3
• spec::CS47L63_ASP1TX7_INPUT4
• spec::CS47L63_ASP1TX8_INPUT1
• spec::CS47L63_ASP1TX8_INPUT2
• spec::CS47L63_ASP1TX8_INPUT3
• spec::CS47L63_ASP1TX8_INPUT4
• spec::CS47L63_ASP1_CLOCK_OVD1
• spec::CS47L63_ASP1_CONTROL1
• spec::CS47L63_ASP1_CONTROL2
• spec::CS47L63_ASP1_CONTROL3
• spec::CS47L63_ASP1_DATA_CONTROL1
• spec::CS47L63_ASP1_DATA_CONTROL5
• spec::CS47L63_ASP1_ENABLES1
• spec::CS47L63_ASP1_FRAME_CONTROL1
• spec::CS47L63_ASP1_FRAME_CONTROL2
• spec::CS47L63_ASP1_FRAME_CONTROL5
• spec::CS47L63_ASP1_FRAME_CONTROL6
• spec::CS47L63_ASP1_FSYNC_CONTROL1
• spec::CS47L63_ASP1_FSYNC_CONTROL2
• spec::CS47L63_ASP1_FSYNC_STATUS1
• spec::CS47L63_ASP1_LATENCY1
• spec::CS47L63_ASP1_TEST1
• spec::CS47L63_ASP2TX1_INPUT1
• spec::CS47L63_ASP2TX1_INPUT2
• spec::CS47L63_ASP2TX1_INPUT3
• spec::CS47L63_ASP2TX1_INPUT4
• spec::CS47L63_ASP2TX2_INPUT1
• spec::CS47L63_ASP2TX2_INPUT2
• spec::CS47L63_ASP2TX2_INPUT3
• spec::CS47L63_ASP2TX2_INPUT4
• spec::CS47L63_ASP2TX3_INPUT1
• spec::CS47L63_ASP2TX3_INPUT2
• spec::CS47L63_ASP2TX3_INPUT3
• spec::CS47L63_ASP2TX3_INPUT4
• spec::CS47L63_ASP2TX4_INPUT1
• spec::CS47L63_ASP2TX4_INPUT2
• spec::CS47L63_ASP2TX4_INPUT3
• spec::CS47L63_ASP2TX4_INPUT4
• spec::CS47L63_ASP2_CLOCK_OVD1
• spec::CS47L63_ASP2_CONTROL1
• spec::CS47L63_ASP2_CONTROL2
• spec::CS47L63_ASP2_CONTROL3
• spec::CS47L63_ASP2_DATA_CONTROL1
• spec::CS47L63_ASP2_DATA_CONTROL5
• spec::CS47L63_ASP2_ENABLES1
• spec::CS47L63_ASP2_FRAME_CONTROL1
• spec::CS47L63_ASP2_FRAME_CONTROL5
• spec::CS47L63_ASP2_FSYNC_CONTROL1
• spec::CS47L63_ASP2_FSYNC_CONTROL2
• spec::CS47L63_ASP2_FSYNC_STATUS1
• spec::CS47L63_ASP2_LATENCY1
• spec::CS47L63_ASP2_TEST1
• spec::CS47L63_ASRC1_CONTROL1
• spec::CS47L63_ASRC1_DEBUG1
• spec::CS47L63_ASRC1_DEBUG2
• spec::CS47L63_ASRC1_DEBUG3
• spec::CS47L63_ASRC1_DEBUG4
• spec::CS47L63_ASRC1_ENABLE
• spec::CS47L63_ASRC1_IN1L_INPUT1
• spec::CS47L63_ASRC1_IN1R_INPUT1
• spec::CS47L63_ASRC1_IN2L_INPUT1
• spec::CS47L63_ASRC1_IN2R_INPUT1
• spec::CS47L63_ASRC1_STATUS
• spec::CS47L63_ASYNC_CLOCK1
• spec::CS47L63_ASYNC_CLOCK2
• spec::CS47L63_ASYNC_CLOCK3
• spec::CS47L63_ASYNC_CLOCK4
• spec::CS47L63_ASYNC_CLOCK5
• spec::CS47L63_ASYNC_CLOCK6
• spec::CS47L63_ASYNC_SAMPLE_RATE1
• spec::CS47L63_ASYNC_SAMPLE_RATE2
• spec::CS47L63_ASYNC_SAMPLE_RATE_STATUS1
• spec::CS47L63_ASYNC_SAMPLE_RATE_STATUS2
• spec::CS47L63_BANDGAP_CONTROL1
• spec::CS47L63_BANDGAP_CONTROL2
• spec::CS47L63_BISR_CTRL
• spec::CS47L63_BISR_RD_ADDR_OFFSET
• spec::CS47L63_BISR_WR_ADDR_OFFSET
• spec::CS47L63_BOOT_DONE_EINT1_MASK
• spec::CS47L63_BOOT_DONE_MASK1_MASK
• spec::CS47L63_CHIP_SPEC_SPARE
• spec::CS47L63_CIF1_BRIDGE_ERR
• spec::CS47L63_CIF2_BRIDGE_ERR
• spec::CS47L63_CIF_MON1
• spec::CS47L63_CIF_MON2
• spec::CS47L63_CIF_MON_PADDR
• spec::CS47L63_CIF_PAD_CTRL1
• spec::CS47L63_CIF_PAD_DBG1
• spec::CS47L63_CLKGEN_PAD_CTRL
• spec::CS47L63_CLOCK32K
• spec::CS47L63_COMFORT_NOISE_GENERATOR
• spec::CS47L63_CTRLIF_ERR_MASK1_MASK
• spec::CS47L63_CTRL_ASYNC0
• spec::CS47L63_CTRL_ASYNC1
• spec::CS47L63_CTRL_ASYNC2
• spec::CS47L63_CTRL_ASYNC3
• spec::CS47L63_CTRL_IF_CONFIG1
• spec::CS47L63_CTRL_IF_CONFIG2
• spec::CS47L63_CTRL_IF_DEBUG1
• spec::CS47L63_CTRL_IF_DEBUG2
• spec::CS47L63_CTRL_IF_DEBUG3
• spec::CS47L63_CTRL_IF_I2C
• spec::CS47L63_CTRL_IF_I2C_2_CONTROL
• spec::CS47L63_CTRL_IF_SPARE1
• spec::CS47L63_CTRL_IF_STATUS1
• spec::CS47L63_CTRL_IF_STATUS2
• spec::CS47L63_DAC_BYP_TEST_1
• spec::CS47L63_DAC_COMP_1
• spec::CS47L63_DAC_COMP_2
• spec::CS47L63_DAC_FILTP_CTRL
• spec::CS47L63_DAC_IF_CONTROL_1
• spec::CS47L63_DAC_IF_CONTROL_2
• spec::CS47L63_DAC_IF_CONTROL_3
• spec::CS47L63_DAC_IF_TEST_1
• spec::CS47L63_DAC_IF_TRIM_1
• spec::CS47L63_DAC_SR_DETECT
• spec::CS47L63_DAC_TEST_1
• spec::CS47L63_DAC_TEST_CONTROL_1
• spec::CS47L63_DAC_TEST_CONTROL_2
• spec::CS47L63_DEVID
• spec::CS47L63_DEV_ID
• spec::CS47L63_DEV_ID_OVD
• spec::CS47L63_DIE_STS1
• spec::CS47L63_DIE_STS2
• spec::CS47L63_DMIC_TEST
• spec::CS47L63_DRC1L_INPUT1
• spec::CS47L63_DRC1L_INPUT2
• spec::CS47L63_DRC1L_INPUT3
• spec::CS47L63_DRC1L_INPUT4
• spec::CS47L63_DRC1R_INPUT1
• spec::CS47L63_DRC1R_INPUT2
• spec::CS47L63_DRC1R_INPUT3
• spec::CS47L63_DRC1R_INPUT4
• spec::CS47L63_DRC1_CONTROL1
• spec::CS47L63_DRC1_CONTROL2
• spec::CS47L63_DRC1_CONTROL3
• spec::CS47L63_DRC1_CONTROL4
• spec::CS47L63_DRC1_CONTROL5
• spec::CS47L63_DRC2L_INPUT1
• spec::CS47L63_DRC2L_INPUT2
• spec::CS47L63_DRC2L_INPUT3
• spec::CS47L63_DRC2L_INPUT4
• spec::CS47L63_DRC2R_INPUT1
• spec::CS47L63_DRC2R_INPUT2
• spec::CS47L63_DRC2R_INPUT3
• spec::CS47L63_DRC2R_INPUT4
• spec::CS47L63_DRC2_CONTROL1
• spec::CS47L63_DRC2_CONTROL2
• spec::CS47L63_DRC2_CONTROL3
• spec::CS47L63_DRC2_CONTROL4
• spec::CS47L63_DRC2_CONTROL5
• spec::CS47L63_DSP1RX1_INPUT1
• spec::CS47L63_DSP1RX1_INPUT2
• spec::CS47L63_DSP1RX1_INPUT3
• spec::CS47L63_DSP1RX1_INPUT4
• spec::CS47L63_DSP1RX2_INPUT1
• spec::CS47L63_DSP1RX2_INPUT2
• spec::CS47L63_DSP1RX2_INPUT3
• spec::CS47L63_DSP1RX2_INPUT4
• spec::CS47L63_DSP1RX3_INPUT1
• spec::CS47L63_DSP1RX3_INPUT2
• spec::CS47L63_DSP1RX3_INPUT3
• spec::CS47L63_DSP1RX3_INPUT4
• spec::CS47L63_DSP1RX4_INPUT1
• spec::CS47L63_DSP1RX4_INPUT2
• spec::CS47L63_DSP1RX4_INPUT3
• spec::CS47L63_DSP1RX4_INPUT4
• spec::CS47L63_DSP1RX5_INPUT1
• spec::CS47L63_DSP1RX5_INPUT2
• spec::CS47L63_DSP1RX5_INPUT3
• spec::CS47L63_DSP1RX5_INPUT4
• spec::CS47L63_DSP1RX6_INPUT1
• spec::CS47L63_DSP1RX6_INPUT2
• spec::CS47L63_DSP1RX6_INPUT3
• spec::CS47L63_DSP1RX6_INPUT4
• spec::CS47L63_DSP1RX7_INPUT1
• spec::CS47L63_DSP1RX7_INPUT2
• spec::CS47L63_DSP1RX7_INPUT3
• spec::CS47L63_DSP1RX7_INPUT4
• spec::CS47L63_DSP1RX8_INPUT1
• spec::CS47L63_DSP1RX8_INPUT2
• spec::CS47L63_DSP1RX8_INPUT3
• spec::CS47L63_DSP1RX8_INPUT4
• spec::CS47L63_DSP1_AHBM_WINDOW0_CONTROL_0
• spec::CS47L63_DSP1_AHBM_WINDOW0_CONTROL_1
• spec::CS47L63_DSP1_AHBM_WINDOW1_CONTROL_0
• spec::CS47L63_DSP1_AHBM_WINDOW1_CONTROL_1
• spec::CS47L63_DSP1_AHBM_WINDOW2_CONTROL_0
• spec::CS47L63_DSP1_AHBM_WINDOW2_CONTROL_1
• spec::CS47L63_DSP1_AHBM_WINDOW3_CONTROL_0
• spec::CS47L63_DSP1_AHBM_WINDOW3_CONTROL_1
• spec::CS47L63_DSP1_AHBM_WINDOW4_CONTROL_0
• spec::CS47L63_DSP1_AHBM_WINDOW4_CONTROL_1
• spec::CS47L63_DSP1_AHBM_WINDOW5_CONTROL_0
• spec::CS47L63_DSP1_AHBM_WINDOW5_CONTROL_1
• spec::CS47L63_DSP1_AHBM_WINDOW6_CONTROL_0
• spec::CS47L63_DSP1_AHBM_WINDOW6_CONTROL_1
• spec::CS47L63_DSP1_AHBM_WINDOW7_CONTROL_0
• spec::CS47L63_DSP1_AHBM_WINDOW7_CONTROL_1
• spec::CS47L63_DSP1_AHBM_WINDOW_DEBUG_0
• spec::CS47L63_DSP1_AHBM_WINDOW_DEBUG_1
• spec::CS47L63_DSP1_AHB_PACK_ERR_MASK1_MASK
• spec::CS47L63_DSP1_AHB_SYS_ERR_MASK1_MASK
• spec::CS47L63_DSP1_CCM_CLK_OVERRIDE
• spec::CS47L63_DSP1_CCM_CORE_CONTROL
• spec::CS47L63_DSP1_CLOCK_FREQ
• spec::CS47L63_DSP1_CLOCK_STATUS
• spec::CS47L63_DSP1_CORE_SOFT_RESET
• spec::CS47L63_DSP1_CTRL_SETUP
• spec::CS47L63_DSP1_DEBUG
• spec::CS47L63_DSP1_IRQ0_MASK1_MASK
• spec::CS47L63_DSP1_IRQ10_CONTROL
• spec::CS47L63_DSP1_IRQ11_CONTROL
• spec::CS47L63_DSP1_IRQ12_CONTROL
• spec::CS47L63_DSP1_IRQ13_CONTROL
• spec::CS47L63_DSP1_IRQ14_CONTROL
• spec::CS47L63_DSP1_IRQ15_CONTROL
• spec::CS47L63_DSP1_IRQ16_CONTROL
• spec::CS47L63_DSP1_IRQ17_CONTROL
• spec::CS47L63_DSP1_IRQ18_CONTROL
• spec::CS47L63_DSP1_IRQ19_CONTROL
• spec::CS47L63_DSP1_IRQ1_CONTROL
• spec::CS47L63_DSP1_IRQ20_CONTROL
• spec::CS47L63_DSP1_IRQ21_CONTROL
• spec::CS47L63_DSP1_IRQ22_CONTROL
• spec::CS47L63_DSP1_IRQ23_CONTROL
• spec::CS47L63_DSP1_IRQ2_CONTROL
• spec::CS47L63_DSP1_IRQ3_CONTROL
• spec::CS47L63_DSP1_IRQ4_CONTROL
• spec::CS47L63_DSP1_IRQ5_CONTROL
• spec::CS47L63_DSP1_IRQ6_CONTROL
• spec::CS47L63_DSP1_IRQ7_CONTROL
• spec::CS47L63_DSP1_IRQ8_CONTROL
• spec::CS47L63_DSP1_IRQ9_CONTROL
• spec::CS47L63_DSP1_MPU_ERR_MASK1_MASK
• spec::CS47L63_DSP1_MPU_LOCK_CONFIG
• spec::CS47L63_DSP1_MPU_PM_VIO_ADDR
• spec::CS47L63_DSP1_MPU_PM_VIO_STATUS
• spec::CS47L63_DSP1_MPU_WDT_RESET_CONTROL
• spec::CS47L63_DSP1_MPU_WINDOW_ACCESS_0
• spec::CS47L63_DSP1_MPU_WINDOW_ACCESS_1
• spec::CS47L63_DSP1_MPU_WINDOW_ACCESS_2
• spec::CS47L63_DSP1_MPU_WINDOW_ACCESS_3
• spec::CS47L63_DSP1_MPU_XMEM_ACCESS_0
• spec::CS47L63_DSP1_MPU_XMEM_ACCESS_1
• spec::CS47L63_DSP1_MPU_XMEM_ACCESS_2
• spec::CS47L63_DSP1_MPU_XMEM_ACCESS_3
• spec::CS47L63_DSP1_MPU_XM_VIO_ADDR
• spec::CS47L63_DSP1_MPU_XM_VIO_STATUS
• spec::CS47L63_DSP1_MPU_XREG_ACCESS_0
• spec::CS47L63_DSP1_MPU_XREG_ACCESS_1
• spec::CS47L63_DSP1_MPU_XREG_ACCESS_2
• spec::CS47L63_DSP1_MPU_XREG_ACCESS_3
• spec::CS47L63_DSP1_MPU_YMEM_ACCESS_0
• spec::CS47L63_DSP1_MPU_YMEM_ACCESS_1
• spec::CS47L63_DSP1_MPU_YMEM_ACCESS_2
• spec::CS47L63_DSP1_MPU_YMEM_ACCESS_3
• spec::CS47L63_DSP1_MPU_YM_VIO_ADDR
• spec::CS47L63_DSP1_MPU_YM_VIO_STATUS
• spec::CS47L63_DSP1_MPU_YREG_ACCESS_0
• spec::CS47L63_DSP1_MPU_YREG_ACCESS_1
• spec::CS47L63_DSP1_MPU_YREG_ACCESS_2
• spec::CS47L63_DSP1_MPU_YREG_ACCESS_3
• spec::CS47L63_DSP1_NMI_CONTROL1
• spec::CS47L63_DSP1_NMI_CONTROL2
• spec::CS47L63_DSP1_NMI_CONTROL3
• spec::CS47L63_DSP1_NMI_CONTROL4
• spec::CS47L63_DSP1_NMI_CONTROL5
• spec::CS47L63_DSP1_NMI_CONTROL6
• spec::CS47L63_DSP1_NMI_CONTROL7
• spec::CS47L63_DSP1_NMI_CONTROL8
• spec::CS47L63_DSP1_PMEM_0
• spec::CS47L63_DSP1_PMEM_1
• spec::CS47L63_DSP1_PMEM_2
• spec::CS47L63_DSP1_PMEM_3
• spec::CS47L63_DSP1_PMEM_4
• spec::CS47L63_DSP1_PMEM_51190
• spec::CS47L63_DSP1_PMEM_51191
• spec::CS47L63_DSP1_PMEM_51192
• spec::CS47L63_DSP1_PMEM_51193
• spec::CS47L63_DSP1_PMEM_51194
• spec::CS47L63_DSP1_PM_SRAM_IBUS_SETUP_0
• spec::CS47L63_DSP1_PM_SRAM_IBUS_SETUP_1
• spec::CS47L63_DSP1_PM_SRAM_IBUS_SETUP_2
• spec::CS47L63_DSP1_PM_SRAM_IBUS_SETUP_3
• spec::CS47L63_DSP1_PM_SRAM_IBUS_SETUP_4
• spec::CS47L63_DSP1_PM_SRAM_IBUS_SETUP_5
• spec::CS47L63_DSP1_RESUME_CONTROL
• spec::CS47L63_DSP1_SAMPLE_RATE_RX1
• spec::CS47L63_DSP1_SAMPLE_RATE_RX2
• spec::CS47L63_DSP1_SAMPLE_RATE_RX3
• spec::CS47L63_DSP1_SAMPLE_RATE_RX4
• spec::CS47L63_DSP1_SAMPLE_RATE_RX5
• spec::CS47L63_DSP1_SAMPLE_RATE_RX6
• spec::CS47L63_DSP1_SAMPLE_RATE_RX7
• spec::CS47L63_DSP1_SAMPLE_RATE_RX8
• spec::CS47L63_DSP1_SAMPLE_RATE_TX1
• spec::CS47L63_DSP1_SAMPLE_RATE_TX2
• spec::CS47L63_DSP1_SAMPLE_RATE_TX3
• spec::CS47L63_DSP1_SAMPLE_RATE_TX4
• spec::CS47L63_DSP1_SAMPLE_RATE_TX5
• spec::CS47L63_DSP1_SAMPLE_RATE_TX6
• spec::CS47L63_DSP1_SAMPLE_RATE_TX7
• spec::CS47L63_DSP1_SAMPLE_RATE_TX8
• spec::CS47L63_DSP1_SCRATCH1
• spec::CS47L63_DSP1_SCRATCH2
• spec::CS47L63_DSP1_SCRATCH3
• spec::CS47L63_DSP1_SCRATCH4
• spec::CS47L63_DSP1_STREAM_ARB_CONTROL
• spec::CS47L63_DSP1_STREAM_ARB_RESYNC_MSK1
• spec::CS47L63_DSP1_SYS_INFO_AHB_ADDR
• spec::CS47L63_DSP1_SYS_INFO_CORE_ID
• spec::CS47L63_DSP1_SYS_INFO_FEATURES
• spec::CS47L63_DSP1_SYS_INFO_FIR_FILTERS
• spec::CS47L63_DSP1_SYS_INFO_ID
• spec::CS47L63_DSP1_SYS_INFO_LMS_FILTERS
• spec::CS47L63_DSP1_SYS_INFO_PM_BANK_SIZE
• spec::CS47L63_DSP1_SYS_INFO_PM_BOOT_SIZE
• spec::CS47L63_DSP1_SYS_INFO_PM_SRAM_SIZE
• spec::CS47L63_DSP1_SYS_INFO_VERSION
• spec::CS47L63_DSP1_SYS_INFO_XM_BANK_SIZE
• spec::CS47L63_DSP1_SYS_INFO_XM_SRAM_SIZE
• spec::CS47L63_DSP1_SYS_INFO_YM_BANK_SIZE
• spec::CS47L63_DSP1_SYS_INFO_YM_SRAM_SIZE
• spec::CS47L63_DSP1_TIMER_CONTROL
• spec::CS47L63_DSP1_TIMESTAMP_COUNT
• spec::CS47L63_DSP1_WDT_CONTROL
• spec::CS47L63_DSP1_WDT_EXPIRE_STS1_MASK
• spec::CS47L63_DSP1_WDT_STATUS
• spec::CS47L63_DSP1_XMEM_PACKED_0
• spec::CS47L63_DSP1_XMEM_PACKED_1
• spec::CS47L63_DSP1_XMEM_PACKED_2
• spec::CS47L63_DSP1_XMEM_PACKED_67578
• spec::CS47L63_DSP1_XMEM_PACKED_67579
• spec::CS47L63_DSP1_XMEM_PACKED_67580
• spec::CS47L63_DSP1_XMEM_UNPACKED24_0
• spec::CS47L63_DSP1_XMEM_UNPACKED24_1
• spec::CS47L63_DSP1_XMEM_UNPACKED24_2
• spec::CS47L63_DSP1_XMEM_UNPACKED24_3
• spec::CS47L63_DSP1_XMEM_UNPACKED24_90106
• spec::CS47L63_DSP1_XMEM_UNPACKED24_90107
• spec::CS47L63_DSP1_XMEM_UNPACKED24_90108
• spec::CS47L63_DSP1_XMEM_UNPACKED24_90109
• spec::CS47L63_DSP1_XMEM_UNPACKED32_0
• spec::CS47L63_DSP1_XMEM_UNPACKED32_1
• spec::CS47L63_DSP1_XMEM_UNPACKED32_45053
• spec::CS47L63_DSP1_XMEM_UNPACKED32_45054
• spec::CS47L63_DSP1_XM_SRAM_IBUS_SETUP_0
• spec::CS47L63_DSP1_XM_SRAM_IBUS_SETUP_1
• spec::CS47L63_DSP1_XM_SRAM_IBUS_SETUP_10
• spec::CS47L63_DSP1_XM_SRAM_IBUS_SETUP_11
• spec::CS47L63_DSP1_XM_SRAM_IBUS_SETUP_2
• spec::CS47L63_DSP1_XM_SRAM_IBUS_SETUP_3
• spec::CS47L63_DSP1_XM_SRAM_IBUS_SETUP_4
• spec::CS47L63_DSP1_XM_SRAM_IBUS_SETUP_5
• spec::CS47L63_DSP1_XM_SRAM_IBUS_SETUP_6
• spec::CS47L63_DSP1_XM_SRAM_IBUS_SETUP_7
• spec::CS47L63_DSP1_XM_SRAM_IBUS_SETUP_8
• spec::CS47L63_DSP1_XM_SRAM_IBUS_SETUP_9
• spec::CS47L63_DSP1_YMEM_PACKED_0
• spec::CS47L63_DSP1_YMEM_PACKED_1
• spec::CS47L63_DSP1_YMEM_PACKED_2
• spec::CS47L63_DSP1_YMEM_PACKED_36858
• spec::CS47L63_DSP1_YMEM_PACKED_36859
• spec::CS47L63_DSP1_YMEM_PACKED_36860
• spec::CS47L63_DSP1_YMEM_UNPACKED24_0
• spec::CS47L63_DSP1_YMEM_UNPACKED24_1
• spec::CS47L63_DSP1_YMEM_UNPACKED24_2
• spec::CS47L63_DSP1_YMEM_UNPACKED24_3
• spec::CS47L63_DSP1_YMEM_UNPACKED24_49146
• spec::CS47L63_DSP1_YMEM_UNPACKED24_49147
• spec::CS47L63_DSP1_YMEM_UNPACKED24_49148
• spec::CS47L63_DSP1_YMEM_UNPACKED24_49149
• spec::CS47L63_DSP1_YMEM_UNPACKED32_0
• spec::CS47L63_DSP1_YMEM_UNPACKED32_1
• spec::CS47L63_DSP1_YMEM_UNPACKED32_24573
• spec::CS47L63_DSP1_YMEM_UNPACKED32_24574
• spec::CS47L63_DSP1_YM_SRAM_IBUS_SETUP_0
• spec::CS47L63_DSP1_YM_SRAM_IBUS_SETUP_1
• spec::CS47L63_DSP1_YM_SRAM_IBUS_SETUP_2
• spec::CS47L63_DSP1_YM_SRAM_IBUS_SETUP_3
• spec::CS47L63_DSP1_YM_SRAM_IBUS_SETUP_4
• spec::CS47L63_DSP1_YM_SRAM_IBUS_SETUP_5
• spec::CS47L63_DSP1_YM_SRAM_IBUS_SETUP_6
• spec::CS47L63_DSP_CLOCK1
• spec::CS47L63_DSP_CLOCK2
• spec::CS47L63_DSP_CLOCK3
• spec::CS47L63_DSP_CLOCK4
• spec::CS47L63_DSP_CLOCK5
• spec::CS47L63_DSP_CLOCK6
• spec::CS47L63_DSP_STREAM_ARB_RESYNC_CTRL
• spec::CS47L63_DVS_STS
• spec::CS47L63_EDRE1_THRESH_1
• spec::CS47L63_EDRE_DEBOUNCE_1
• spec::CS47L63_EDRE_ENABLE
• spec::CS47L63_EDRE_MANUAL
• spec::CS47L63_EDRE_TEST_1
• spec::CS47L63_EDRE_TEST_3
• spec::CS47L63_EQ1_BAND1_COEFF1
• spec::CS47L63_EQ1_BAND1_COEFF2
• spec::CS47L63_EQ1_BAND1_PG
• spec::CS47L63_EQ1_BAND2_COEFF1
• spec::CS47L63_EQ1_BAND2_COEFF2
• spec::CS47L63_EQ1_BAND2_PG
• spec::CS47L63_EQ1_BAND3_COEFF1
• spec::CS47L63_EQ1_BAND3_COEFF2
• spec::CS47L63_EQ1_BAND3_PG
• spec::CS47L63_EQ1_BAND4_COEFF1
• spec::CS47L63_EQ1_BAND4_COEFF2
• spec::CS47L63_EQ1_BAND4_PG
• spec::CS47L63_EQ1_BAND5_COEFF1
• spec::CS47L63_EQ1_BAND5_PG
• spec::CS47L63_EQ1_GAIN1
• spec::CS47L63_EQ1_GAIN2
• spec::CS47L63_EQ1_INPUT1
• spec::CS47L63_EQ1_INPUT2
• spec::CS47L63_EQ1_INPUT3
• spec::CS47L63_EQ1_INPUT4
• spec::CS47L63_EQ2_BAND1_COEFF1
• spec::CS47L63_EQ2_BAND1_COEFF2
• spec::CS47L63_EQ2_BAND1_PG
• spec::CS47L63_EQ2_BAND2_COEFF1
• spec::CS47L63_EQ2_BAND2_COEFF2
• spec::CS47L63_EQ2_BAND2_PG
• spec::CS47L63_EQ2_BAND3_COEFF1
• spec::CS47L63_EQ2_BAND3_COEFF2
• spec::CS47L63_EQ2_BAND3_PG
• spec::CS47L63_EQ2_BAND4_COEFF1
• spec::CS47L63_EQ2_BAND4_COEFF2
• spec::CS47L63_EQ2_BAND4_PG
• spec::CS47L63_EQ2_BAND5_COEFF1
• spec::CS47L63_EQ2_BAND5_PG
• spec::CS47L63_EQ2_GAIN1
• spec::CS47L63_EQ2_GAIN2
• spec::CS47L63_EQ2_INPUT1
• spec::CS47L63_EQ2_INPUT2
• spec::CS47L63_EQ2_INPUT3
• spec::CS47L63_EQ2_INPUT4
• spec::CS47L63_EQ3_BAND1_COEFF1
• spec::CS47L63_EQ3_BAND1_COEFF2
• spec::CS47L63_EQ3_BAND1_PG
• spec::CS47L63_EQ3_BAND2_COEFF1
• spec::CS47L63_EQ3_BAND2_COEFF2
• spec::CS47L63_EQ3_BAND2_PG
• spec::CS47L63_EQ3_BAND3_COEFF1
• spec::CS47L63_EQ3_BAND3_COEFF2
• spec::CS47L63_EQ3_BAND3_PG
• spec::CS47L63_EQ3_BAND4_COEFF1
• spec::CS47L63_EQ3_BAND4_COEFF2
• spec::CS47L63_EQ3_BAND4_PG
• spec::CS47L63_EQ3_BAND5_COEFF1
• spec::CS47L63_EQ3_BAND5_PG
• spec::CS47L63_EQ3_GAIN1
• spec::CS47L63_EQ3_GAIN2
• spec::CS47L63_EQ3_INPUT1
• spec::CS47L63_EQ3_INPUT2
• spec::CS47L63_EQ3_INPUT3
• spec::CS47L63_EQ3_INPUT4
• spec::CS47L63_EQ4_BAND1_COEFF1
• spec::CS47L63_EQ4_BAND1_COEFF2
• spec::CS47L63_EQ4_BAND1_PG
• spec::CS47L63_EQ4_BAND2_COEFF1
• spec::CS47L63_EQ4_BAND2_COEFF2
• spec::CS47L63_EQ4_BAND2_PG
• spec::CS47L63_EQ4_BAND3_COEFF1
• spec::CS47L63_EQ4_BAND3_COEFF2
• spec::CS47L63_EQ4_BAND3_PG
• spec::CS47L63_EQ4_BAND4_COEFF1
• spec::CS47L63_EQ4_BAND4_COEFF2
• spec::CS47L63_EQ4_BAND4_PG
• spec::CS47L63_EQ4_BAND5_COEFF1
• spec::CS47L63_EQ4_BAND5_PG
• spec::CS47L63_EQ4_GAIN1
• spec::CS47L63_EQ4_GAIN2
• spec::CS47L63_EQ4_INPUT1
• spec::CS47L63_EQ4_INPUT2
• spec::CS47L63_EQ4_INPUT3
• spec::CS47L63_EQ4_INPUT4
• spec::CS47L63_EQ_CONTROL1
• spec::CS47L63_EQ_CONTROL2
• spec::CS47L63_FABID
• spec::CS47L63_FAB_ID
• spec::CS47L63_FLL1_ANALOGUE_TEST1
• spec::CS47L63_FLL1_CONTROL1
• spec::CS47L63_FLL1_CONTROL2
• spec::CS47L63_FLL1_CONTROL3
• spec::CS47L63_FLL1_CONTROL4
• spec::CS47L63_FLL1_CONTROL5
• spec::CS47L63_FLL1_CONTROL6
• spec::CS47L63_FLL1_CONTROL7
• spec::CS47L63_FLL1_DIGITAL_TEST1
• spec::CS47L63_FLL1_DIGITAL_TEST2
• spec::CS47L63_FLL1_DIGITAL_TEST3
• spec::CS47L63_FLL1_DIGITAL_TEST4
• spec::CS47L63_FLL1_DIGITAL_TEST5
• spec::CS47L63_FLL1_GPIO_CLOCK
• spec::CS47L63_FLL2_ANALOGUE_TEST1
• spec::CS47L63_FLL2_CONTROL1
• spec::CS47L63_FLL2_CONTROL2
• spec::CS47L63_FLL2_CONTROL3
• spec::CS47L63_FLL2_CONTROL4
• spec::CS47L63_FLL2_CONTROL5
• spec::CS47L63_FLL2_CONTROL6
• spec::CS47L63_FLL2_CONTROL7
• spec::CS47L63_FLL2_DIGITAL_TEST1
• spec::CS47L63_FLL2_DIGITAL_TEST2
• spec::CS47L63_FLL2_DIGITAL_TEST3
• spec::CS47L63_FLL2_DIGITAL_TEST4
• spec::CS47L63_FLL2_DIGITAL_TEST5
• spec::CS47L63_FLL2_GPIO_CLOCK
• spec::CS47L63_FLL_DSP_CTRL
• spec::CS47L63_FRF_COEFF_1L_1
• spec::CS47L63_FRF_COEFF_1L_2
• spec::CS47L63_FX_SAMPLE_RATE
• spec::CS47L63_FX_STATUS
• spec::CS47L63_FX_TEST
• spec::CS47L63_GPIO10_CTRL1
• spec::CS47L63_GPIO11_CTRL1
• spec::CS47L63_GPIO12_CTRL1
• spec::CS47L63_GPIO1_CTRL1
• spec::CS47L63_GPIO2_CTRL1
• spec::CS47L63_GPIO3_CTRL1
• spec::CS47L63_GPIO4_CTRL1
• spec::CS47L63_GPIO5_CTRL1
• spec::CS47L63_GPIO6_CTRL1
• spec::CS47L63_GPIO7_CTRL1
• spec::CS47L63_GPIO8_CTRL1
• spec::CS47L63_GPIO9_CTRL1
• spec::CS47L63_GPIO_DEBUG_CTRL
• spec::CS47L63_GPIO_STATUS1
• spec::CS47L63_HP1L_CTRL
• spec::CS47L63_HP_OCD_CTRL1
• spec::CS47L63_HP_OCD_STAT1
• spec::CS47L63_HP_OCD_TEST1
• spec::CS47L63_HP_OCD_TEST2
• spec::CS47L63_IN1L_CONTROL1
• spec::CS47L63_IN1L_CONTROL2
• spec::CS47L63_IN1R_CONTROL1
• spec::CS47L63_IN1R_CONTROL2
• spec::CS47L63_IN1_CIC_TEST
• spec::CS47L63_IN2L_CONTROL1
• spec::CS47L63_IN2L_CONTROL2
• spec::CS47L63_IN2R_CONTROL1
• spec::CS47L63_IN2R_CONTROL2
• spec::CS47L63_IN2_CIC_TEST
• spec::CS47L63_INPUT1_CONTROL1
• spec::CS47L63_INPUT2_CONTROL1
• spec::CS47L63_INPUT_CONTROL
• spec::CS47L63_INPUT_CONTROL2
• spec::CS47L63_INPUT_CONTROL3
• spec::CS47L63_INPUT_DITH_CONTROL
• spec::CS47L63_INPUT_HPF_CONTROL
• spec::CS47L63_INPUT_MIDMODE_CONTROL
• spec::CS47L63_INPUT_RATE_CONTROL
• spec::CS47L63_INPUT_STATUS
• spec::CS47L63_INPUT_TEST1
• spec::CS47L63_INPUT_TEST2
• spec::CS47L63_INPUT_VOL_CONTROL
• spec::CS47L63_IN_SIG_DET_CONTROL
• spec::CS47L63_IRQ1_CFG
• spec::CS47L63_IRQ1_CTRL_AOD
• spec::CS47L63_IRQ1_EDGE_11
• spec::CS47L63_IRQ1_EDGE_17
• spec::CS47L63_IRQ1_EINT_1
• spec::CS47L63_IRQ1_EINT_10
• spec::CS47L63_IRQ1_EINT_11
• spec::CS47L63_IRQ1_EINT_12
• spec::CS47L63_IRQ1_EINT_13
• spec::CS47L63_IRQ1_EINT_14
• spec::CS47L63_IRQ1_EINT_15
• spec::CS47L63_IRQ1_EINT_17
• spec::CS47L63_IRQ1_EINT_18
• spec::CS47L63_IRQ1_EINT_2
• spec::CS47L63_IRQ1_EINT_3
• spec::CS47L63_IRQ1_EINT_5
• spec::CS47L63_IRQ1_EINT_6
• spec::CS47L63_IRQ1_EINT_7
• spec::CS47L63_IRQ1_EINT_9
• spec::CS47L63_IRQ1_EINT_AOD
• spec::CS47L63_IRQ1_MASK_1
• spec::CS47L63_IRQ1_MASK_10
• spec::CS47L63_IRQ1_MASK_11
• spec::CS47L63_IRQ1_MASK_12
• spec::CS47L63_IRQ1_MASK_13
• spec::CS47L63_IRQ1_MASK_14
• spec::CS47L63_IRQ1_MASK_15
• spec::CS47L63_IRQ1_MASK_17
• spec::CS47L63_IRQ1_MASK_18
• spec::CS47L63_IRQ1_MASK_2
• spec::CS47L63_IRQ1_MASK_3
• spec::CS47L63_IRQ1_MASK_5
• spec::CS47L63_IRQ1_MASK_6
• spec::CS47L63_IRQ1_MASK_7
• spec::CS47L63_IRQ1_MASK_9
• spec::CS47L63_IRQ1_MASK_AOD
• spec::CS47L63_IRQ1_STATUS
• spec::CS47L63_IRQ1_STS_1
• spec::CS47L63_IRQ1_STS_10
• spec::CS47L63_IRQ1_STS_11
• spec::CS47L63_IRQ1_STS_12
• spec::CS47L63_IRQ1_STS_13
• spec::CS47L63_IRQ1_STS_14
• spec::CS47L63_IRQ1_STS_15
• spec::CS47L63_IRQ1_STS_17
• spec::CS47L63_IRQ1_STS_2
• spec::CS47L63_IRQ1_STS_3
• spec::CS47L63_IRQ1_STS_5
• spec::CS47L63_IRQ1_STS_6
• spec::CS47L63_IRQ1_STS_7
• spec::CS47L63_IRQ1_STS_9
• spec::CS47L63_IRQ3_CFG
• spec::CS47L63_IRQ3_EINT_1
• spec::CS47L63_IRQ3_EINT_2
• spec::CS47L63_IRQ3_MASK_1
• spec::CS47L63_IRQ3_MASK_2
• spec::CS47L63_IRQ3_STATUS
• spec::CS47L63_IRQ3_STS_1
• spec::CS47L63_IRQ3_STS_2
• spec::CS47L63_ISRC1DEC1_INPUT1
• spec::CS47L63_ISRC1DEC2_INPUT1
• spec::CS47L63_ISRC1DEC3_INPUT1
• spec::CS47L63_ISRC1DEC4_INPUT1
• spec::CS47L63_ISRC1INT1_INPUT1
• spec::CS47L63_ISRC1INT2_INPUT1
• spec::CS47L63_ISRC1INT3_INPUT1
• spec::CS47L63_ISRC1INT4_INPUT1
• spec::CS47L63_ISRC1_CONTROL1
• spec::CS47L63_ISRC1_CONTROL2
• spec::CS47L63_ISRC1_DEBUG1
• spec::CS47L63_ISRC2DEC1_INPUT1
• spec::CS47L63_ISRC2DEC2_INPUT1
• spec::CS47L63_ISRC2INT1_INPUT1
• spec::CS47L63_ISRC2INT2_INPUT1
• spec::CS47L63_ISRC2_CONTROL1
• spec::CS47L63_ISRC2_CONTROL2
• spec::CS47L63_ISRC2_DEBUG1
• spec::CS47L63_ISRC3DEC1_INPUT1
• spec::CS47L63_ISRC3DEC2_INPUT1
• spec::CS47L63_ISRC3INT1_INPUT1
• spec::CS47L63_ISRC3INT2_INPUT1
• spec::CS47L63_ISRC3_CONTROL1
• spec::CS47L63_ISRC3_CONTROL2
• spec::CS47L63_ISRC3_DEBUG1
• spec::CS47L63_LDO2_CTRL1
• spec::CS47L63_LHPF1_COEFF
• spec::CS47L63_LHPF1_INPUT1
• spec::CS47L63_LHPF1_INPUT2
• spec::CS47L63_LHPF1_INPUT3
• spec::CS47L63_LHPF1_INPUT4
• spec::CS47L63_LHPF2_COEFF
• spec::CS47L63_LHPF2_INPUT1
• spec::CS47L63_LHPF2_INPUT2
• spec::CS47L63_LHPF2_INPUT3
• spec::CS47L63_LHPF2_INPUT4
• spec::CS47L63_LHPF3_COEFF
• spec::CS47L63_LHPF3_INPUT1
• spec::CS47L63_LHPF3_INPUT2
• spec::CS47L63_LHPF3_INPUT3
• spec::CS47L63_LHPF3_INPUT4
• spec::CS47L63_LHPF4_COEFF
• spec::CS47L63_LHPF4_INPUT1
• spec::CS47L63_LHPF4_INPUT2
• spec::CS47L63_LHPF4_INPUT3
• spec::CS47L63_LHPF4_INPUT4
• spec::CS47L63_LHPF_CONTROL1
• spec::CS47L63_LHPF_CONTROL2
• spec::CS47L63_LSRC2_CONTROL
• spec::CS47L63_LSRC2_CONTROL2
• spec::CS47L63_LSRC2_ENABLE
• spec::CS47L63_LSRC2_INL_INPUT1
• spec::CS47L63_LSRC2_INR_INPUT1
• spec::CS47L63_LSRC2_STATUS_REG0
• spec::CS47L63_LSRC2_TEST_REG0
• spec::CS47L63_LSRC2_TEST_REG12
• spec::CS47L63_LSRC2_TEST_REG1A
• spec::CS47L63_LSRC2_TEST_REG6
• spec::CS47L63_LSRC2_TEST_REGA
• spec::CS47L63_LSRC2_TEST_REGE
• spec::CS47L63_LSRC3_CONTROL
• spec::CS47L63_LSRC3_CONTROL2
• spec::CS47L63_LSRC3_ENABLE
• spec::CS47L63_LSRC3_INL_INPUT1
• spec::CS47L63_LSRC3_INR_INPUT1
• spec::CS47L63_LSRC3_STATUS_REG0
• spec::CS47L63_LSRC3_TEST_REG0
• spec::CS47L63_LSRC3_TEST_REG12
• spec::CS47L63_LSRC3_TEST_REG1A
• spec::CS47L63_LSRC3_TEST_REG6
• spec::CS47L63_LSRC3_TEST_REGA
• spec::CS47L63_LSRC3_TEST_REGE
• spec::CS47L63_MCU_CTRL0
• spec::CS47L63_MCU_CTRL1
• spec::CS47L63_MCU_CTRL2
• spec::CS47L63_MCU_CTRL3
• spec::CS47L63_MCU_CTRL4
• spec::CS47L63_MCU_CTRL5
• spec::CS47L63_MICBIAS_CTRL1
• spec::CS47L63_MICBIAS_CTRL5
• spec::CS47L63_MICBIAS_STATUS1
• spec::CS47L63_MICBIAS_TST_CTRL1
• spec::CS47L63_MICBIAS_TST_CTRL4
• spec::CS47L63_MICB_AOD_CTRL
• spec::CS47L63_MICD_CLAMP_CONTROL
• spec::CS47L63_MISC_TST_CTRL1
• spec::CS47L63_MIXER_BYPASS
• spec::CS47L63_MIXER_CLK_OVD
• spec::CS47L63_OTPID
• spec::CS47L63_OTP_CTRL0
• spec::CS47L63_OTP_CTRL1
• spec::CS47L63_OTP_CTRL3
• spec::CS47L63_OTP_CTRL4
• spec::CS47L63_OTP_CTRL5
• spec::CS47L63_OTP_CTRL6
• spec::CS47L63_OTP_CTRL7
• spec::CS47L63_OTP_CTRL8
• spec::CS47L63_OTP_PROM
• spec::CS47L63_OUT1L_CONTROL_1
• spec::CS47L63_OUT1L_ENABLE_1
• spec::CS47L63_OUT1L_INPUT1
• spec::CS47L63_OUT1L_INPUT2
• spec::CS47L63_OUT1L_INPUT3
• spec::CS47L63_OUT1L_INPUT4
• spec::CS47L63_OUT1L_VOLUME_1
• spec::CS47L63_OUT1L_VOLUME_2
• spec::CS47L63_OUT1_COMP_COEFF
• spec::CS47L63_OUTPUT_AEC_CONTROL_1
• spec::CS47L63_OUTPUT_AEC_ENABLE_1
• spec::CS47L63_OUTPUT_AEC_STATUS_1
• spec::CS47L63_OUTPUT_ANC_CTRL_1
• spec::CS47L63_OUTPUT_ANC_CTRL_2
• spec::CS47L63_OUTPUT_ASYNC_CLK
• spec::CS47L63_OUTPUT_CONTROL_1
• spec::CS47L63_OUTPUT_DSP_CLK
• spec::CS47L63_OUTPUT_ENABLE_1
• spec::CS47L63_OUTPUT_FILTER_CONTROL_1
• spec::CS47L63_OUTPUT_NG_CONTROL_1
• spec::CS47L63_OUTPUT_STATUS_1
• spec::CS47L63_OUTPUT_SYS_CLK
• spec::CS47L63_OUTPUT_VOLUME_RAMP
• spec::CS47L63_PAD_CTRL_SPARE
• spec::CS47L63_PDM_PAD_CTRL
• spec::CS47L63_PRODUCT_ID
• spec::CS47L63_PWM1_INPUT1
• spec::CS47L63_PWM1_INPUT2
• spec::CS47L63_PWM1_INPUT3
• spec::CS47L63_PWM1_INPUT4
• spec::CS47L63_PWM2_INPUT1
• spec::CS47L63_PWM2_INPUT2
• spec::CS47L63_PWM2_INPUT3
• spec::CS47L63_PWM2_INPUT4
• spec::CS47L63_PWM_DRIVE_1
• spec::CS47L63_PWM_DRIVE_2
• spec::CS47L63_PWM_DRIVE_3
• spec::CS47L63_RATE_ESTIMATOR1
• spec::CS47L63_RATE_ESTIMATOR2
• spec::CS47L63_RATE_ESTIMATOR3
• spec::CS47L63_RATE_ESTIMATOR4
• spec::CS47L63_RATE_ESTIMATOR5
• spec::CS47L63_RATE_ESTIMATOR6
• spec::CS47L63_RATE_ESTIMATOR7
• spec::CS47L63_RCO_CTRL1
• spec::CS47L63_RCO_CTRL2
• spec::CS47L63_RELID
• spec::CS47L63_REL_ID
• spec::CS47L63_REVID
• spec::CS47L63_REV_ID
• spec::CS47L63_SAMPLE_RATE1
• spec::CS47L63_SAMPLE_RATE2
• spec::CS47L63_SAMPLE_RATE3
• spec::CS47L63_SAMPLE_RATE4
• spec::CS47L63_SAMPLE_RATE_STATUS1
• spec::CS47L63_SAMPLE_RATE_STATUS2
• spec::CS47L63_SAMPLE_RATE_STATUS3
• spec::CS47L63_SAMPLE_RATE_STATUS4
• spec::CS47L63_SFT_RESET
• spec::CS47L63_SLIM_MANU_ID
• spec::CS47L63_SPI1_CFG_1
• spec::CS47L63_SUB_ANA_SPARE
• spec::CS47L63_SW_MANU_ID
• spec::CS47L63_SYSCLK_ERR_MASK1_MASK
• spec::CS47L63_SYSCLK_FAIL_MASK1_MASK
• spec::CS47L63_SYSTEM_CLOCK1
• spec::CS47L63_SYSTEM_CLOCK2
• spec::CS47L63_SYSTEM_CLOCK3
• spec::CS47L63_SYSTEM_CLOCK4
• spec::CS47L63_SYSTEM_CLOCK5
• spec::CS47L63_SYSTEM_CLOCK6
• spec::CS47L63_SYSTEM_CLOCK7
• spec::CS47L63_TEST_KEY_CTRL
• spec::CS47L63_TONE_GENERATOR1
• spec::CS47L63_TONE_GENERATOR2
• spec::CS47L63_TONE_GENERATOR3
• spec::CS47L63_USER_KEY_CTRL