Function xuantie::asm::dcache_cisw

pub unsafe fn dcache_cisw(way_and_set: usize)

DCACHE.CISW, D-cache clean dirty and invalid for way and set instruction

Writes L1 D-cache dirty item corresponding to given way and set to next level storage, and invalidate this table item. This instruction only operates on the current hart.

Permissions

Can run on M mode, or S mode if applicable.

Exceptions

Raises illegal instruction exception when mxstatus.theadisaee = 0, or when mxstatus.theadisaee = 1 but run on U mode.

Platform support

This instruction is supported on Xuantie C910, C906, E907 and E906 cores.

The C910 core has a 2-way set-associative D-cache. Input variable rs1[31] represents number of way, while rs1[w:6] represents number of set. When D-cache is configured 32 Kibibytes, w equals 13; when configured 64 Kibibytes, w equals 14.

The C906 core has a 4-way set-associative D-cache. Input variable rs1[31:30] represents number of way, while rs1[w:6] represents number of set. When D-cache is configured 32 Kibibytes, w equals 13; when configured 64 Kibibytes, w equals 14.

The E907 core has a 2-way set-associative D-cache. Input variable rs1[31] represents number of way, while rs1[w:6] represents number of set. When D-cache is configured 32 Kibibytes, w equals 13; when configured 16 Kibibytes, w equals 12, and so on.

The E906 core has a 2-way set-associative D-cache. Input variable rs1[31] represents number of way, while rs1[w:6] represents number of set. When D-cache is configured 32 Kibibytes, w equals 13; when configured 16 Kibibytes, w equals 12, and so on.