1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016
1017
1018
1019
1020
1021
1022
1023
1024
1025
1026
1027
1028
1029
1030
1031
1032
1033
1034
1035
1036
1037
1038
1039
1040
1041
1042
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052
1053
1054
1055
1056
1057
1058
1059
1060
1061
1062
1063
1064
1065
1066
1067
1068
1069
1070
1071
1072
1073
1074
1075
1076
1077
1078
1079
1080
1081
1082
1083
1084
1085
1086
1087
1088
1089
1090
1091
1092
1093
1094
1095
1096
1097
1098
1099
1100
1101
1102
1103
1104
1105
1106
1107
1108
1109
1110
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124
1125
1126
1127
1128
1129
1130
1131
1132
1133
1134
1135
1136
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146
1147
1148
1149
1150
1151
1152
1153
1154
1155
1156
1157
1158
1159
1160
1161
1162
1163
1164
1165
1166
1167
1168
1169
1170
1171
1172
1173
1174
1175
1176
1177
1178
1179
1180
1181
1182
1183
1184
1185
1186
1187
1188
1189
1190
1191
1192
1193
1194
1195
1196
1197
1198
1199
1200
1201
1202
1203
1204
1205
1206
1207
1208
1209
1210
1211
1212
1213
1214
1215
1216
1217
1218
1219
1220
1221
1222
1223
1224
1225
1226
1227
1228
1229
1230
1231
1232
1233
1234
1235
1236
1237
1238
1239
1240
1241
1242
1243
1244
1245
1246
1247
1248
1249
1250
1251
1252
1253
1254
1255
1256
1257
1258
1259
1260
1261
1262
1263
1264
1265
1266
1267
1268
1269
1270
1271
1272
1273
1274
1275
1276
1277
1278
1279
1280
1281
1282
1283
1284
1285
1286
1287
1288
1289
1290
1291
1292
1293
1294
1295
1296
1297
1298
1299
1300
1301
1302
1303
1304
1305
1306
1307
1308
1309
use std::collections::{HashMap, HashSet};
use std::error;
use std::fmt;
use std::error::{Error};
use std::hash::{Hash, Hasher};
use std::iter::FromIterator;
use slog::Drain;
use xc2bit::*;
use *;
use objpool::*;
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
pub struct AssignedLocation {
pub fb: u32,
pub i: u32,
}
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
pub enum InputGraphIOInputType {
Reg,
Xor,
}
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
pub enum InputGraphIOOEType {
PTerm(ObjPoolIndex<InputGraphPTerm>),
GTS(ObjPoolIndex<InputGraphBufgGTS>),
OpenDrain,
}
#[derive(Clone, Debug, PartialEq, Eq, Hash, Serialize, Deserialize)]
pub struct InputGraphIOBuf {
pub input: Option<InputGraphIOInputType>,
pub oe: Option<InputGraphIOOEType>,
pub schmitt_trigger: bool,
pub termination_enabled: bool,
pub slew_is_fast: bool,
pub uses_data_gate: bool,
}
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
pub enum InputGraphRegRSType {
PTerm(ObjPoolIndex<InputGraphPTerm>),
GSR(ObjPoolIndex<InputGraphBufgGSR>),
}
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
pub enum InputGraphRegInputType {
Pin,
Xor,
}
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
pub enum InputGraphRegClockType {
PTerm(ObjPoolIndex<InputGraphPTerm>),
GCK(ObjPoolIndex<InputGraphBufgClk>),
}
#[derive(Clone, Debug, PartialEq, Eq, Hash, Serialize, Deserialize)]
pub struct InputGraphReg {
pub mode: XC2MCRegMode,
pub clkinv: bool,
pub clkddr: bool,
pub init_state: bool,
pub set_input: Option<InputGraphRegRSType>,
pub reset_input: Option<InputGraphRegRSType>,
pub ce_input: Option<ObjPoolIndex<InputGraphPTerm>>,
pub dt_input: InputGraphRegInputType,
pub clk_input: InputGraphRegClockType,
}
#[derive(Clone, Debug, PartialEq, Eq, Hash, Serialize, Deserialize)]
pub struct InputGraphXor {
pub orterm_inputs: Vec<ObjPoolIndex<InputGraphPTerm>>,
pub andterm_input: Option<ObjPoolIndex<InputGraphPTerm>>,
pub invert_out: bool,
}
#[derive(Clone, Debug, PartialEq, Eq, Hash, Serialize, Deserialize)]
pub struct InputGraphMacrocell {
pub name: String,
pub requested_loc: Option<RequestedLocation>,
pub io_bits: Option<InputGraphIOBuf>,
pub reg_bits: Option<InputGraphReg>,
pub xor_bits: Option<InputGraphXor>,
pub io_feedback_used: bool,
pub reg_feedback_used: bool,
pub xor_feedback_used: bool,
}
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
pub enum InputGraphMacrocellType {
PinOutput,
PinInputUnreg,
PinInputReg,
BuriedComb,
BuriedReg,
}
impl InputGraphMacrocellType {
pub fn is_pininput(&self) -> bool {
match self {
&InputGraphMacrocellType::PinOutput |
&InputGraphMacrocellType::BuriedComb |
&InputGraphMacrocellType::BuriedReg => false,
&InputGraphMacrocellType::PinInputReg |
&InputGraphMacrocellType::PinInputUnreg => true,
}
}
}
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
pub enum InputGraphPTermInputType {
Reg,
Xor,
Pin,
}
pub type InputGraphPTermInput = (InputGraphPTermInputType, ObjPoolIndex<InputGraphMacrocell>);
#[derive(Clone, Debug, Serialize, Deserialize)]
pub struct InputGraphPTerm {
pub name: String,
pub requested_loc: Option<RequestedLocation>,
pub inputs_true: Vec<InputGraphPTermInput>,
pub inputs_comp: Vec<InputGraphPTermInput>,
}
#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
pub struct InputGraphBufgClk {
pub name: String,
pub requested_loc: Option<RequestedLocation>,
pub input: ObjPoolIndex<InputGraphMacrocell>,
}
#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
pub struct InputGraphBufgGTS {
pub name: String,
pub requested_loc: Option<RequestedLocation>,
pub input: ObjPoolIndex<InputGraphMacrocell>,
pub invert: bool,
}
#[derive(Clone, PartialEq, Eq, Hash, Debug, Serialize, Deserialize)]
pub struct InputGraphBufgGSR {
pub name: String,
pub requested_loc: Option<RequestedLocation>,
pub input: ObjPoolIndex<InputGraphMacrocell>,
pub invert: bool,
}
#[derive(Debug, PartialEq, Eq, Hash, Serialize, Deserialize)]
pub struct InputGraph {
pub mcs: ObjPool<InputGraphMacrocell>,
pub pterms: ObjPool<InputGraphPTerm>,
pub bufg_clks: ObjPool<InputGraphBufgClk>,
pub bufg_gts: ObjPool<InputGraphBufgGTS>,
pub bufg_gsr: ObjPool<InputGraphBufgGSR>,
}
#[derive(Copy, Clone, PartialEq, Eq, Hash, Debug)]
enum InputGraphAnyPoolIdx {
Macrocell(ObjPoolIndex<InputGraphMacrocell>),
PTerm(ObjPoolIndex<InputGraphPTerm>),
BufgClk(ObjPoolIndex<InputGraphBufgClk>),
BufgGTS(ObjPoolIndex<InputGraphBufgGTS>),
BufgGSR(ObjPoolIndex<InputGraphBufgGSR>),
}
impl slog::Value for InputGraphAnyPoolIdx {
fn serialize(&self, _record: &slog::Record, key: slog::Key, serializer: &mut slog::Serializer) -> slog::Result {
match self {
&InputGraphAnyPoolIdx::Macrocell(i) => {
serializer.emit_usize(key, i.get_raw_i())?;
serializer.emit_str("inputgraph type", "macrocell")
},
&InputGraphAnyPoolIdx::PTerm(i) => {
serializer.emit_usize(key, i.get_raw_i())?;
serializer.emit_str("inputgraph type", "pterm")
},
&InputGraphAnyPoolIdx::BufgClk(i) => {
serializer.emit_usize(key, i.get_raw_i())?;
serializer.emit_str("inputgraph type", "bufg")
},
&InputGraphAnyPoolIdx::BufgGTS(i) => {
serializer.emit_usize(key, i.get_raw_i())?;
serializer.emit_str("inputgraph type", "bufgts")
},
&InputGraphAnyPoolIdx::BufgGSR(i) => {
serializer.emit_usize(key, i.get_raw_i())?;
serializer.emit_str("inputgraph type", "bufgsr")
},
}
}
}
impl InputGraphMacrocell {
pub fn get_type(&self) -> InputGraphMacrocellType {
if self.io_bits.is_some() {
if self.io_bits.as_ref().unwrap().input.is_some() {
InputGraphMacrocellType::PinOutput
} else {
if self.reg_bits.is_some() {
InputGraphMacrocellType::PinInputReg
} else {
InputGraphMacrocellType::PinInputUnreg
}
}
} else {
if self.reg_bits.is_some() {
InputGraphMacrocellType::BuriedReg
} else {
InputGraphMacrocellType::BuriedComb
}
}
}
}
impl PartialEq for InputGraphPTerm {
fn eq(&self, other: &InputGraphPTerm) -> bool {
let a_inp_true_hash: HashSet<(InputGraphPTermInputType, ObjPoolIndex<InputGraphMacrocell>)> =
HashSet::from_iter(self.inputs_true.iter().cloned());
let a_inp_comp_hash: HashSet<(InputGraphPTermInputType, ObjPoolIndex<InputGraphMacrocell>)> =
HashSet::from_iter(self.inputs_comp.iter().cloned());
let b_inp_true_hash: HashSet<(InputGraphPTermInputType, ObjPoolIndex<InputGraphMacrocell>)> =
HashSet::from_iter(other.inputs_true.iter().cloned());
let b_inp_comp_hash: HashSet<(InputGraphPTermInputType, ObjPoolIndex<InputGraphMacrocell>)> =
HashSet::from_iter(other.inputs_comp.iter().cloned());
a_inp_true_hash == b_inp_true_hash && a_inp_comp_hash == b_inp_comp_hash
}
}
impl Eq for InputGraphPTerm { }
impl Hash for InputGraphPTerm {
fn hash<H: Hasher>(&self, state: &mut H) {
for x in &self.inputs_true {
x.hash(state);
}
for x in &self.inputs_comp {
x.hash(state);
}
}
}
fn combine_names(old: &str, additional: &str) -> String {
if old == "" {
additional.to_owned()
} else {
format!("{}_{}", old, additional)
}
}
fn combine_locs(old: Option<RequestedLocation>, additional: Option<RequestedLocation>, logger: &slog::Logger)
-> Result<Option<RequestedLocation>, IntermedToInputError> {
if old.is_none() {
Ok(additional)
} else if additional.is_none() {
Ok(old)
} else {
let old_ = old.unwrap();
let new = additional.unwrap();
if old_.fb != new.fb {
error!(logger, "intermed2input - LOCs that need to agree do not agree on FB";
"first index" => old_.fb,
"second index" => new.fb);
Err(IntermedToInputError::LocMismatchedFB(old_.fb, new.fb))
} else {
if old_.i.is_none() {
Ok(additional)
} else if new.i.is_none() {
Ok(old)
} else {
let old_i = old_.i.unwrap();
let new_i = new.i.unwrap();
if old_i != new_i {
error!(logger, "intermed2input - LOCs that need to agree do not agree on macrocell";
"first index" => old_i,
"second index" => new_i);
Err(IntermedToInputError::LocMismatchedMC(old_i, new_i))
} else {
Ok(old)
}
}
}
}
}
#[derive(Clone, Debug, PartialEq, Eq)]
pub enum IntermedToInputError {
WrongConnectionType(String),
WrongTiedValue(String),
WrongPTermInputs(String),
TooManyFeedbacksUsed(String),
LocMismatchedFB(u32, u32),
LocMismatchedMC(u32, u32),
SanityCheckError(&'static str),
}
impl error::Error for IntermedToInputError {
fn description(&self) -> &'static str {
match self {
&IntermedToInputError::WrongConnectionType(_) => "node is connected to another node of the wrong type",
&IntermedToInputError::WrongTiedValue(_) => "node input is tied to a disallowed constant",
&IntermedToInputError::WrongPTermInputs(_) => "p-term inputs incorrect (duplicate or in true+comp)",
&IntermedToInputError::TooManyFeedbacksUsed(_) => "too many feedback paths used (XOR + register + IO)",
&IntermedToInputError::LocMismatchedFB(_, _) => "two LOC constraints have mismatched FB index",
&IntermedToInputError::LocMismatchedMC(_, _) => "two LOC constraints have mismatched macrocell index",
&IntermedToInputError::SanityCheckError(_) => "sanity check failed",
}
}
fn cause(&self) -> Option<&error::Error> {
None
}
}
impl fmt::Display for IntermedToInputError {
fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
match self {
&IntermedToInputError::WrongConnectionType(ref s) |
&IntermedToInputError::WrongTiedValue(ref s) |
&IntermedToInputError::WrongPTermInputs(ref s) |
&IntermedToInputError::TooManyFeedbacksUsed(ref s) => {
write!(f, "{} - {}", self.description(), s)
},
&IntermedToInputError::SanityCheckError(s) => {
write!(f, "{} - {}", self.description(), s)
},
&IntermedToInputError::LocMismatchedFB(i1, i2) |
&IntermedToInputError::LocMismatchedMC(i1, i2) => {
write!(f, "{} - {}/{}", self.description(), i1, i2)
},
}
}
}
impl InputGraph {
pub fn from_intermed_graph<L: Into<Option<slog::Logger>>>(g: &IntermediateGraph, logger: L)
-> Result<Self, IntermedToInputError> {
let logger = logger.into().unwrap_or(slog::Logger::root(slog_stdlog::StdLog.fuse(), o!()));
let mut mcs = ObjPool::new();
let mut pterms = ObjPool::new();
let mut bufg_clks = ObjPool::new();
let mut bufg_gts = ObjPool::new();
let mut bufg_gsr = ObjPool::new();
let mut mcs_map = HashMap::new();
let mut pterms_map = HashMap::new();
let mut bufg_clks_map = HashMap::new();
let mut bufg_gts_map = HashMap::new();
let mut bufg_gsr_map = HashMap::new();
let mut consumed_inputs = HashSet::new();
let gathered_mcs = g.gather_macrocells(logger.new(o!())).unwrap();
for i in 0..gathered_mcs.len() {
let dummy_mc = InputGraphMacrocell {
name: String::from(""),
requested_loc: None,
io_bits: None,
reg_bits: None,
xor_bits: None,
io_feedback_used: false,
reg_feedback_used: false,
xor_feedback_used: false,
};
let newg_idx = mcs.insert(dummy_mc);
let oldg_idx = gathered_mcs[i];
mcs_map.insert(oldg_idx, newg_idx);
}
#[allow(non_camel_case_types)]
struct process_one_intermed_node_state<'a> {
g: &'a IntermediateGraph,
mcs: &'a mut ObjPool<InputGraphMacrocell>,
pterms: &'a mut ObjPool<InputGraphPTerm>,
bufg_clks: &'a mut ObjPool<InputGraphBufgClk>,
bufg_gts: &'a mut ObjPool<InputGraphBufgGTS>,
bufg_gsr: &'a mut ObjPool<InputGraphBufgGSR>,
mcs_map: &'a mut HashMap<ObjPoolIndex<IntermediateGraphNode>, ObjPoolIndex<InputGraphMacrocell>>,
pterms_map: &'a mut HashMap<ObjPoolIndex<IntermediateGraphNode>, ObjPoolIndex<InputGraphPTerm>>,
bufg_clks_map: &'a mut HashMap<ObjPoolIndex<IntermediateGraphNode>, ObjPoolIndex<InputGraphBufgClk>>,
bufg_gts_map: &'a mut HashMap<ObjPoolIndex<IntermediateGraphNode>, ObjPoolIndex<InputGraphBufgGTS>>,
bufg_gsr_map: &'a mut HashMap<ObjPoolIndex<IntermediateGraphNode>, ObjPoolIndex<InputGraphBufgGSR>>,
consumed_inputs: &'a mut HashSet<usize>,
}
fn process_one_intermed_node<'a>(s: &mut process_one_intermed_node_state<'a>,
n_idx: ObjPoolIndex<IntermediateGraphNode>, logger: &slog::Logger)
-> Result<InputGraphAnyPoolIdx, IntermedToInputError> {
let n = s.g.nodes.get(n_idx);
if s.consumed_inputs.contains(&n_idx.get_raw_i()) {
let ret = match n.variant {
IntermediateGraphNodeVariant::IOBuf{..} |
IntermediateGraphNodeVariant::InBuf{..} |
IntermediateGraphNodeVariant::Reg{..} |
IntermediateGraphNodeVariant::Xor{..} |
IntermediateGraphNodeVariant::OrTerm{..} =>
InputGraphAnyPoolIdx::Macrocell(*s.mcs_map.get(&n_idx).unwrap()),
IntermediateGraphNodeVariant::AndTerm{..} =>
InputGraphAnyPoolIdx::PTerm(*s.pterms_map.get(&n_idx).unwrap()),
IntermediateGraphNodeVariant::BufgClk{..} =>
InputGraphAnyPoolIdx::BufgClk(*s.bufg_clks_map.get(&n_idx).unwrap()),
IntermediateGraphNodeVariant::BufgGTS{..} =>
InputGraphAnyPoolIdx::BufgGTS(*s.bufg_gts_map.get(&n_idx).unwrap()),
IntermediateGraphNodeVariant::BufgGSR{..} =>
InputGraphAnyPoolIdx::BufgGSR(*s.bufg_gsr_map.get(&n_idx).unwrap()),
};
debug!(logger, "intermed2input - found existing node";
"name" => &n.name,
"intermed" => n_idx,
"inputgraph" => ret);
return Ok(ret);
}
s.consumed_inputs.insert(n_idx.get_raw_i());
match n.variant {
IntermediateGraphNodeVariant::IOBuf{oe, input, schmitt_trigger, termination_enabled,
slew_is_fast, uses_data_gate, ..} => {
let newg_idx = *s.mcs_map.get(&n_idx).unwrap();
let old_input = input;
let input = {
if oe.is_some() && oe.unwrap() == s.g.vss_net {
None
} else if input.is_some() {
if input.unwrap() == s.g.vss_net {
if oe.is_none() || oe.unwrap() == s.g.vdd_net || oe.unwrap() == s.g.vss_net {
error!(logger, "intermed2input - input is tied low but OE isn't used";
"name" => &n.name);
return Err(IntermedToInputError::WrongTiedValue(n.name.to_owned()));
}
let input_n = s.g.nets.get(oe.unwrap()).source.unwrap();
let input_type = match s.g.nodes.get(input_n).variant {
IntermediateGraphNodeVariant::Xor{..} => {
Some(InputGraphIOInputType::Xor)
},
IntermediateGraphNodeVariant::Reg{..} => {
Some(InputGraphIOInputType::Reg)
},
_ => {
error!(logger, "intermed2input - input is not an XOR or a register";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
},
};
assert!(!s.mcs_map.contains_key(&input_n));
s.mcs_map.insert(input_n, newg_idx);
process_one_intermed_node(s, input_n, logger)?;
input_type
} else if input.unwrap() == s.g.vdd_net {
error!(logger, "intermed2input - input is tied to a constant one";
"name" => &n.name);
return Err(IntermedToInputError::WrongTiedValue(n.name.to_owned()));
} else {
let input_n = s.g.nets.get(input.unwrap()).source.unwrap();
let input_type = match s.g.nodes.get(input_n).variant {
IntermediateGraphNodeVariant::Xor{..} => {
Some(InputGraphIOInputType::Xor)
},
IntermediateGraphNodeVariant::Reg{..} => {
Some(InputGraphIOInputType::Reg)
},
_ => {
error!(logger, "intermed2input - input is not an XOR or a register";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
},
};
assert!(!s.mcs_map.contains_key(&input_n));
s.mcs_map.insert(input_n, newg_idx);
process_one_intermed_node(s, input_n, logger)?;
input_type
}
} else {
None
}
};
let oe = {
if oe.is_some() {
if oe.unwrap() == s.g.vdd_net || oe.unwrap() == s.g.vss_net {
None
} else {
if old_input.is_some() && old_input.unwrap() == s.g.vss_net {
Some(InputGraphIOOEType::OpenDrain)
} else {
let oe_n = s.g.nets.get(oe.unwrap()).source.unwrap();
let oe_newg_n = process_one_intermed_node(s, oe_n, logger)?;
Some(match oe_newg_n {
InputGraphAnyPoolIdx::PTerm(x) => InputGraphIOOEType::PTerm(x),
InputGraphAnyPoolIdx::BufgGTS(x) => InputGraphIOOEType::GTS(x),
_ => {
error!(logger, "intermed2input - OE is not a P-term or GTS";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
},
})
}
}
} else {
None
}
};
{
info!(logger, "intermed2input - adding IO bits";
"name" => &n.name,
"intermed" => n_idx,
"inputgraph" => newg_idx);
let newg_n = s.mcs.get_mut(newg_idx);
assert!(newg_n.io_bits.is_none());
newg_n.name = combine_names(&newg_n.name, &n.name);
newg_n.requested_loc = combine_locs(newg_n.requested_loc, n.location, logger)?;
newg_n.io_bits = Some(InputGraphIOBuf {
input,
oe,
schmitt_trigger,
termination_enabled,
slew_is_fast,
uses_data_gate,
});
}
Ok(InputGraphAnyPoolIdx::Macrocell(newg_idx))
},
IntermediateGraphNodeVariant::InBuf{schmitt_trigger, termination_enabled, uses_data_gate, ..} => {
let newg_idx = *s.mcs_map.get(&n_idx).unwrap();
{
info!(logger, "intermed2input - adding input bits";
"name" => &n.name,
"intermed" => n_idx,
"inputgraph" => newg_idx);
let newg_n = s.mcs.get_mut(newg_idx);
assert!(newg_n.io_bits.is_none());
newg_n.name = combine_names(&newg_n.name, &n.name);
newg_n.requested_loc = combine_locs(newg_n.requested_loc, n.location, logger)?;
newg_n.io_bits = Some(InputGraphIOBuf {
input: None,
oe: None,
schmitt_trigger,
termination_enabled,
slew_is_fast: true,
uses_data_gate,
});
}
Ok(InputGraphAnyPoolIdx::Macrocell(newg_idx))
},
IntermediateGraphNodeVariant::Xor{orterm_input, andterm_input, invert_out, ..} => {
let newg_idx = *s.mcs_map.get(&n_idx).unwrap();
let mut orterm_inputs = Vec::new();
if orterm_input.is_some() {
let or_n = s.g.nets.get(orterm_input.unwrap()).source.unwrap();
s.consumed_inputs.insert(or_n.get_raw_i());
assert!(!s.mcs_map.contains_key(&or_n));
s.mcs_map.insert(or_n, newg_idx);
if let IntermediateGraphNodeVariant::OrTerm{ref inputs, ..} = s.g.nodes.get(or_n).variant {
for x in inputs {
let input_n = s.g.nets.get(*x).source.unwrap();
if let IntermediateGraphNodeVariant::AndTerm{..} =
s.g.nodes.get(input_n).variant {} else {
error!(logger, "intermed2input - input is not a P-term";
"name" => &s.g.nodes.get(input_n).name);
return Err(IntermedToInputError::WrongConnectionType(
s.g.nodes.get(input_n).name.to_owned()));
}
let input_newg_any = process_one_intermed_node(s, input_n, logger)?;
let input_newg = if let InputGraphAnyPoolIdx::PTerm(x) = input_newg_any { x } else {
panic!("Internal error - not a product term?");
};
orterm_inputs.push(input_newg);
}
} else {
error!(logger, "intermed2input - input is not an OR term";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
}
}
let mut invert_out = invert_out;
let ptc_input = {
if andterm_input.is_some() {
if andterm_input.unwrap() == s.g.vdd_net {
invert_out = !invert_out;
None
} else if andterm_input.unwrap() == s.g.vss_net {
None
} else {
let ptc_n = s.g.nets.get(andterm_input.unwrap()).source.unwrap();
let ptc_newg_n = process_one_intermed_node(s, ptc_n, logger)?;
if let InputGraphAnyPoolIdx::PTerm(x) = ptc_newg_n {
Some(x)
} else {
error!(logger, "intermed2input - PTC input is not a P-term";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
}
}
} else {
None
}
};
{
info!(logger, "intermed2input - adding XOR bits";
"name" => &n.name,
"intermed" => n_idx,
"inputgraph" => newg_idx);
let newg_n = s.mcs.get_mut(newg_idx);
assert!(newg_n.xor_bits.is_none());
newg_n.name = combine_names(&newg_n.name, &n.name);
newg_n.requested_loc = combine_locs(newg_n.requested_loc, n.location, logger)?;
newg_n.xor_bits = Some(InputGraphXor {
orterm_inputs,
andterm_input: ptc_input,
invert_out,
});
}
Ok(InputGraphAnyPoolIdx::Macrocell(newg_idx))
},
IntermediateGraphNodeVariant::AndTerm{ref inputs_true, ref inputs_comp, ..} => {
let mut inputs_true_new = Vec::new();
for x in inputs_true {
let input_n = s.g.nets.get(*x).source.unwrap();
let input_type = match s.g.nodes.get(input_n).variant {
IntermediateGraphNodeVariant::Xor{..} => InputGraphPTermInputType::Xor,
IntermediateGraphNodeVariant::Reg{..} => InputGraphPTermInputType::Reg,
IntermediateGraphNodeVariant::IOBuf{..} |
IntermediateGraphNodeVariant::InBuf{..} => InputGraphPTermInputType::Pin,
_ => {
error!(logger, "intermed2input - input is not a register, XOR, or IO pad";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
},
};
let input_newg_any = process_one_intermed_node(s, input_n, logger)?;
let input_newg = if let InputGraphAnyPoolIdx::Macrocell(x) = input_newg_any { x } else {
panic!("Internal error - not a macrocell?");
};
{
let input_newg_n = s.mcs.get_mut(input_newg);
match input_type {
InputGraphPTermInputType::Pin => input_newg_n.io_feedback_used = true,
InputGraphPTermInputType::Xor => input_newg_n.xor_feedback_used = true,
InputGraphPTermInputType::Reg => input_newg_n.reg_feedback_used = true,
}
}
inputs_true_new.push((input_type, input_newg));
}
let mut inputs_comp_new = Vec::new();
for x in inputs_comp {
let input_n = s.g.nets.get(*x).source.unwrap();
let input_type = match s.g.nodes.get(input_n).variant {
IntermediateGraphNodeVariant::Xor{..} => InputGraphPTermInputType::Xor,
IntermediateGraphNodeVariant::Reg{..} => InputGraphPTermInputType::Reg,
IntermediateGraphNodeVariant::IOBuf{..} |
IntermediateGraphNodeVariant::InBuf{..} => InputGraphPTermInputType::Pin,
_ => {
error!(logger, "intermed2input - input is not a register, XOR, or IO pad";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
},
};
let input_newg_any = process_one_intermed_node(s, input_n, logger)?;
let input_newg = if let InputGraphAnyPoolIdx::Macrocell(x) = input_newg_any { x } else {
panic!("Internal error - not a macrocell?");
};
{
let input_newg_n = s.mcs.get_mut(input_newg);
match input_type {
InputGraphPTermInputType::Pin => input_newg_n.io_feedback_used = true,
InputGraphPTermInputType::Xor => input_newg_n.xor_feedback_used = true,
InputGraphPTermInputType::Reg => input_newg_n.reg_feedback_used = true,
}
}
inputs_comp_new.push((input_type, input_newg));
}
let newg_n = InputGraphPTerm {
name: n.name.clone(),
requested_loc: n.location,
inputs_true: inputs_true_new,
inputs_comp: inputs_comp_new,
};
let newg_idx = s.pterms.insert(newg_n);
info!(logger, "intermed2input - adding P-term";
"name" => &n.name,
"intermed" => n_idx,
"inputgraph" => newg_idx);
s.pterms_map.insert(n_idx, newg_idx);
Ok(InputGraphAnyPoolIdx::PTerm(newg_idx))
},
IntermediateGraphNodeVariant::OrTerm{..} => {
panic!("Internal error - unexpected OR gate here");
},
IntermediateGraphNodeVariant::Reg{mode, clkinv, clkddr, init_state, set_input, reset_input,
ce_input, dt_input, clk_input, ..} => {
let newg_idx = *s.mcs_map.get(&n_idx).unwrap();
let dt_input = {
let input_n = s.g.nets.get(dt_input).source.unwrap();
let input_type = match s.g.nodes.get(input_n).variant {
IntermediateGraphNodeVariant::Xor{..} => {
InputGraphRegInputType::Xor
},
IntermediateGraphNodeVariant::IOBuf{..} |
IntermediateGraphNodeVariant::InBuf{..} => {
InputGraphRegInputType::Pin
},
_ => {
error!(logger, "intermed2input - D/T input is not an XOR or IO pad";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
},
};
if input_type == InputGraphRegInputType::Xor {
assert!(!s.mcs_map.contains_key(&input_n));
s.mcs_map.insert(input_n, newg_idx);
process_one_intermed_node(s, input_n, logger)?;
}
input_type
};
let clk_input = {
let clk_n = s.g.nets.get(clk_input).source.unwrap();
let clk_newg_n = process_one_intermed_node(s, clk_n, logger)?;
if let InputGraphAnyPoolIdx::PTerm(x) = clk_newg_n {
InputGraphRegClockType::PTerm(x)
} else if let InputGraphAnyPoolIdx::BufgClk(x) = clk_newg_n {
InputGraphRegClockType::GCK(x)
} else {
error!(logger, "intermed2input - clock input is not a P-term or global clock";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
}
};
let ce_input = {
if ce_input.is_some() {
let ce_n = s.g.nets.get(ce_input.unwrap()).source.unwrap();
let ce_newg_n = process_one_intermed_node(s, ce_n, logger)?;
if let InputGraphAnyPoolIdx::PTerm(x) = ce_newg_n {
Some(x)
} else {
error!(logger, "intermed2input - CE input is not a P-term";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
}
} else {
None
}
};
let set_input = {
if set_input.is_some() {
if set_input.unwrap() == s.g.vss_net {
None
} else if set_input.unwrap() == s.g.vdd_net {
error!(logger, "intermed2input - set input cannot be tied high";
"name" => &n.name);
return Err(IntermedToInputError::WrongTiedValue(n.name.to_owned()));
} else {
let set_n = s.g.nets.get(set_input.unwrap()).source.unwrap();
let set_newg_n = process_one_intermed_node(s, set_n, logger)?;
if let InputGraphAnyPoolIdx::PTerm(x) = set_newg_n {
Some(InputGraphRegRSType::PTerm(x))
} else if let InputGraphAnyPoolIdx::BufgGSR(x) = set_newg_n {
Some(InputGraphRegRSType::GSR(x))
} else {
error!(logger, "intermed2input - set input is not a P-term or GSR";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
}
}
} else {
None
}
};
let reset_input = {
if reset_input.is_some() {
if reset_input.unwrap() == s.g.vss_net {
None
} else if reset_input.unwrap() == s.g.vdd_net {
error!(logger, "intermed2input - reset input cannot be tied high";
"name" => &n.name);
return Err(IntermedToInputError::WrongTiedValue(n.name.to_owned()));
} else {
let reset_n = s.g.nets.get(reset_input.unwrap()).source.unwrap();
let reset_newg_n = process_one_intermed_node(s, reset_n, logger)?;
if let InputGraphAnyPoolIdx::PTerm(x) = reset_newg_n {
Some(InputGraphRegRSType::PTerm(x))
} else if let InputGraphAnyPoolIdx::BufgGSR(x) = reset_newg_n {
Some(InputGraphRegRSType::GSR(x))
} else {
error!(logger, "intermed2input - reset input is not a P-term or GSR";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
}
}
} else {
None
}
};
{
info!(logger, "intermed2input - adding register bits";
"name" => &n.name,
"intermed" => n_idx,
"inputgraph" => newg_idx);
let newg_n = s.mcs.get_mut(newg_idx);
assert!(newg_n.reg_bits.is_none());
newg_n.name = combine_names(&newg_n.name, &n.name);
newg_n.requested_loc = combine_locs(newg_n.requested_loc, n.location, logger)?;
newg_n.reg_bits = Some(InputGraphReg {
mode,
clkinv,
clkddr,
init_state,
set_input,
reset_input,
ce_input,
dt_input,
clk_input,
});
}
Ok(InputGraphAnyPoolIdx::Macrocell(newg_idx))
},
IntermediateGraphNodeVariant::BufgClk{input, ..} => {
let input_n = s.g.nets.get(input).source.unwrap();
match s.g.nodes.get(input_n).variant {
IntermediateGraphNodeVariant::IOBuf{..} |
IntermediateGraphNodeVariant::InBuf{..} => {},
_ => {
error!(logger, "intermed2input - input is not an IO pad";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
},
};
let input_newg_any = process_one_intermed_node(s, input_n, logger)?;
let input_newg = if let InputGraphAnyPoolIdx::Macrocell(x) = input_newg_any { x } else {
panic!("Internal error - not a macrocell?");
};
let newg_n = InputGraphBufgClk {
name: n.name.clone(),
requested_loc: n.location,
input: input_newg,
};
let newg_idx = s.bufg_clks.insert(newg_n);
info!(logger, "intermed2input - adding BUFG";
"name" => &n.name,
"intermed" => n_idx,
"inputgraph" => newg_idx);
s.bufg_clks_map.insert(n_idx, newg_idx);
Ok(InputGraphAnyPoolIdx::BufgClk(newg_idx))
},
IntermediateGraphNodeVariant::BufgGTS{input, invert, ..} => {
let input_n = s.g.nets.get(input).source.unwrap();
match s.g.nodes.get(input_n).variant {
IntermediateGraphNodeVariant::IOBuf{..} |
IntermediateGraphNodeVariant::InBuf{..} => {},
_ => {
error!(logger, "intermed2input - input is not an IO pad";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
},
};
let input_newg_any = process_one_intermed_node(s, input_n, logger)?;
let input_newg = if let InputGraphAnyPoolIdx::Macrocell(x) = input_newg_any { x } else {
panic!("Internal error - not a macrocell?");
};
let newg_n = InputGraphBufgGTS {
name: n.name.clone(),
requested_loc: n.location,
input: input_newg,
invert,
};
let newg_idx = s.bufg_gts.insert(newg_n);
info!(logger, "intermed2input - adding BUFGTS";
"name" => &n.name,
"intermed" => n_idx,
"inputgraph" => newg_idx);
s.bufg_gts_map.insert(n_idx, newg_idx);
Ok(InputGraphAnyPoolIdx::BufgGTS(newg_idx))
},
IntermediateGraphNodeVariant::BufgGSR{input, invert, ..} => {
let input_n = s.g.nets.get(input).source.unwrap();
match s.g.nodes.get(input_n).variant {
IntermediateGraphNodeVariant::IOBuf{..} |
IntermediateGraphNodeVariant::InBuf{..} => {},
_ => {
error!(logger, "intermed2input - input is not an IO pad";
"name" => &n.name);
return Err(IntermedToInputError::WrongConnectionType(n.name.to_owned()));
},
};
let input_newg_any = process_one_intermed_node(s, input_n, logger)?;
let input_newg = if let InputGraphAnyPoolIdx::Macrocell(x) = input_newg_any { x } else {
panic!("Internal error - not a macrocell?");
};
let newg_n = InputGraphBufgGSR {
name: n.name.clone(),
requested_loc: n.location,
input: input_newg,
invert,
};
let newg_idx = s.bufg_gsr.insert(newg_n);
info!(logger, "intermed2input - adding BUFGSR";
"name" => &n.name,
"intermed" => n_idx,
"inputgraph" => newg_idx);
s.bufg_gsr_map.insert(n_idx, newg_idx);
Ok(InputGraphAnyPoolIdx::BufgGSR(newg_idx))
},
}
}
{
let mut s = process_one_intermed_node_state {
g,
mcs: &mut mcs,
pterms: &mut pterms,
bufg_clks: &mut bufg_clks,
bufg_gts: &mut bufg_gts,
bufg_gsr: &mut bufg_gsr,
mcs_map: &mut mcs_map,
pterms_map: &mut pterms_map,
bufg_clks_map: &mut bufg_clks_map,
bufg_gts_map: &mut bufg_gts_map,
bufg_gsr_map: &mut bufg_gsr_map,
consumed_inputs: &mut consumed_inputs,
};
for oldg_mc in gathered_mcs {
process_one_intermed_node(&mut s, oldg_mc, &logger)?;
}
}
for i in 0..g.nodes.len() {
if !consumed_inputs.contains(&i) {
panic!("Internal error - did not consume all intermediate inputs");
}
}
let mut ret = Self {
mcs,
pterms,
bufg_clks,
bufg_gts,
bufg_gsr,
};
ret.unfuse_pterms(&logger);
ret.sanity_check(&logger)?;
Ok(ret)
}
fn sanity_check(&self, logger: &slog::Logger) -> Result<(), IntermedToInputError> {
for x in self.mcs.iter() {
if x.io_feedback_used && x.io_bits.is_none() {
error!(logger, "intermed2input (sanity) - the IO part of the macrocell was used, \
but the IO data is missing";
"name" => &x.name);
return Err(IntermedToInputError::SanityCheckError(
"Used IO input but there is no IO data?"));
}
if x.reg_feedback_used && x.reg_bits.is_none() {
error!(logger, "intermed2input (sanity) - the register part of the macrocell was used, \
but the register data is missing";
"name" => &x.name);
return Err(IntermedToInputError::SanityCheckError(
"Used register input but there is no register data?"));
}
if x.xor_feedback_used && x.xor_bits.is_none() {
error!(logger, "intermed2input (sanity) - the XOR part of the macrocell was used, \
but the XOR data is missing";
"name" => &x.name);
return Err(IntermedToInputError::SanityCheckError(
"Used XOR input but there is no XOR data?"));
}
if x.io_feedback_used && x.reg_feedback_used && x.xor_feedback_used {
error!(logger, "intermed2input (sanity) - used more than the possible feedback paths";
"name" => &x.name);
return Err(IntermedToInputError::TooManyFeedbacksUsed(x.name.to_owned()));
}
}
for pt in self.pterms.iter() {
let inputs_true_set: HashSet<(InputGraphPTermInputType, ObjPoolIndex<InputGraphMacrocell>)> =
HashSet::from_iter(pt.inputs_true.iter().cloned());
let inputs_comp_set: HashSet<(InputGraphPTermInputType, ObjPoolIndex<InputGraphMacrocell>)> =
HashSet::from_iter(pt.inputs_comp.iter().cloned());
if inputs_true_set.len() != pt.inputs_true.len() {
error!(logger, "intermed2input (sanity) - duplicate true input to p-term";
"name" => &pt.name);
return Err(IntermedToInputError::WrongPTermInputs(pt.name.to_owned()));
}
if inputs_comp_set.len() != pt.inputs_comp.len() {
error!(logger, "intermed2input (sanity) - duplicate comp input to p-term";
"name" => &pt.name);
return Err(IntermedToInputError::WrongPTermInputs(pt.name.to_owned()));
}
if inputs_true_set.intersection(&inputs_comp_set).count() != 0 {
error!(logger, "intermed2input (sanity) - input to both true and comp input of p-term";
"name" => &pt.name);
return Err(IntermedToInputError::WrongPTermInputs(pt.name.to_owned()));
}
}
for x in self.mcs.iter() {
macro_rules! check_pterm {
($mc_req_loc:expr, $pt:expr) => {
if let Some(pt_req_loc) = self.pterms.get($pt).requested_loc {
if $mc_req_loc.fb != pt_req_loc.fb {
error!(logger, "intermed2input (sanity) - macrocell uses P-term in wrong FB";
"macrocell name" => &x.name,
"macrocell FB" => $mc_req_loc.fb,
"p-term FB" => pt_req_loc.fb);
return Err(IntermedToInputError::LocMismatchedFB($mc_req_loc.fb, pt_req_loc.fb));
}
}
}
}
if let Some(mc_req_loc) = x.requested_loc {
if let Some(ref xor) = x.xor_bits {
if let Some(pterm) = xor.andterm_input {
check_pterm!(mc_req_loc, pterm);
}
for &pterm in &xor.orterm_inputs {
check_pterm!(mc_req_loc, pterm);
}
}
if let Some(ref reg) = x.reg_bits {
if let Some(pterm) = reg.ce_input {
check_pterm!(mc_req_loc, pterm);
}
if let InputGraphRegClockType::PTerm(pterm) = reg.clk_input {
check_pterm!(mc_req_loc, pterm);
}
if let Some(InputGraphRegRSType::PTerm(pterm)) = reg.set_input {
check_pterm!(mc_req_loc, pterm);
}
if let Some(InputGraphRegRSType::PTerm(pterm)) = reg.reset_input {
check_pterm!(mc_req_loc, pterm);
}
}
if let Some(ref io) = x.io_bits {
if let Some(InputGraphIOOEType::PTerm(pterm)) = io.oe {
check_pterm!(mc_req_loc, pterm);
}
}
}
}
Ok(())
}
fn unfuse_pterms(&mut self, logger: &slog::Logger) {
let mut used_pterms = HashSet::new();
for mc in self.mcs.iter_mut() {
macro_rules! clone_pterm {
($pterm:expr) => {{
let cloned_pterm = self.pterms.get($pterm).clone();
debug!(logger, "cloning a P-term";
"pterm name" => &cloned_pterm.name,
"referencing node" => &mc.name);
let new_pterm = self.pterms.insert(cloned_pterm);
new_pterm
}}
}
if mc.xor_bits.is_some() {
let xor = mc.xor_bits.as_mut().unwrap();
if let Some(pterm) = xor.andterm_input {
if used_pterms.contains(&pterm) {
xor.andterm_input = Some(clone_pterm!(pterm));
}
used_pterms.insert(pterm);
}
for i in 0..xor.orterm_inputs.len() {
let pterm = xor.orterm_inputs[i];
if used_pterms.contains(&pterm) {
xor.orterm_inputs[i] = clone_pterm!(pterm);
}
used_pterms.insert(pterm);
}
}
if mc.reg_bits.is_some() {
let reg = mc.reg_bits.as_mut().unwrap();
if let Some(pterm) = reg.ce_input {
if used_pterms.contains(&pterm) {
reg.ce_input = Some(clone_pterm!(pterm));
}
used_pterms.insert(pterm);
}
if let InputGraphRegClockType::PTerm(pterm) = reg.clk_input {
if used_pterms.contains(&pterm) {
reg.clk_input = InputGraphRegClockType::PTerm(clone_pterm!(pterm));
}
used_pterms.insert(pterm);
}
if let Some(InputGraphRegRSType::PTerm(pterm)) = reg.set_input {
if used_pterms.contains(&pterm) {
reg.set_input = Some(InputGraphRegRSType::PTerm(clone_pterm!(pterm)));
}
used_pterms.insert(pterm);
}
if let Some(InputGraphRegRSType::PTerm(pterm)) = reg.reset_input {
if used_pterms.contains(&pterm) {
reg.reset_input = Some(InputGraphRegRSType::PTerm(clone_pterm!(pterm)));
}
used_pterms.insert(pterm);
}
}
if mc.io_bits.is_some() {
let io = mc.io_bits.as_mut().unwrap();
if let Some(InputGraphIOOEType::PTerm(pterm)) = io.oe {
if used_pterms.contains(&pterm) {
io.oe = Some(InputGraphIOOEType::PTerm(clone_pterm!(pterm)));
}
used_pterms.insert(pterm);
}
}
}
}
}
#[cfg(test)]
mod tests {
use super::*;
use std;
use std::fs::File;
use std::io::Read;
extern crate serde_json;
fn run_one_reftest(input_filename: &'static str) {
let input_path = std::path::Path::new(input_filename);
let mut input_data = Vec::new();
File::open(&input_path).unwrap().read_to_end(&mut input_data).unwrap();
let intermed_graph = serde_json::from_slice(&input_data).unwrap();
let our_data_structure = InputGraph::from_intermed_graph(&intermed_graph, None).unwrap();
let mut output_path = input_path.to_path_buf();
output_path.set_extension("out");
let mut output_data = Vec::new();
File::open(&output_path).unwrap().read_to_end(&mut output_data).unwrap();
let reference_data_structure = serde_json::from_slice(&output_data).unwrap();
assert_eq!(our_data_structure, reference_data_structure);
}
include!(concat!(env!("OUT_DIR"), "/netlist-reftests.rs"));
}