Module x86::msr [] [src]

MSR value list and function to read and write them.

Constants

APIC_BASE

Section 10.4.4, Local APIC Status and Location.

BIOS_UPDT_TRIG

BIOS Update Trigger Register.

DEBUGCTLMSR
EBL_CR_POWERON

Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.

IA32_APERF

Actual Performance Frequency Clock Count (RW) See Table 35-2.

IA32_APIC_BASE

APIC Location and Status (R/W) See Table 35-2. See Section 10.4.4, Local APIC Status and Location.

IA32_A_PMC0

(If CPUID.0AH: EAX[15:8] > 0) & IA32_PERF_CAPABILITIES[ 13] = 1

IA32_A_PMC1

(If CPUID.0AH: EAX[15:8] > 1) & IA32_PERF_CAPABILITIES[ 13] = 1

IA32_A_PMC2

(If CPUID.0AH: EAX[15:8] > 2) & IA32_PERF_CAPABILITIES[ 13] = 1

IA32_A_PMC3

(If CPUID.0AH: EAX[15:8] > 3) & IA32_PERF_CAPABILITIES[ 13] = 1

IA32_A_PMC4

(If CPUID.0AH: EAX[15:8] > 4) & IA32_PERF_CAPABILITIES[ 13] = 1

IA32_A_PMC5

(If CPUID.0AH: EAX[15:8] > 5) & IA32_PERF_CAPABILITIES[ 13] = 1

IA32_A_PMC6

(If CPUID.0AH: EAX[15:8] > 6) & IA32_PERF_CAPABILITIES[ 13] = 1

IA32_A_PMC7

(If CPUID.0AH: EAX[15:8] > 7) & IA32_PERF_CAPABILITIES[ 13] = 1

IA32_BIOS_SIGN_ID

BIOS Update Signature ID (R/W) See Table 35-2.

IA32_BIOS_UPDT_TRIG

BIOS Update Trigger Register (W) See Table 35-2.

IA32_CLOCK_MODULATION

Clock Modulation (R/W) See Table 35-2. IA32_CLOCK_MODULATION MSR was originally named IA32_THERM_CONTROL MSR.

IA32_CPU_DCA_CAP
IA32_DCA_0_CAP

06_2EH

IA32_DEBUGCTL

Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section.

IA32_DS_AREA

DS Save Area (R/W) See Table 35-2. Points to the DS buffer management area, which is used to manage the BTS and PEBS buffers. See Section 18.12.4, Debug Store (DS) Mechanism.

IA32_EFER

If ( CPUID.80000001.EDX.[bit 20] or CPUID.80000001.EDX.[bit 29])

IA32_ENERGY_PERF_BIAS

if CPUID.6H:ECX[3] = 1

IA32_FEATURE_CONTROL

Control Features in IA-32 Processor (R/W) See Table 35-2 (If CPUID.01H:ECX.[bit 5])

IA32_FIXED_CTR0

Fixed-Function Performance Counter Register 0 (R/W) See Table 35-2.

IA32_FIXED_CTR1

Fixed-Function Performance Counter Register 1 (R/W) See Table 35-2.

IA32_FIXED_CTR2

Fixed-Function Performance Counter Register 2 (R/W) See Table 35-2.

IA32_FIXED_CTR_CTRL

Fixed-Function-Counter Control Register (R/W) See Table 35-2.

IA32_FMASK

System Call Flag Mask (R/W) See Table 35-2.

IA32_FS_BASE

Map of BASE Address of FS (R/W) See Table 35-2.

IA32_GS_BASE

Map of BASE Address of GS (R/W) See Table 35-2.

IA32_KERNEL_GSBASE

Swap Target of BASE Address of GS (R/W) See Table 35-2.

IA32_KERNEL_GS_BASE

If CPUID.80000001.EDX.[bit 29] = 1

IA32_LSTAR

IA-32e Mode System Call Target Address (R/W) See Table 35-2.

IA32_MC0_ADDR

See Section 14.3.2.3., IA32_MCi_ADDR MSRs . The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC0_ADDR1

P6 Family Processors

IA32_MC0_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

IA32_MC0_CTL2

See Table 35-2.

IA32_MC0_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs. The IA32_MC0_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.

IA32_MC0_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

IA32_MC10_ADDR1

06_2EH

IA32_MC10_CTL

06_2EH

IA32_MC10_CTL2

See Table 35-2.

IA32_MC10_MISC

06_2EH

IA32_MC10_STATUS

06_2EH

IA32_MC11_ADDR1

06_2EH

IA32_MC11_CTL

06_2EH

IA32_MC11_CTL2

See Table 35-2.

IA32_MC11_MISC

06_2EH

IA32_MC11_STATUS

06_2EH

IA32_MC12_ADDR1

06_2EH

IA32_MC12_CTL

06_2EH

IA32_MC12_CTL2

See Table 35-2.

IA32_MC12_MISC

06_2EH

IA32_MC12_STATUS

06_2EH

IA32_MC13_ADDR1

06_2EH

IA32_MC13_CTL

06_2EH

IA32_MC13_CTL2

See Table 35-2.

IA32_MC13_MISC

06_2EH

IA32_MC13_STATUS

06_2EH

IA32_MC14_ADDR1

06_2EH

IA32_MC14_CTL

06_2EH

IA32_MC14_CTL2

See Table 35-2.

IA32_MC14_MISC

06_2EH

IA32_MC14_STATUS

06_2EH

IA32_MC15_ADDR1

06_2EH

IA32_MC15_CTL

06_2EH

IA32_MC15_CTL2

See Table 35-2.

IA32_MC15_MISC

06_2EH

IA32_MC15_STATUS

06_2EH

IA32_MC16_ADDR1

06_2EH

IA32_MC16_CTL

06_2EH

IA32_MC16_CTL2

See Table 35-2.

IA32_MC16_MISC

06_2EH

IA32_MC16_STATUS

06_2EH

IA32_MC17_ADDR1

06_2EH

IA32_MC17_CTL

06_2EH

IA32_MC17_CTL2

See Table 35-2.

IA32_MC17_MISC

06_2EH

IA32_MC17_STATUS

06_2EH

IA32_MC18_ADDR1

06_2EH

IA32_MC18_CTL

06_2EH

IA32_MC18_CTL2

See Table 35-2.

IA32_MC18_MISC

06_2EH

IA32_MC18_STATUS

06_2EH

IA32_MC19_ADDR1

06_2EH

IA32_MC19_CTL

06_2EH

IA32_MC19_CTL2

See Table 35-2.

IA32_MC19_MISC

06_2EH

IA32_MC19_STATUS

06_2EH

IA32_MC1_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The IA32_MC1_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

IA32_MC1_ADDR2

P6 Family Processors

IA32_MC1_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

IA32_MC1_CTL2

See Table 35-2.

IA32_MC1_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs. The IA32_MC1_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.

IA32_MC1_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

IA32_MC20_ADDR1

06_2EH

IA32_MC20_CTL

06_2EH

IA32_MC20_CTL2

See Table 35-2.

IA32_MC20_MISC

06_2EH

IA32_MC20_STATUS

06_2EH

IA32_MC21_ADDR1

06_2EH

IA32_MC21_CTL

06_2EH

IA32_MC21_CTL2

See Table 35-2.

IA32_MC21_MISC

06_2EH

IA32_MC21_STATUS

06_2EH

IA32_MC2_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.

IA32_MC2_ADDR1

P6 Family Processors

IA32_MC2_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

IA32_MC2_CTL2

See Table 35-2.

IA32_MC2_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs. The IA32_MC2_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC2_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.

IA32_MC2_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

IA32_MC3_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The IA32_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.

IA32_MC3_ADDR1

P6 Family Processors

IA32_MC3_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

IA32_MC3_CTL2

See Table 35-2.

IA32_MC3_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs. The IA32_MC3_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.

IA32_MC3_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

IA32_MC4_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The IA32_MC2_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.

IA32_MC4_ADDR1

P6 Family Processors

IA32_MC4_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

IA32_MC4_CTL2

See Table 35-2.

IA32_MC4_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs. The IA32_MC2_MISC MSR is either not implemented or does not contain additional information if the MISCV flag in the IA32_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general- protection exception.

IA32_MC4_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

IA32_MC5_ADDR1

06_0FH

IA32_MC5_CTL

06_0FH

IA32_MC5_CTL2

See Table 35-2.

IA32_MC5_MISC

06_0FH

IA32_MC5_STATUS

06_0FH

IA32_MC6_ADDR1

06_1DH

IA32_MC6_CTL

06_1DH

IA32_MC6_CTL2

See Table 35-2.

IA32_MC6_MISC

Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4

IA32_MC6_STATUS

06_1DH

IA32_MC7_ADDR1

06_1AH

IA32_MC7_CTL

06_1AH

IA32_MC7_CTL2

See Table 35-2.

IA32_MC7_MISC

06_1AH

IA32_MC7_STATUS

06_1AH

IA32_MC8_ADDR1

06_1AH

IA32_MC8_CTL

06_1AH

IA32_MC8_CTL2

See Table 35-2.

IA32_MC8_MISC

06_1AH

IA32_MC8_STATUS

06_1AH

IA32_MC9_ADDR1

06_2EH

IA32_MC9_CTL

06_2EH

IA32_MC9_CTL2

See Table 35-2.

IA32_MC9_MISC

06_2EH

IA32_MC9_STATUS

06_2EH

IA32_MCG_CAP

Machine Check Capabilities (R) See Table 35-2. See Section 15.3.1.1, IA32_MCG_CAP MSR.

IA32_MCG_CTL

Machine Check Feature Enable (R/W) See Table 35-2. See Section 15.3.1.3, IA32_MCG_CTL MSR.

IA32_MCG_STATUS

Machine Check Status. (R) See Table 35-2. See Section 15.3.1.2, IA32_MCG_STATUS MSR.

IA32_MISC_ENABLE
IA32_MONITOR_FILTER_LINE_SIZE

See Section 8.10.5, Monitor/Mwait Address Range Determination.

IA32_MONITOR_FILTER_SIZE

See Section 8.10.5, Monitor/Mwait Address Range Determination, and see Table 35-2.

IA32_MPERF

Maximum Performance Frequency Clock Count (RW) See Table 35-2.

IA32_MTRRCAP

MTRR Information See Section 11.11.1, MTRR Feature Identification. .

IA32_MTRR_DEF_TYPE

Default Memory Types (R/W) Sets the memory type for the regions of physical memory that are not mapped by the MTRRs. See Section 11.11.2.1, IA32_MTRR_DEF_TYPE MSR.

IA32_MTRR_FIX16K_80000

Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.

IA32_MTRR_FIX16K_A0000

Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.

IA32_MTRR_FIX4K_C0000

Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.

IA32_MTRR_FIX4K_C8000

Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs .

IA32_MTRR_FIX4K_D0000

Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs .

IA32_MTRR_FIX4K_D8000

Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.

IA32_MTRR_FIX4K_E0000

Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.

IA32_MTRR_FIX4K_E8000

Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.

IA32_MTRR_FIX4K_F0000

Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.

IA32_MTRR_FIX4K_F8000

Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.

IA32_MTRR_FIX64K_00000

Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.

IA32_MTRR_PHYSBASE0

Variable Range Base MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSBASE1

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSBASE2

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSBASE3

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSBASE4

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSBASE5

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSBASE6

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSBASE7

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSBASE8

if IA32_MTRR_CAP[7:0] > 8

IA32_MTRR_PHYSBASE9

if IA32_MTRR_CAP[7:0] > 9

IA32_MTRR_PHYSMASK0

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSMASK1

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSMASK2

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs .

IA32_MTRR_PHYSMASK3

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSMASK4

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSMASK5

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSMASK6

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSMASK7

Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.

IA32_MTRR_PHYSMASK8

if IA32_MTRR_CAP[7:0] > 8

IA32_MTRR_PHYSMASK9

if IA32_MTRR_CAP[7:0] > 9

IA32_P5_MC_ADDR

See Section 35.16, MSRs in Pentium Processors.

IA32_P5_MC_TYPE

See Section 35.16, MSRs in Pentium Processors.

IA32_PACKAGE_THERM_INTERRUPT

If CPUID.06H: EAX[6] = 1

IA32_PACKAGE_THERM_STATUS

If CPUID.06H: EAX[6] = 1

IA32_PAT

Page Attribute Table See Section 11.11.2.2, Fixed Range MTRRs.

IA32_PEBS_ENABLE
IA32_PERFEVTSEL0

Performance Event Select for Counter 0 (R/W) Supports all fields described inTable 35-2 and the fields below.

IA32_PERFEVTSEL1

Performance Event Select for Counter 1 (R/W) Supports all fields described inTable 35-2 and the fields below.

IA32_PERFEVTSEL2

Performance Event Select for Counter 2 (R/W) Supports all fields described inTable 35-2 and the fields below.

IA32_PERFEVTSEL3

Performance Event Select for Counter 3 (R/W) Supports all fields described inTable 35-2 and the fields below.

IA32_PERFEVTSEL4

See Table 35-2; If CPUID.0AH:EAX[15:8] = 8

IA32_PERFEVTSEL5

See Table 35-2; If CPUID.0AH:EAX[15:8] = 8

IA32_PERFEVTSEL6

See Table 35-2; If CPUID.0AH:EAX[15:8] = 8

IA32_PERFEVTSEL7

See Table 35-2; If CPUID.0AH:EAX[15:8] = 8

IA32_PERF_CAPABILITIES

See Table 35-2. See Section 17.4.1, IA32_DEBUGCTL MSR.

IA32_PERF_CTL

See Table 35-2. See Section 14.1, Enhanced Intel Speedstep® Technology.

IA32_PERF_GLOBAL_CTRL

See Table 35-2. See Section 18.4.2, Global Counter Control Facilities.

IA32_PERF_GLOBAL_OVF_CTRL

See Table 35-2. See Section 18.4.2, Global Counter Control Facilities.

IA32_PERF_GLOBAL_STAUS

See Table 35-2. See Section 18.4.2, Global Counter Control Facilities.

IA32_PERF_STATUS

See Table 35-2. See Section 14.1, Enhanced Intel Speedstep® Technology.

IA32_PLATFORM_DCA_CAP

06_0FH

IA32_PLATFORM_ID

Platform ID (R) See Table 35-2. The operating system can use this MSR to determine slot information for the processor and the proper microcode update to load.

IA32_PMC0

Performance Counter Register See Table 35-2.

IA32_PMC1

Performance Counter Register See Table 35-2.

IA32_PMC2

Performance Counter Register See Table 35-2.

IA32_PMC3

Performance Counter Register See Table 35-2.

IA32_PMC4

Performance Counter Register See Table 35-2.

IA32_PMC5

Performance Counter Register See Table 35-2.

IA32_PMC6

Performance Counter Register See Table 35-2.

IA32_PMC7

Performance Counter Register See Table 35-2.

IA32_PQR_ASSOC

If ( CPUID.(EAX=07H, ECX=0):EBX.[bit 12] = 1 )

IA32_QM_CTR

If ( CPUID.(EAX=07H, ECX=0):EBX.[bit 12] = 1 )

IA32_QM_EVTSEL

If ( CPUID.(EAX=07H, ECX=0):EBX.[bit 12] = 1 )

IA32_SMBASE

If IA32_VMX_MISC[bit 15])

IA32_SMM_MONITOR_CTL

SMM Monitor Configuration (R/W) See Table 35-2.

IA32_SMRR_PHYSBASE

See Table 35-2.

IA32_SMRR_PHYSMASK

If IA32_MTRR_CAP[SMRR] = 1

IA32_STAR

System Call Target Address (R/W) See Table 35-2.

IA32_SYSENTER_CS

CS register target for CPL 0 code (R/W) See Table 35-2. See Section 5.8.7, Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.

IA32_SYSENTER_EIP

CPL 0 code entry point (R/W) See Table 35-2. See Section 5.8.7, Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.

IA32_SYSENTER_ESP

Stack pointer for CPL 0 stack (R/W) See Table 35-2. See Section 5.8.7, Performing Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.

IA32_THERM_INTERRUPT

Thermal Interrupt Control (R/W) See Section 14.5.2, Thermal Monitor, and see Table 35-2.

IA32_THERM_STATUS

Thermal Monitor Status (R/W) See Section 14.5.2, Thermal Monitor, and see Table 35-2.

IA32_TIME_STAMP_COUNTER

See Section 17.13, Time-Stamp Counter, and see Table 35-2.

IA32_TSC_ADJUST

Per-Logical-Processor TSC ADJUST (R/W) See Table 35-2.

IA32_TSC_AUX

AUXILIARY TSC Signature. (R/W) See Table 35-2 and Section 17.13.2, IA32_TSC_AUX Register and RDTSCP Support.

IA32_TSC_DEADLINE

TSC Target of Local APIC s TSC Deadline Mode (R/W) See Table 35-2

IA32_VMX_BASIC

Reporting Register of Basic VMX Capabilities (R/O) See Table 35-2. See Appendix A.1, Basic VMX Information (If CPUID.01H:ECX.[bit 9])

IA32_VMX_CR0_FIXED0

Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7, VMX-Fixed Bits in CR0 (If CPUID.01H:ECX.[bit 9])

IA32_VMX_CR0_FIXED1

Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7, VMX-Fixed Bits in CR0 (If CPUID.01H:ECX.[bit 9])

IA32_VMX_CR4_FIXED0

Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8, VMX-Fixed Bits in CR4 (If CPUID.01H:ECX.[bit 9])

IA32_VMX_CR4_FIXED1

Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8, VMX-Fixed Bits in CR4 (If CPUID.01H:ECX.[bit 9])

IA32_VMX_CRO_FIXED0

If CPUID.01H:ECX.[bit 5] = 1

IA32_VMX_CRO_FIXED1

If CPUID.01H:ECX.[bit 5] = 1

IA32_VMX_ENTRY_CTLS

Capability Reporting Register of VM-entry Controls (R/O) See Appendix A.5, VM-Entry Controls (If CPUID.01H:ECX.[bit 9])

IA32_VMX_EPT_VPID_CAP

If ( CPUID.01H:ECX.[bit 5], IA32_VMX_PROCBASED_C TLS[bit 63], and either IA32_VMX_PROCBASED_C TLS2[bit 33] or IA32_VMX_PROCBASED_C TLS2[bit 37])

IA32_VMX_EPT_VPID_ENUM

Capability Reporting Register of EPT and VPID (R/O) See Table 35-2

IA32_VMX_EXIT_CTLS

Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4, VM-Exit Controls (If CPUID.01H:ECX.[bit 9])

IA32_VMX_FMFUNC

Capability Reporting Register of VM-function Controls (R/O) See Table 35-2

IA32_VMX_MISC

Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6, Miscellaneous Data (If CPUID.01H:ECX.[bit 9])

IA32_VMX_PINBASED_CTLS

Capability Reporting Register of Pin-based VM-execution Controls (R/O) See Appendix A.3, VM-Execution Controls (If CPUID.01H:ECX.[bit 9])

IA32_VMX_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-based VM-execution Controls (R/O) See Appendix A.3, VM-Execution Controls (If CPUID.01H:ECX.[bit 9])

IA32_VMX_PROCBASED_CTLS2

Capability Reporting Register of Secondary Processor-based VM-execution Controls (R/O) See Appendix A.3, VM-Execution Controls (If CPUID.01H:ECX.[bit 9] and IA32_VMX_PROCBASED_CTLS[bit 63])

IA32_VMX_TRUE_ENTRY_CTLS

Capability Reporting Register of VM-entry Flex Controls (R/O) See Table 35-2

IA32_VMX_TRUE_EXIT_CTLS

Capability Reporting Register of VM-exit Flex Controls (R/O) See Table 35-2

IA32_VMX_TRUE_PINBASED_CTLS

Capability Reporting Register of Pin-based VM-execution Flex Controls (R/O) See Table 35-2

IA32_VMX_TRUE_PROCBASED_CTLS

Capability Reporting Register of Primary Processor-based VM-execution Flex Controls (R/O) See Table 35-2

IA32_VMX_VMCS_ENUM

Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix A.9, VMCS Enumeration (If CPUID.01H:ECX.[bit 9])

IA32_VMX_VMFUNC

If( CPUID.01H:ECX.[bit 5] = 1 and IA32_VMX_BASIC[bit 55] )

IA32_X2APIC_APICID

x2APIC ID register (R/O) See x2APIC Specification.

IA32_X2APIC_CUR_COUNT

x2APIC Current Count register (R/O)

IA32_X2APIC_DIV_CONF

x2APIC Divide Configuration register (R/W)

IA32_X2APIC_EOI

If ( CPUID.01H:ECX.[bit 21] = 1 )

IA32_X2APIC_ESR

If ( CPUID.01H:ECX.[bit 21] = 1 )

IA32_X2APIC_ICR

x2APIC Interrupt Command register (R/W)

IA32_X2APIC_INIT_COUNT

x2APIC Initial Count register (R/W)

IA32_X2APIC_IRR0

x2APIC Interrupt Request register bits 31:0

IA32_X2APIC_IRR1

x2APIC Interrupt Request register bits 63:32

IA32_X2APIC_IRR2

x2APIC Interrupt Request register bits 95:64

IA32_X2APIC_IRR3

x2APIC Interrupt Request register bits 127:96

IA32_X2APIC_IRR4

x2APIC Interrupt Request register bits 159:128

IA32_X2APIC_IRR5

x2APIC Interrupt Request register bits 191:160

IA32_X2APIC_IRR6

x2APIC Interrupt Request register bits 223:192

IA32_X2APIC_IRR7

x2APIC Interrupt Request register bits 255:224

IA32_X2APIC_ISR0

x2APIC In-Service register bits 31:0

IA32_X2APIC_ISR1

x2APIC In-Service register bits 63:32

IA32_X2APIC_ISR2

x2APIC In-Service register bits 95:64

IA32_X2APIC_ISR3

x2APIC In-Service register bits 127:96

IA32_X2APIC_ISR4

x2APIC In-Service register bits 159:128

IA32_X2APIC_ISR5

x2APIC In-Service register bits 191:160

IA32_X2APIC_ISR6

x2APIC In-Service register bits 223:192

IA32_X2APIC_ISR7

x2APIC In-Service register bits 255:224

IA32_X2APIC_LDR

x2APIC Logical Destination register (R/O)

IA32_X2APIC_LVT_CMCI

x2APIC LVT Corrected Machine Check Interrupt register (R/W)

IA32_X2APIC_LVT_ERROR

If ( CPUID.01H:ECX.[bit 21] = 1 )

IA32_X2APIC_LVT_LINT0

If ( CPUID.01H:ECX.[bit 21] = 1 )

IA32_X2APIC_LVT_LINT1

If ( CPUID.01H:ECX.[bit 21] = 1 )

IA32_X2APIC_LVT_PMI

x2APIC LVT Performance Monitor register (R/W)

IA32_X2APIC_LVT_THERMAL

x2APIC LVT Thermal Sensor Interrupt register (R/W)

IA32_X2APIC_LVT_TIMER

x2APIC LVT Timer Interrupt register (R/W)

IA32_X2APIC_PPR

x2APIC Processor Priority register (R/O)

IA32_X2APIC_SELF_IPI

If ( CPUID.01H:ECX.[bit 21] = 1 )

IA32_X2APIC_SIVR

x2APIC Spurious Interrupt Vector register (R/W)

IA32_X2APIC_TMR0

x2APIC Trigger Mode register bits 31:0

IA32_X2APIC_TMR1

x2APIC Trigger Mode register bits 63:32

IA32_X2APIC_TMR2

x2APIC Trigger Mode register bits 95:64

IA32_X2APIC_TMR3

x2APIC Trigger Mode register bits 127:96

IA32_X2APIC_TMR4

x2APIC Trigger Mode register bits 159:128

IA32_X2APIC_TMR5

x2APIC Trigger Mode register bits 191:160

IA32_X2APIC_TMR6

x2APIC Trigger Mode register bits 223:192

IA32_X2APIC_TMR7

x2APIC Trigger Mode register bits 255:224

IA32_X2APIC_TPR

x2APIC Task Priority register (R/W)

IA32_X2APIC_VERSION

If ( CPUID.01H:ECX.[bit 21] = 1 )

LASTBRANCHFROMIP
LASTBRANCHTOIP
LASTINTFROMIP
LASTINTTOIP
MC0_ADDR
MC0_CTL
MC0_MISC

Defined in MCA architecture but not implemented in the P6 family processors.

MC0_STATUS
MC1_ADDR
MC1_CTL
MC1_MISC

Defined in MCA architecture but not implemented in the P6 family processors.

MC1_STATUS

Bit definitions same as MC0_STATUS.

MC2_ADDR
MC2_CTL
MC2_MISC

Defined in MCA architecture but not implemented in the P6 family processors.

MC2_STATUS

Bit definitions same as MC0_STATUS.

MC3_ADDR
MC3_CTL
MC3_MISC

Defined in MCA architecture but not implemented in the P6 family processors.

MC3_STATUS

Bit definitions same as MC0_STATUS.

MC4_ADDR

Defined in MCA architecture but not implemented in P6 Family processors.

MC4_CTL
MC4_MISC

Defined in MCA architecture but not implemented in the P6 family processors.

MC4_STATUS

Bit definitions same as MC0_STATUS, except bits 0, 4, 57, and 61 are hardcoded to 1.

MCG_CAP
MCG_CTL
MCG_STATUS
MSR_ALF_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_ALF_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_B0_PMON_BOX_CTRL

Uncore B-box 0 perfmon local box control MSR.

MSR_B0_PMON_BOX_OVF_CTRL

Uncore B-box 0 perfmon local box overflow control MSR.

MSR_B0_PMON_BOX_STATUS

Uncore B-box 0 perfmon local box status MSR.

MSR_B0_PMON_CTR0

Uncore B-box 0 perfmon counter MSR.

MSR_B0_PMON_CTR1

Uncore B-box 0 perfmon counter MSR.

MSR_B0_PMON_CTR2

Uncore B-box 0 perfmon counter MSR.

MSR_B0_PMON_CTR3

Uncore B-box 0 perfmon counter MSR.

MSR_B0_PMON_EVNT_SEL0

Uncore B-box 0 perfmon event select MSR.

MSR_B0_PMON_EVNT_SEL1

Uncore B-box 0 perfmon event select MSR.

MSR_B0_PMON_EVNT_SEL2

Uncore B-box 0 perfmon event select MSR.

MSR_B0_PMON_EVNT_SEL3

Uncore B-box 0 perfmon event select MSR.

MSR_B0_PMON_MASK

Uncore B-box 0 perfmon local box mask MSR.

MSR_B0_PMON_MATCH

Uncore B-box 0 perfmon local box match MSR.

MSR_B1_PMON_BOX_CTRL

Uncore B-box 1 perfmon local box control MSR.

MSR_B1_PMON_BOX_OVF_CTRL

Uncore B-box 1 perfmon local box overflow control MSR.

MSR_B1_PMON_BOX_STATUS

Uncore B-box 1 perfmon local box status MSR.

MSR_B1_PMON_CTR0

Uncore B-box 1 perfmon counter MSR.

MSR_B1_PMON_CTR1

Uncore B-box 1 perfmon counter MSR.

MSR_B1_PMON_CTR2

Uncore B-box 1 perfmon counter MSR.

MSR_B1_PMON_CTR3

Uncore B-box 1 perfmon counter MSR.

MSR_B1_PMON_EVNT_SEL0

Uncore B-box 1 perfmon event select MSR.

MSR_B1_PMON_EVNT_SEL1

Uncore B-box 1 perfmon event select MSR.

MSR_B1_PMON_EVNT_SEL2

Uncore B-box 1 perfmon event select MSR.

MSR_B1_PMON_EVNT_SEL3

Uncore B-box 1vperfmon event select MSR.

MSR_B1_PMON_MASK

Uncore B-box 1 perfmon local box mask MSR.

MSR_B1_PMON_MATCH

Uncore B-box 1 perfmon local box match MSR.

MSR_BBL_CR_CTL
MSR_BBL_CR_CTL3
MSR_BPU_CCCR0

See Section 18.12.3, CCCR MSRs.

MSR_BPU_CCCR1

See Section 18.12.3, CCCR MSRs.

MSR_BPU_CCCR2

See Section 18.12.3, CCCR MSRs.

MSR_BPU_CCCR3

See Section 18.12.3, CCCR MSRs.

MSR_BPU_COUNTER0

See Section 18.12.2, Performance Counters.

MSR_BPU_COUNTER1

See Section 18.12.2, Performance Counters.

MSR_BPU_COUNTER2

See Section 18.12.2, Performance Counters.

MSR_BPU_COUNTER3

See Section 18.12.2, Performance Counters.

MSR_BPU_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_BPU_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_BSU_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_BSU_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_C0_PMON_BOX_CTRL

Uncore C-box 0 perfmon local box control MSR.

MSR_C0_PMON_BOX_OVF_CTRL

Uncore C-box 0 perfmon local box overflow control MSR.

MSR_C0_PMON_BOX_STATUS

Uncore C-box 0 perfmon local box status MSR.

MSR_C0_PMON_CTR0

Uncore C-box 0 perfmon counter MSR.

MSR_C0_PMON_CTR1

Uncore C-box 0 perfmon counter MSR.

MSR_C0_PMON_CTR2

Uncore C-box 0 perfmon counter MSR.

MSR_C0_PMON_CTR3

Uncore C-box 0 perfmon counter MSR.

MSR_C0_PMON_CTR4

Uncore C-box 0 perfmon counter MSR.

MSR_C0_PMON_CTR5

Uncore C-box 0 perfmon counter MSR.

MSR_C0_PMON_EVNT_SEL0

Uncore C-box 0 perfmon event select MSR.

MSR_C0_PMON_EVNT_SEL1

Uncore C-box 0 perfmon event select MSR.

MSR_C0_PMON_EVNT_SEL2

Uncore C-box 0 perfmon event select MSR.

MSR_C0_PMON_EVNT_SEL3

Uncore C-box 0 perfmon event select MSR.

MSR_C0_PMON_EVNT_SEL4

Uncore C-box 0 perfmon event select MSR.

MSR_C0_PMON_EVNT_SEL5

Uncore C-box 0 perfmon event select MSR.

MSR_C1_PMON_BOX_CTRL

Uncore C-box 1 perfmon local box control MSR.

MSR_C1_PMON_BOX_OVF_CTRL

Uncore C-box 1 perfmon local box overflow control MSR.

MSR_C1_PMON_BOX_STATUS

Uncore C-box 1 perfmon local box status MSR.

MSR_C1_PMON_CTR0

Uncore C-box 1 perfmon counter MSR.

MSR_C1_PMON_CTR1

Uncore C-box 1 perfmon counter MSR.

MSR_C1_PMON_CTR2

Uncore C-box 1 perfmon counter MSR.

MSR_C1_PMON_CTR3

Uncore C-box 1 perfmon counter MSR.

MSR_C1_PMON_CTR4

Uncore C-box 1 perfmon counter MSR.

MSR_C1_PMON_CTR5

Uncore C-box 1 perfmon counter MSR.

MSR_C1_PMON_EVNT_SEL0

Uncore C-box 1 perfmon event select MSR.

MSR_C1_PMON_EVNT_SEL1

Uncore C-box 1 perfmon event select MSR.

MSR_C1_PMON_EVNT_SEL2

Uncore C-box 1 perfmon event select MSR.

MSR_C1_PMON_EVNT_SEL3

Uncore C-box 1 perfmon event select MSR.

MSR_C1_PMON_EVNT_SEL4

Uncore C-box 1 perfmon event select MSR.

MSR_C1_PMON_EVNT_SEL5

Uncore C-box 1 perfmon event select MSR.

MSR_C2_PMON_BOX_CTRL

Uncore C-box 2 perfmon local box control MSR.

MSR_C2_PMON_BOX_OVF_CTRL

Uncore C-box 2 perfmon local box overflow control MSR.

MSR_C2_PMON_BOX_STATUS

Uncore C-box 2 perfmon local box status MSR.

MSR_C2_PMON_CTR0

Uncore C-box 2 perfmon counter MSR.

MSR_C2_PMON_CTR1

Uncore C-box 2 perfmon counter MSR.

MSR_C2_PMON_CTR2

Uncore C-box 2 perfmon counter MSR.

MSR_C2_PMON_CTR3

Uncore C-box 2 perfmon counter MSR.

MSR_C2_PMON_CTR4

Uncore C-box 2 perfmon counter MSR.

MSR_C2_PMON_CTR5

Uncore C-box 2 perfmon counter MSR.

MSR_C2_PMON_EVNT_SEL0

Uncore C-box 2 perfmon event select MSR.

MSR_C2_PMON_EVNT_SEL1

Uncore C-box 2 perfmon event select MSR.

MSR_C2_PMON_EVNT_SEL2

Uncore C-box 2 perfmon event select MSR.

MSR_C2_PMON_EVNT_SEL3

Uncore C-box 2 perfmon event select MSR.

MSR_C2_PMON_EVNT_SEL4

Uncore C-box 2 perfmon event select MSR.

MSR_C2_PMON_EVNT_SEL5

Uncore C-box 2 perfmon event select MSR.

MSR_C3_PMON_BOX_CTRL

Uncore C-box 3 perfmon local box control MSR.

MSR_C3_PMON_BOX_OVF_CTRL

Uncore C-box 3 perfmon local box overflow control MSR.

MSR_C3_PMON_BOX_STATUS

Uncore C-box 3 perfmon local box status MSR.

MSR_C3_PMON_CTR0

Uncore C-box 3 perfmon counter MSR.

MSR_C3_PMON_CTR1

Uncore C-box 3 perfmon counter MSR.

MSR_C3_PMON_CTR2

Uncore C-box 3 perfmon counter MSR.

MSR_C3_PMON_CTR3

Uncore C-box 3 perfmon counter MSR.

MSR_C3_PMON_CTR4

Uncore C-box 3 perfmon counter MSR.

MSR_C3_PMON_CTR5

Uncore C-box 3 perfmon counter MSR.

MSR_C3_PMON_EVNT_SEL0

Uncore C-box 3 perfmon event select MSR.

MSR_C3_PMON_EVNT_SEL1

Uncore C-box 3 perfmon event select MSR.

MSR_C3_PMON_EVNT_SEL2

Uncore C-box 3 perfmon event select MSR.

MSR_C3_PMON_EVNT_SEL3

Uncore C-box 3 perfmon event select MSR.

MSR_C3_PMON_EVNT_SEL4

Uncore C-box 3 perfmon event select MSR.

MSR_C3_PMON_EVNT_SEL5

Uncore C-box 3 perfmon event select MSR.

MSR_C4_PMON_BOX_CTRL

Uncore C-box 4 perfmon local box control MSR.

MSR_C4_PMON_BOX_OVF_CTRL

Uncore C-box 4 perfmon local box overflow control MSR.

MSR_C4_PMON_BOX_STATUS

Uncore C-box 4 perfmon local box status MSR.

MSR_C4_PMON_CTR0

Uncore C-box 4 perfmon counter MSR.

MSR_C4_PMON_CTR1

Uncore C-box 4 perfmon counter MSR.

MSR_C4_PMON_CTR2

Uncore C-box 4 perfmon counter MSR.

MSR_C4_PMON_CTR3

Uncore C-box 4 perfmon counter MSR.

MSR_C4_PMON_CTR4

Uncore C-box 4 perfmon counter MSR.

MSR_C4_PMON_CTR5

Uncore C-box 4 perfmon counter MSR.

MSR_C4_PMON_EVNT_SEL0

Uncore C-box 4 perfmon event select MSR.

MSR_C4_PMON_EVNT_SEL1

Uncore C-box 4 perfmon event select MSR.

MSR_C4_PMON_EVNT_SEL2

Uncore C-box 4 perfmon event select MSR.

MSR_C4_PMON_EVNT_SEL3

Uncore C-box 4 perfmon event select MSR.

MSR_C4_PMON_EVNT_SEL4

Uncore C-box 4 perfmon event select MSR.

MSR_C4_PMON_EVNT_SEL5

Uncore C-box 4 perfmon event select MSR.

MSR_C5_PMON_BOX_CTRL

Uncore C-box 5 perfmon local box control MSR.

MSR_C5_PMON_BOX_OVF_CTRL

Uncore C-box 5 perfmon local box overflow control MSR.

MSR_C5_PMON_BOX_STATUS

Uncore C-box 5 perfmon local box status MSR.

MSR_C5_PMON_CTR0

Uncore C-box 5 perfmon counter MSR.

MSR_C5_PMON_CTR1

Uncore C-box 5 perfmon counter MSR.

MSR_C5_PMON_CTR2

Uncore C-box 5 perfmon counter MSR.

MSR_C5_PMON_CTR3

Uncore C-box 5 perfmon counter MSR.

MSR_C5_PMON_CTR4

Uncore C-box 5 perfmon counter MSR.

MSR_C5_PMON_CTR5

Uncore C-box 5 perfmon counter MSR.

MSR_C5_PMON_EVNT_SEL0

Uncore C-box 5 perfmon event select MSR.

MSR_C5_PMON_EVNT_SEL1

Uncore C-box 5 perfmon event select MSR.

MSR_C5_PMON_EVNT_SEL2

Uncore C-box 5 perfmon event select MSR.

MSR_C5_PMON_EVNT_SEL3

Uncore C-box 5 perfmon event select MSR.

MSR_C5_PMON_EVNT_SEL4

Uncore C-box 5 perfmon event select MSR.

MSR_C5_PMON_EVNT_SEL5

Uncore C-box 5 perfmon event select MSR.

MSR_C6_PMON_BOX_CTRL

Uncore C-box 6 perfmon local box control MSR.

MSR_C6_PMON_BOX_OVF_CTRL

Uncore C-box 6 perfmon local box overflow control MSR.

MSR_C6_PMON_BOX_STATUS

Uncore C-box 6 perfmon local box status MSR.

MSR_C6_PMON_CTR0

Uncore C-box 6 perfmon counter MSR.

MSR_C6_PMON_CTR1

Uncore C-box 6 perfmon counter MSR.

MSR_C6_PMON_CTR2

Uncore C-box 6 perfmon counter MSR.

MSR_C6_PMON_CTR3

Uncore C-box 6 perfmon counter MSR.

MSR_C6_PMON_CTR4

Uncore C-box 6 perfmon counter MSR.

MSR_C6_PMON_CTR5

Uncore C-box 6 perfmon counter MSR.

MSR_C6_PMON_EVNT_SEL0

Uncore C-box 6 perfmon event select MSR.

MSR_C6_PMON_EVNT_SEL1

Uncore C-box 6 perfmon event select MSR.

MSR_C6_PMON_EVNT_SEL2

Uncore C-box 6 perfmon event select MSR.

MSR_C6_PMON_EVNT_SEL3

Uncore C-box 6 perfmon event select MSR.

MSR_C6_PMON_EVNT_SEL4

Uncore C-box 6 perfmon event select MSR.

MSR_C6_PMON_EVNT_SEL5

Uncore C-box 6 perfmon event select MSR.

MSR_C7_PMON_BOX_CTRL

Uncore C-box 7 perfmon local box control MSR.

MSR_C7_PMON_BOX_OVF_CTRL

Uncore C-box 7 perfmon local box overflow control MSR.

MSR_C7_PMON_BOX_STATUS

Uncore C-box 7 perfmon local box status MSR.

MSR_C7_PMON_CTR0

Uncore C-box 7 perfmon counter MSR.

MSR_C7_PMON_CTR1

Uncore C-box 7 perfmon counter MSR.

MSR_C7_PMON_CTR2

Uncore C-box 7 perfmon counter MSR.

MSR_C7_PMON_CTR3

Uncore C-box 7 perfmon counter MSR.

MSR_C7_PMON_CTR4

Uncore C-box 7 perfmon counter MSR.

MSR_C7_PMON_CTR5

Uncore C-box 7 perfmon counter MSR.

MSR_C7_PMON_EVNT_SEL0

Uncore C-box 7 perfmon event select MSR.

MSR_C7_PMON_EVNT_SEL1

Uncore C-box 7 perfmon event select MSR.

MSR_C7_PMON_EVNT_SEL2

Uncore C-box 7 perfmon event select MSR.

MSR_C7_PMON_EVNT_SEL3

Uncore C-box 7 perfmon event select MSR.

MSR_C7_PMON_EVNT_SEL4

Uncore C-box 7 perfmon event select MSR.

MSR_C7_PMON_EVNT_SEL5

Uncore C-box 7 perfmon event select MSR.

MSR_C8_PMON_BOX_CTRL

Uncore C-box 8 perfmon local box control MSR.

MSR_C8_PMON_BOX_OVF_CTRL

Uncore C-box 8 perfmon local box overflow control MSR.

MSR_C8_PMON_BOX_STATUS

Uncore C-box 8 perfmon local box status MSR.

MSR_C8_PMON_CTR0

Uncore C-box 8 perfmon counter MSR.

MSR_C8_PMON_CTR1

Uncore C-box 8 perfmon counter MSR.

MSR_C8_PMON_CTR2

Uncore C-box 8 perfmon counter MSR.

MSR_C8_PMON_CTR3

Uncore C-box 8 perfmon counter MSR.

MSR_C8_PMON_CTR4

Uncore C-box 8 perfmon counter MSR.

MSR_C8_PMON_CTR5

Uncore C-box 8 perfmon counter MSR.

MSR_C8_PMON_EVNT_SEL0

Uncore C-box 8 perfmon event select MSR.

MSR_C8_PMON_EVNT_SEL1

Uncore C-box 8 perfmon event select MSR.

MSR_C8_PMON_EVNT_SEL2

Uncore C-box 8 perfmon event select MSR.

MSR_C8_PMON_EVNT_SEL3

Uncore C-box 8 perfmon event select MSR.

MSR_C8_PMON_EVNT_SEL4

Uncore C-box 8 perfmon event select MSR.

MSR_C8_PMON_EVNT_SEL5

Uncore C-box 8 perfmon event select MSR.

MSR_C9_PMON_BOX_CTRL

Uncore C-box 9 perfmon local box control MSR.

MSR_C9_PMON_BOX_OVF_CTRL

Uncore C-box 9 perfmon local box overflow control MSR.

MSR_C9_PMON_BOX_STATUS

Uncore C-box 9 perfmon local box status MSR.

MSR_C9_PMON_CTR0

Uncore C-box 9 perfmon counter MSR.

MSR_C9_PMON_CTR1

Uncore C-box 9 perfmon counter MSR.

MSR_C9_PMON_CTR2

Uncore C-box 9 perfmon counter MSR.

MSR_C9_PMON_CTR3

Uncore C-box 9 perfmon counter MSR.

MSR_C9_PMON_CTR4

Uncore C-box 9 perfmon counter MSR.

MSR_C9_PMON_CTR5

Uncore C-box 9 perfmon counter MSR.

MSR_C9_PMON_EVNT_SEL0

Uncore C-box 9 perfmon event select MSR.

MSR_C9_PMON_EVNT_SEL1

Uncore C-box 9 perfmon event select MSR.

MSR_C9_PMON_EVNT_SEL2

Uncore C-box 9 perfmon event select MSR.

MSR_C9_PMON_EVNT_SEL3

Uncore C-box 9 perfmon event select MSR.

MSR_C9_PMON_EVNT_SEL4

Uncore C-box 9 perfmon event select MSR.

MSR_C9_PMON_EVNT_SEL5

Uncore C-box 9 perfmon event select MSR.

MSR_CONFIG_TDP_CONTROL

ConfigTDP Control (R/W)

MSR_CONFIG_TDP_LEVEL1

ConfigTDP Level 1 ratio and power level (R/O)

MSR_CONFIG_TDP_LEVEL2

ConfigTDP Level 2 ratio and power level (R/O)

MSR_CONFIG_TDP_NOMINAL

Nominal TDP Ratio (R/O)

MSR_CORE_C1_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.

MSR_CORE_C3_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.

MSR_CORE_C4_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.

MSR_CORE_C6_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.

MSR_CORE_C7_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.

MSR_CRU_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_CRU_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_CRU_ESCR2

See Section 18.12.1, ESCR MSRs.

MSR_CRU_ESCR3

See Section 18.12.1, ESCR MSRs.

MSR_CRU_ESCR4

See Section 18.12.1, ESCR MSRs.

MSR_CRU_ESCR5

See Section 18.12.1, ESCR MSRs.

MSR_DAC_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_DAC_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_DEBUGCTLA

Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section. See Section 17.9.1, MSR_DEBUGCTLA MSR.

MSR_DEBUGCTLB

Debug Control (R/W) Controls how several debug features are used. Bit definitions are discussed in the referenced section. See Section 17.11, Last Branch, Interrupt, and Exception Recording (Pentium M Processors).

MSR_DRAM_ENERGY_STATUS

DRAM Energy Status (R/O) See Section 14.7.5, DRAM RAPL Domain.

MSR_DRAM_PERF_STATUS

DRAM Performance Throttling Status (R/O) See Section 14.7.5, DRAM RAPL Domain.

MSR_DRAM_POWER_INFO

DRAM RAPL Parameters (R/W) See Section 14.7.5, DRAM RAPL Domain.

MSR_DRAM_POWER_LIMIT

DRAM RAPL Power Limit Control (R/W) See Section 14.7.5, DRAM RAPL Domain.

MSR_EBC_FREQUENCY_ID

Processor Frequency Configuration The bit field layout of this MSR varies according to the MODEL value in the CPUID version information. The following bit field layout applies to Pentium 4 and Xeon Processors with MODEL encoding equal or greater than 2. (R) The field Indicates the current processor frequency configuration.

MSR_EBC_HARD_POWERON

Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.

MSR_EBC_SOFT_POWERON

Processor Soft Power-On Configuration (R/W) Enables and disables processor features.

MSR_EBL_CR_POWERON

Processor Hard Power-On Configuration (R/W) Enables and disables processor features; (R) indicates current processor configuration.

MSR_EFSB_DRDY0

EFSB DRDY Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache for details.

MSR_EFSB_DRDY1

EFSB DRDY Event Control and Counter Register (R/W)

MSR_EMON_L3_CTR_CTL0

GBUSQ Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.

MSR_EMON_L3_CTR_CTL1

GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2

MSR_EMON_L3_CTR_CTL2

GSNPQ Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.

MSR_EMON_L3_CTR_CTL3

GSNPQ Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2

MSR_EMON_L3_CTR_CTL4

FSB Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache for details.

MSR_EMON_L3_CTR_CTL5

FSB Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2

MSR_EMON_L3_CTR_CTL6

FSB Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2

MSR_EMON_L3_CTR_CTL7

FSB Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2

MSR_EMON_L3_GL_CTL

L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 17.2.2

MSR_ERROR_CONTROL

MC Bank Error Configuration (R/W)

MSR_FIRM_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_FIRM_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_FLAME_CCCR0

See Section 18.12.3, CCCR MSRs.

MSR_FLAME_CCCR1

See Section 18.12.3, CCCR MSRs.

MSR_FLAME_CCCR2

See Section 18.12.3, CCCR MSRs.

MSR_FLAME_CCCR3

See Section 18.12.3, CCCR MSRs.

MSR_FLAME_COUNTER0

See Section 18.12.2, Performance Counters.

MSR_FLAME_COUNTER1

See Section 18.12.2, Performance Counters.

MSR_FLAME_COUNTER2

See Section 18.12.2, Performance Counters.

MSR_FLAME_COUNTER3

See Section 18.12.2, Performance Counters.

MSR_FLAME_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_FLAME_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_FSB_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_FSB_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_FSB_FREQ

Scaleable Bus Speed(RO) This field indicates the intended scaleable bus clock speed for processors based on Intel Atom microarchitecture:

MSR_GQ_SNOOP_MESF
MSR_IFSB_BUSQ0

IFSB BUSQ Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.

MSR_IFSB_BUSQ1

IFSB BUSQ Event Control and Counter Register (R/W)

MSR_IFSB_CNTR7

IFSB Latency Event Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.

MSR_IFSB_CTL6

IFSB Latency Event Control Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache for details.

MSR_IFSB_SNPQ0

IFSB SNPQ Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.

MSR_IFSB_SNPQ1

IFSB SNPQ Event Control and Counter Register (R/W)

MSR_IQ_CCCR0

See Section 18.12.3, CCCR MSRs.

MSR_IQ_CCCR1

See Section 18.12.3, CCCR MSRs.

MSR_IQ_CCCR2

See Section 18.12.3, CCCR MSRs.

MSR_IQ_CCCR3

See Section 18.12.3, CCCR MSRs.

MSR_IQ_CCCR4

See Section 18.12.3, CCCR MSRs.

MSR_IQ_CCCR5

See Section 18.12.3, CCCR MSRs.

MSR_IQ_COUNTER4

See Section 18.12.2, Performance Counters.

MSR_IQ_COUNTER5

See Section 18.12.2, Performance Counters.

MSR_IQ_ESCR0

See Section 18.12.1, ESCR MSRs. This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-02H.

MSR_IQ_ESCR1

See Section 18.12.1, ESCR MSRs. This MSR is not available on later processors. It is only available on processor family 0FH, models 01H-02H.

MSR_IS_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_IS_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_ITLB_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_ITLB_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_IX_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_LASTBRANCH_0

Last Branch Record 0 (R/W) One of four last branch record registers on the last branch record stack. It contains pointers to the source and destination instruction for one of the last four branches, exceptions, or interrupts that the processor took. MSR_LASTBRANCH_0 through MSR_LASTBRANCH_3 at 1DBH-1DEH are available only on family 0FH, models 0H-02H. They have been replaced by the MSRs at 680H- 68FH and 6C0H-6CFH.

MSR_LASTBRANCH_0_FROM_IP

Last Branch Record 0 From IP (R/W) One of eight pairs of last branch record registers on the last branch record stack. This part of the stack contains pointers to the source instruction for one of the last eight branches, exceptions, or interrupts taken by the processor. See also: Last Branch Record Stack TOS at 1C9H Section 17.11, Last Branch, Interrupt, and Exception Recording (Pentium M Processors).

MSR_LASTBRANCH_0_TO_IP

Last Branch Record 0 (R/W) One of 16 pairs of last branch record registers on the last branch record stack (6C0H-6CFH). This part of the stack contains pointers to the destination instruction for one of the last 16 branches, exceptions, or interrupts that the processor took. See Section 17.9, Last Branch, Interrupt, and Exception Recording (Processors based on Intel NetBurst® Microarchitecture).

MSR_LASTBRANCH_1

Last Branch Record 1 (R/W) See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_10_FROM_IP

Last Branch Record 10 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_10_TO_IP

Last Branch Record 10 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_11_FROM_IP

Last Branch Record 11 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_11_TO_IP

Last Branch Record 11 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_12_FROM_IP

Last Branch Record 12 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_12_TO_IP

Last Branch Record 12 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_13_FROM_IP

Last Branch Record 13 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_13_TO_IP

Last Branch Record 13 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_14_FROM_IP

Last Branch Record 14 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_14_TO_IP

Last Branch Record 14 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_15_FROM_IP

Last Branch Record 15 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_15_TO_IP

Last Branch Record 15 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_1_FROM_IP

Last Branch Record 1 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_1_TO_IP

Last Branch Record 1 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_2

Last Branch Record 2 See description of the MSR_LASTBRANCH_0 MSR at 1DBH.

MSR_LASTBRANCH_2_FROM_IP

Last Branch Record 2 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_2_TO_IP

Last Branch Record 2 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_3

Last Branch Record 3 See description of the MSR_LASTBRANCH_0 MSR at 1DBH.

MSR_LASTBRANCH_3_FROM_IP

Last Branch Record 3 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_3_TO_IP

Last Branch Record 3 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_4

Last Branch Record 4 (R/W) See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_4_FROM_IP

Last Branch Record 4 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_4_TO_IP

Last Branch Record 4 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_5

Last Branch Record 5 (R/W) See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_5_FROM_IP

Last Branch Record 5 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_5_TO_IP

Last Branch Record 5 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_6

Last Branch Record 6 (R/W) See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_6_FROM_IP

Last Branch Record 6 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_6_TO_IP

Last Branch Record 6 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_7

Last Branch Record 7 (R/W) See description of MSR_LASTBRANCH_0.

MSR_LASTBRANCH_7_FROM_IP

Last Branch Record 7 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_7_TO_IP

Last Branch Record 7 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_8_FROM_IP

Last Branch Record 8 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_8_TO_IP

Last Branch Record 8 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_9_FROM_IP

Last Branch Record 9 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.

MSR_LASTBRANCH_9_TO_IP

Last Branch Record 9 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.

MSR_LASTBRANCH_TOS

Last Branch Record Stack TOS (R/W) Contains an index (0-3 or 0-15) that points to the top of the last branch record stack (that is, that points the index of the MSR containing the most recent branch record). See Section 17.9.2, LBR Stack for Processors Based on Intel NetBurst® Microarchitecture ; and addresses 1DBH-1DEH and 680H-68FH.

MSR_LBR_SELECT

Last Branch Record Filtering Select Register (R/W) See Section 17.6.2, Filtering of Last Branch Records.

MSR_LER_FROM_LIP

Last Exception Record From Linear IP (R) Contains a pointer to the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.11, Last Branch, Interrupt, and Exception Recording (Pentium M Processors) and Section 17.12.2, Last Branch and Last Exception MSRs.

MSR_LER_TO_LIP

Last Exception Record To Linear IP (R) This area contains a pointer to the target of the last branch instruction that the processor executed prior to the last exception that was generated or the last interrupt that was handled. See Section 17.11, Last Branch, Interrupt, and Exception Recording (Pentium M Processors) and Section 17.12.2, Last Branch and Last Exception MSRs.

MSR_M0_PMON_ADDR_MASK

Uncore M-box 0 perfmon local box address mask MSR.

MSR_M0_PMON_ADDR_MATCH

Uncore M-box 0 perfmon local box address match MSR.

MSR_M0_PMON_BOX_CTRL

Uncore M-box 0 perfmon local box control MSR.

MSR_M0_PMON_BOX_OVF_CTRL

Uncore M-box 0 perfmon local box overflow control MSR.

MSR_M0_PMON_BOX_STATUS

Uncore M-box 0 perfmon local box status MSR.

MSR_M0_PMON_CTR0

Uncore M-box 0 perfmon counter MSR.

MSR_M0_PMON_CTR1

Uncore M-box 0 perfmon counter MSR.

MSR_M0_PMON_CTR2

Uncore M-box 0 perfmon counter MSR.

MSR_M0_PMON_CTR3

Uncore M-box 0 perfmon counter MSR.

MSR_M0_PMON_CTR4

Uncore M-box 0 perfmon counter MSR.

MSR_M0_PMON_CTR5

Uncore M-box 0 perfmon counter MSR.

MSR_M0_PMON_DSP

Uncore M-box 0 perfmon DSP unit select MSR.

MSR_M0_PMON_EVNT_SEL0

Uncore M-box 0 perfmon event select MSR.

MSR_M0_PMON_EVNT_SEL1

Uncore M-box 0 perfmon event select MSR.

MSR_M0_PMON_EVNT_SEL2

Uncore M-box 0 perfmon event select MSR.

MSR_M0_PMON_EVNT_SEL3

Uncore M-box 0 perfmon event select MSR.

MSR_M0_PMON_EVNT_SEL4

Uncore M-box 0 perfmon event select MSR.

MSR_M0_PMON_EVNT_SEL5

Uncore M-box 0 perfmon event select MSR.

MSR_M0_PMON_ISS

Uncore M-box 0 perfmon ISS unit select MSR.

MSR_M0_PMON_MAP

Uncore M-box 0 perfmon MAP unit select MSR.

MSR_M0_PMON_MM_CONFIG

Uncore M-box 0 perfmon local box address match/mask config MSR.

MSR_M0_PMON_MSC_THR

Uncore M-box 0 perfmon MIC THR select MSR.

MSR_M0_PMON_PGT

Uncore M-box 0 perfmon PGT unit select MSR.

MSR_M0_PMON_PLD

Uncore M-box 0 perfmon PLD unit select MSR.

MSR_M0_PMON_TIMESTAMP

Uncore M-box 0 perfmon time stamp unit select MSR.

MSR_M0_PMON_ZDP

Uncore M-box 0 perfmon ZDP unit select MSR.

MSR_M1_PMON_ADDR_MASK

Uncore M-box 1 perfmon local box address mask MSR.

MSR_M1_PMON_ADDR_MATCH

Uncore M-box 1 perfmon local box address match MSR.

MSR_M1_PMON_BOX_CTRL

Uncore M-box 1 perfmon local box control MSR.

MSR_M1_PMON_BOX_OVF_CTRL

Uncore M-box 1 perfmon local box overflow control MSR.

MSR_M1_PMON_BOX_STATUS

Uncore M-box 1 perfmon local box status MSR.

MSR_M1_PMON_CTR0

Uncore M-box 1 perfmon counter MSR.

MSR_M1_PMON_CTR1

Uncore M-box 1 perfmon counter MSR.

MSR_M1_PMON_CTR2

Uncore M-box 1 perfmon counter MSR.

MSR_M1_PMON_CTR3

Uncore M-box 1 perfmon counter MSR.

MSR_M1_PMON_CTR4

Uncore M-box 1 perfmon counter MSR.

MSR_M1_PMON_CTR5

Uncore M-box 1 perfmon counter MSR.

MSR_M1_PMON_DSP

Uncore M-box 1 perfmon DSP unit select MSR.

MSR_M1_PMON_EVNT_SEL0

Uncore M-box 1 perfmon event select MSR.

MSR_M1_PMON_EVNT_SEL1

Uncore M-box 1 perfmon event select MSR.

MSR_M1_PMON_EVNT_SEL2

Uncore M-box 1 perfmon event select MSR.

MSR_M1_PMON_EVNT_SEL3

Uncore M-box 1 perfmon event select MSR.

MSR_M1_PMON_EVNT_SEL4

Uncore M-box 1 perfmon event select MSR.

MSR_M1_PMON_EVNT_SEL5

Uncore M-box 1 perfmon event select MSR.

MSR_M1_PMON_ISS

Uncore M-box 1 perfmon ISS unit select MSR.

MSR_M1_PMON_MAP

Uncore M-box 1 perfmon MAP unit select MSR.

MSR_M1_PMON_MM_CONFIG

Uncore M-box 1 perfmon local box address match/mask config MSR.

MSR_M1_PMON_MSC_THR

Uncore M-box 1 perfmon MIC THR select MSR.

MSR_M1_PMON_PGT

Uncore M-box 1 perfmon PGT unit select MSR.

MSR_M1_PMON_PLD

Uncore M-box 1 perfmon PLD unit select MSR.

MSR_M1_PMON_TIMESTAMP

Uncore M-box 1 perfmon time stamp unit select MSR.

MSR_M1_PMON_ZDP

Uncore M-box 1 perfmon ZDP unit select MSR.

MSR_MC0_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC10_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC10_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC10_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC10_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC11_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC11_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC11_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC11_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC12_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC12_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC12_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC12_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC13_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC13_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC13_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC13_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC14_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC14_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC14_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC14_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC15_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC15_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC15_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC15_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC16_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC16_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC16_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC16_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC17_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC17_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC17_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC17_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC18_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC18_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC18_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC18_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC19_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC19_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC19_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC19_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC1_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC20_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC20_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC20_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC20_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC21_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC21_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC21_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC21_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC22_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC22_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC22_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC22_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC23_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC23_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC23_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC23_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC24_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC24_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC24_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC24_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC25_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC25_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC25_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC25_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC26_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC26_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC26_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC26_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC2_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC3_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The MSR_MC3_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

MSR_MC3_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC3_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC3_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS.

MSR_MC4_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

MSR_MC4_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC4_CTL2

Always 0 (CMCI not supported).

MSR_MC4_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC4_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS.

MSR_MC5_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The MSR_MC4_ADDR register is either not implemented or contains no address if the ADDRV flag in the MSR_MC4_STATUS register is clear. When not implemented in the processor, all reads and writes to this MSR will cause a general-protection exception.

MSR_MC5_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC5_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC5_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC6_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC6_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC6_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC6_STATUS

Apply to Intel Xeon processor 7400 series (processor signature 06_1D) only. See Section 15.3.2.2, IA32_MCi_STATUS MSRS. and Chapter 23.

MSR_MC7_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC7_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC7_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC7_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC8_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC8_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC8_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC8_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MC9_ADDR

See Section 15.3.2.3, IA32_MCi_ADDR MSRs.

MSR_MC9_CTL

See Section 15.3.2.1, IA32_MCi_CTL MSRs.

MSR_MC9_MISC

See Section 15.3.2.4, IA32_MCi_MISC MSRs.

MSR_MC9_STATUS

See Section 15.3.2.2, IA32_MCi_STATUS MSRS, and Chapter 16.

MSR_MCG_MISC

Machine Check Miscellaneous See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_R10

Machine Check R10 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_R11

Machine Check R11 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_R12

Machine Check R12 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_R13

Machine Check R13 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_R14

Machine Check R14 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_R8

Machine Check R8 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_R9

Machine Check R9D/R9 See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_RAX

Machine Check EAX/RAX Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_RBP

Machine Check EBP/RBP Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_RBX

Machine Check EBX/RBX Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_RCX

Machine Check ECX/RCX Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_RDI

Machine Check EDI/RDI Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_RDX

Machine Check EDX/RDX Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_RFLAGS

Machine Check EFLAGS/RFLAG Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_RIP

Machine Check EIP/RIP Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MCG_RSI

Machine Check ESI/RSI Save State See Section 15.3.2.6, IA32_MCG Extended Machine Check State MSRs.

MSR_MISC_PWR_MGMT

See http://biosbits.org.

MSR_MOB_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_MOB_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_MS_CCCR0

See Section 18.12.3, CCCR MSRs.

MSR_MS_CCCR1

See Section 18.12.3, CCCR MSRs.

MSR_MS_CCCR2

See Section 18.12.3, CCCR MSRs.

MSR_MS_CCCR3

See Section 18.12.3, CCCR MSRs.

MSR_MS_COUNTER0

See Section 18.12.2, Performance Counters.

MSR_MS_COUNTER1

See Section 18.12.2, Performance Counters.

MSR_MS_COUNTER2

See Section 18.12.2, Performance Counters.

MSR_MS_COUNTER3

See Section 18.12.2, Performance Counters.

MSR_MS_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_MS_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_OFFCORE_RSP_0

Offcore Response Event Select Register (R/W)

MSR_OFFCORE_RSP_1

Offcore Response Event Select Register (R/W)

MSR_PEBS_ENABLE

Precise Event-Based Sampling (PEBS) (R/W) Controls the enabling of precise event sampling and replay tagging.

MSR_PEBS_LD_LAT

see See Section 18.7.1.2, Load Latency Performance Monitoring Facility.

MSR_PEBS_MATRIX_VERT

See Table 19-26.

MSR_PEBS_NUM_ALT
MSR_PERF_CAPABILITIES

RO. This applies to processors that do not support architectural perfmon version 2.

MSR_PERF_FIXED_CTR0

Fixed-Function Performance Counter Register 0 (R/W)

MSR_PERF_FIXED_CTR1

Fixed-Function Performance Counter Register 1 (R/W)

MSR_PERF_FIXED_CTR2

Fixed-Function Performance Counter Register 2 (R/W)

MSR_PERF_FIXED_CTR_CTRL

Fixed-Function-Counter Control Register (R/W)

MSR_PERF_GLOBAL_CTRL

See Section 18.4.2, Global Counter Control Facilities.

MSR_PERF_GLOBAL_OVF_CTRL

See Section 18.4.2, Global Counter Control Facilities.

MSR_PERF_GLOBAL_STAUS

See Section 18.4.2, Global Counter Control Facilities.

MSR_PERF_STATUS
MSR_PKGC3_IRTL

Package C3 Interrupt Response Limit (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.

MSR_PKGC6_IRTL

Package C6 Interrupt Response Limit (R/W) This MSR defines the budget allocated for the package to exit from C6 to a C0 state, where interrupt request can be delivered to the core and serviced. Additional core-exit latency amy be applicable depending on the actual C-state the core is in. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.

MSR_PKGC7_IRTL

Package C7 Interrupt Response Limit (R/W) This MSR defines the budget allocated for the package to exit from C7 to a C0 state, where interrupt request can be delivered to the core and serviced. Additional core-exit latency amy be applicable depending on the actual C-state the core is in. Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States.

MSR_PKG_C10_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States.

MSR_PKG_C2_RESIDENCY

Package C2 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States

MSR_PKG_C3_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.

MSR_PKG_C4_RESIDENCY

Package C4 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States

MSR_PKG_C6C_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.

MSR_PKG_C6_RESIDENCY

Package C6 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States

MSR_PKG_C7_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States.

MSR_PKG_C9_RESIDENCY

Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States.

MSR_PKG_CST_CONFIG_CONTROL

C-State Configuration Control (R/W) Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C- States. See http://biosbits.org.

MSR_PKG_ENERGY_STATUS

PKG Energy Status (R/O) See Section 14.7.3, Package RAPL Domain.

MSR_PKG_PERF_STATUS

Package RAPL Perf Status (R/O)

MSR_PKG_POWER_INFO

PKG RAPL Parameters (R/W) See Section 14.7.3, Package RAPL Domain.

MSR_PKG_POWER_LIMIT

PKG RAPL Power Limit Control (R/W) See Section 14.7.3, Package RAPL Domain.

MSR_PLATFORM_BRV

Platform Feature Requirements (R)

MSR_PLATFORM_ID

Model Specific Platform ID (R)

MSR_PLATFORM_INFO

see http://biosbits.org.

MSR_PMG_IO_CAPTURE_BASE

Power Management IO Redirection in C-state (R/W) See http://biosbits.org.

MSR_PMH_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_PMH_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_POWER_CTL

Power Control Register. See http://biosbits.org.

MSR_PP0_ENERGY_STATUS

PP0 Energy Status (R/O) See Section 14.7.4, PP0/PP1 RAPL Domains.

MSR_PP0_PERF_STATUS

PP0 Performance Throttling Status (R/O) See Section 14.7.4, PP0/PP1 RAPL Domains.

MSR_PP0_POLICY

PP0 Balance Policy (R/W) See Section 14.7.4, PP0/PP1 RAPL Domains.

MSR_PP0_POWER_LIMIT

PP0 RAPL Power Limit Control (R/W) See Section 14.7.4, PP0/PP1 RAPL Domains.

MSR_PP1_ENERGY_STATUS

PP1 Energy Status (R/O) See Section 14.7.4, PP0/PP1 RAPL Domains.

MSR_PP1_POLICY

PP1 Balance Policy (R/W) See Section 14.7.4, PP0/PP1 RAPL Domains.

MSR_PP1_POWER_LIMIT

PP1 RAPL Power Limit Control (R/W) See Section 14.7.4, PP0/PP1 RAPL Domains.

MSR_R0_PMON_BOX_CTRL

Uncore R-box 0 perfmon local box control MSR.

MSR_R0_PMON_BOX_OVF_CTRL

Uncore R-box 0 perfmon local box overflow control MSR.

MSR_R0_PMON_BOX_STATUS

Uncore R-box 0 perfmon local box status MSR.

MSR_R0_PMON_CTR0

Uncore R-box 0 perfmon counter MSR.

MSR_R0_PMON_CTR1

Uncore R-box 0 perfmon counter MSR.

MSR_R0_PMON_CTR2

Uncore R-box 0 perfmon counter MSR.

MSR_R0_PMON_CTR3

Uncore R-box 0 perfmon counter MSR.

MSR_R0_PMON_CTR4

Uncore R-box 0 perfmon counter MSR.

MSR_R0_PMON_CTR5

Uncore R-box 0 perfmon counter MSR.

MSR_R0_PMON_CTR6

Uncore R-box 0 perfmon counter MSR.

MSR_R0_PMON_CTR7

Uncore R-box 0 perfmon counter MSR.

MSR_R0_PMON_EVNT_SEL0

Uncore R-box 0 perfmon event select MSR.

MSR_R0_PMON_EVNT_SEL1

Uncore R-box 0 perfmon event select MSR.

MSR_R0_PMON_EVNT_SEL2

Uncore R-box 0 perfmon event select MSR.

MSR_R0_PMON_EVNT_SEL3

Uncore R-box 0 perfmon event select MSR.

MSR_R0_PMON_EVNT_SEL4

Uncore R-box 0 perfmon event select MSR.

MSR_R0_PMON_EVNT_SEL5

Uncore R-box 0 perfmon event select MSR.

MSR_R0_PMON_EVNT_SEL6

Uncore R-box 0 perfmon event select MSR.

MSR_R0_PMON_EVNT_SEL7

Uncore R-box 0 perfmon event select MSR.

MSR_R0_PMON_IPERF0_P0

Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.

MSR_R0_PMON_IPERF0_P1

Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.

MSR_R0_PMON_IPERF0_P2

Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.

MSR_R0_PMON_IPERF0_P3

Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.

MSR_R0_PMON_IPERF0_P4

Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.

MSR_R0_PMON_IPERF0_P5

Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.

MSR_R0_PMON_IPERF0_P6

Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.

MSR_R0_PMON_IPERF0_P7

Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.

MSR_R0_PMON_QLX_P0

Uncore R-box 0 perfmon QLX unit Port 0 select MSR.

MSR_R0_PMON_QLX_P1

Uncore R-box 0 perfmon QLX unit Port 1 select MSR.

MSR_R0_PMON_QLX_P2

Uncore R-box 0 perfmon QLX unit Port 2 select MSR.

MSR_R0_PMON_QLX_P3

Uncore R-box 0 perfmon QLX unit Port 3 select MSR.

MSR_R1_PMON_BOX_CTRL

Uncore R-box 1 perfmon local box control MSR.

MSR_R1_PMON_BOX_OVF_CTRL

Uncore R-box 1 perfmon local box overflow control MSR.

MSR_R1_PMON_BOX_STATUS

Uncore R-box 1 perfmon local box status MSR.

MSR_R1_PMON_CTR10

Uncore R-box 1 perfmon counter MSR.

MSR_R1_PMON_CTR11

Uncore R-box 1 perfmon counter MSR.

MSR_R1_PMON_CTR12

Uncore R-box 1 perfmon counter MSR.

MSR_R1_PMON_CTR13

Uncore R-box 1perfmon counter MSR.

MSR_R1_PMON_CTR14

Uncore R-box 1 perfmon counter MSR.

MSR_R1_PMON_CTR15

Uncore R-box 1 perfmon counter MSR.

MSR_R1_PMON_CTR8

Uncore R-box 1 perfmon counter MSR.

MSR_R1_PMON_CTR9

Uncore R-box 1 perfmon counter MSR.

MSR_R1_PMON_EVNT_SEL10

Uncore R-box 1 perfmon event select MSR.

MSR_R1_PMON_EVNT_SEL11

Uncore R-box 1 perfmon event select MSR.

MSR_R1_PMON_EVNT_SEL12

Uncore R-box 1 perfmon event select MSR.

MSR_R1_PMON_EVNT_SEL13

Uncore R-box 1 perfmon event select MSR.

MSR_R1_PMON_EVNT_SEL14

Uncore R-box 1 perfmon event select MSR.

MSR_R1_PMON_EVNT_SEL15

Uncore R-box 1 perfmon event select MSR.

MSR_R1_PMON_EVNT_SEL8

Uncore R-box 1 perfmon event select MSR.

MSR_R1_PMON_EVNT_SEL9

Uncore R-box 1 perfmon event select MSR.

MSR_R1_PMON_IPERF1_P10

Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.

MSR_R1_PMON_IPERF1_P11

Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.

MSR_R1_PMON_IPERF1_P12

Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.

MSR_R1_PMON_IPERF1_P13

Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.

MSR_R1_PMON_IPERF1_P14

Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.

MSR_R1_PMON_IPERF1_P15

Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.

MSR_R1_PMON_IPERF1_P8

Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.

MSR_R1_PMON_IPERF1_P9

Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.

MSR_R1_PMON_QLX_P4

Uncore R-box 1 perfmon QLX unit Port 4 select MSR.

MSR_R1_PMON_QLX_P5

Uncore R-box 1 perfmon QLX unit Port 5 select MSR.

MSR_R1_PMON_QLX_P6

Uncore R-box 1 perfmon QLX unit Port 6 select MSR.

MSR_R1_PMON_QLX_P7

Uncore R-box 1 perfmon QLX unit Port 7 select MSR.

MSR_RAPL_POWER_UNIT

Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.7.1, RAPL Interfaces.

MSR_RAT_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_RAT_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_S0_PMON_BOX_CTRL

Uncore S-box 0 perfmon local box control MSR.

MSR_S0_PMON_BOX_OVF_CTRL

Uncore S-box 0 perfmon local box overflow control MSR.

MSR_S0_PMON_BOX_STATUS

Uncore S-box 0 perfmon local box status MSR.

MSR_S0_PMON_CTR0

Uncore S-box 0 perfmon counter MSR.

MSR_S0_PMON_CTR1

Uncore S-box 0 perfmon counter MSR.

MSR_S0_PMON_CTR2

Uncore S-box 0 perfmon counter MSR.

MSR_S0_PMON_CTR3

Uncore S-box 0 perfmon counter MSR.

MSR_S0_PMON_EVNT_SEL0

Uncore S-box 0 perfmon event select MSR.

MSR_S0_PMON_EVNT_SEL1

Uncore S-box 0 perfmon event select MSR.

MSR_S0_PMON_EVNT_SEL2

Uncore S-box 0 perfmon event select MSR.

MSR_S0_PMON_EVNT_SEL3

Uncore S-box 0 perfmon event select MSR.

MSR_S0_PMON_MASK

Uncore S-box 0 perfmon local box mask MSR.

MSR_S0_PMON_MATCH

Uncore S-box 0 perfmon local box match MSR.

MSR_S1_PMON_BOX_CTRL

Uncore S-box 1 perfmon local box control MSR.

MSR_S1_PMON_BOX_OVF_CTRL

Uncore S-box 1 perfmon local box overflow control MSR.

MSR_S1_PMON_BOX_STATUS

Uncore S-box 1 perfmon local box status MSR.

MSR_S1_PMON_CTR0

Uncore S-box 1 perfmon counter MSR.

MSR_S1_PMON_CTR1

Uncore S-box 1 perfmon counter MSR.

MSR_S1_PMON_CTR2

Uncore S-box 1 perfmon counter MSR.

MSR_S1_PMON_CTR3

Uncore S-box 1 perfmon counter MSR.

MSR_S1_PMON_EVNT_SEL0

Uncore S-box 1 perfmon event select MSR.

MSR_S1_PMON_EVNT_SEL1

Uncore S-box 1 perfmon event select MSR.

MSR_S1_PMON_EVNT_SEL2

Uncore S-box 1 perfmon event select MSR.

MSR_S1_PMON_EVNT_SEL3

Uncore S-box 1 perfmon event select MSR.

MSR_S1_PMON_MASK

Uncore S-box 1 perfmon local box mask MSR.

MSR_S1_PMON_MATCH

Uncore S-box 1 perfmon local box match MSR.

MSR_SAAT_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_SAAT_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_SMI_COUNT

SMI Counter (R/O)

MSR_SMM_BLOCKED

SMM Blocked (SMM-RO) Reports the blocked state of all logical processors in the package . Available only while in SMM.

MSR_SMM_DELAYED

SMM Delayed (SMM-RO) Reports the interruptible state of all logical processors in the package . Available only while in SMM and MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.

MSR_SMM_FEATURE_CONTROL

Enhanced SMM Feature Control (SMM-RW) Reports SMM capability Enhancement. Accessible only while in SMM.

MSR_SMM_MCA_CAP

Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in SMM.

MSR_SMRR_PHYSMASK

System Management Mode Physical Address Mask register (WO in SMM) Model-specific implementation of SMRR-like interface, read visible and write only in SMM..

MSR_SSU_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_TBPU_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_TBPU_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_TC_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_TC_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_TEMPERATURE_TARGET
MSR_THERM2_CTL

Thermal Monitor 2 Control.

MSR_TURBO_ACTIVATION_RATIO

ConfigTDP Control (R/W)

MSR_TURBO_POWER_CURRENT_LIMIT

See http://biosbits.org.

MSR_TURBO_RATIO_LIMIT

Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1

MSR_U2L_ESCR0

See Section 18.12.1, ESCR MSRs.

MSR_U2L_ESCR1

See Section 18.12.1, ESCR MSRs.

MSR_UNCORE_ADDR_OPCODE_MATCH

See Section 18.7.2.3, Uncore Address/Opcode Match MSR.

MSR_UNCORE_FIXED_CTR0

See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.

MSR_UNCORE_FIXED_CTR_CTRL

See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.

MSR_UNCORE_PERFEVTSEL0

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PERFEVTSEL1

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PERFEVTSEL2

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PERFEVTSEL3

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PERFEVTSEL4

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PERFEVTSEL5

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PERFEVTSEL6

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PERFEVTSEL7

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PERF_GLOBAL_CTRL

See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.

MSR_UNCORE_PERF_GLOBAL_OVF_CTRL

See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.

MSR_UNCORE_PERF_GLOBAL_STATUS

See Section 18.7.2.1, Uncore Performance Monitoring Management Facility.

MSR_UNCORE_PMC0

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PMC1

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PMC2

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PMC3

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PMC4

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PMC5

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PMC6

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNCORE_PMC7

See Section 18.7.2.2, Uncore Performance Event Configuration Facility.

MSR_UNC_ARB_PERFEVTSEL0

Uncore Arb unit, counter 0 event select MSR

MSR_UNC_ARB_PERFEVTSEL1

Uncore Arb unit, counter 1 event select MSR

MSR_UNC_ARB_PER_CTR0

Uncore Arb unit, performance counter 0

MSR_UNC_ARB_PER_CTR1

Uncore Arb unit, performance counter 1

MSR_UNC_CBO_0_PERFEVTSEL0

Uncore C-Box 0, counter 0 event select MSR

MSR_UNC_CBO_0_PERFEVTSEL1

Uncore C-Box 0, counter 1 event select MSR

MSR_UNC_CBO_0_PER_CTR0

Uncore C-Box 0, performance counter 0

MSR_UNC_CBO_0_PER_CTR1

Uncore C-Box 0, performance counter 1

MSR_UNC_CBO_1_PERFEVTSEL0

Uncore C-Box 1, counter 0 event select MSR

MSR_UNC_CBO_1_PERFEVTSEL1

Uncore C-Box 1, counter 1 event select MSR

MSR_UNC_CBO_1_PER_CTR0

Uncore C-Box 1, performance counter 0

MSR_UNC_CBO_1_PER_CTR1

Uncore C-Box 1, performance counter 1

MSR_UNC_CBO_2_PERFEVTSEL0

Uncore C-Box 2, counter 0 event select MSR

MSR_UNC_CBO_2_PERFEVTSEL1

Uncore C-Box 2, counter 1 event select MSR

MSR_UNC_CBO_2_PER_CTR0

Uncore C-Box 2, performance counter 0

MSR_UNC_CBO_2_PER_CTR1

Uncore C-Box 2, performance counter 1

MSR_UNC_CBO_3_PERFEVTSEL0

Uncore C-Box 3, counter 0 event select MSR

MSR_UNC_CBO_3_PERFEVTSEL1

Uncore C-Box 3, counter 1 event select MSR.

MSR_UNC_CBO_3_PER_CTR0

Uncore C-Box 3, performance counter 0.

MSR_UNC_CBO_3_PER_CTR1

Uncore C-Box 3, performance counter 1.

MSR_UNC_CBO_CONFIG

Uncore C-Box configuration information (R/O)

MSR_UNC_PERF_FIXED_CTR

Uncore fixed counter

MSR_UNC_PERF_FIXED_CTRL

Uncore fixed counter control (R/W)

MSR_UNC_PERF_GLOBAL_CTRL

Uncore PMU global control

MSR_UNC_PERF_GLOBAL_STATUS

Uncore PMU main status

MSR_U_PMON_CTR

Uncore U-box perfmon counter MSR.

MSR_U_PMON_EVNT_SEL

Uncore U-box perfmon event select MSR.

MSR_U_PMON_GLOBAL_CTRL

Uncore U-box perfmon global control MSR.

MSR_U_PMON_GLOBAL_OVF_CTRL

Uncore U-box perfmon global overflow control MSR.

MSR_U_PMON_GLOBAL_STATUS

Uncore U-box perfmon global status MSR.

MSR_W_PMON_BOX_CTRL

Uncore W-box perfmon local box control MSR.

MSR_W_PMON_BOX_OVF_CTRL

Uncore W-box perfmon local box overflow control MSR.

MSR_W_PMON_BOX_STATUS

Uncore W-box perfmon local box status MSR.

MSR_W_PMON_CTR0

Uncore W-box perfmon counter MSR.

MSR_W_PMON_CTR1

Uncore W-box perfmon counter MSR.

MSR_W_PMON_CTR2

Uncore W-box perfmon counter MSR.

MSR_W_PMON_CTR3

Uncore W-box perfmon counter MSR.

MSR_W_PMON_EVNT_SEL0

Uncore W-box perfmon event select MSR.

MSR_W_PMON_EVNT_SEL1

Uncore W-box perfmon event select MSR.

MSR_W_PMON_EVNT_SEL2

Uncore W-box perfmon event select MSR.

MSR_W_PMON_EVNT_SEL3

Uncore W-box perfmon event select MSR.

MSR_W_PMON_FIXED_CTR

Uncore W-box perfmon fixed counter

MSR_W_PMON_FIXED_CTR_CTL

Uncore U-box perfmon fixed counter control MSR

P5_MC_ADDR

See Section 35.16, MSRs in Pentium Processors, and see Table 35-2.

P5_MC_TYPE

See Section 35.16, MSRs in Pentium Processors, and see Table 35-2.

ROB_CR_BKUPTMPDR6
SYSENTER_CS_MSR

CS register target for CPL 0 code

SYSENTER_EIP_MSR

CPL 0 code entry point

SYSENTER_ESP_MSR

Stack pointer for CPL 0 stack

TEST_CTL

Test Control Register

TSC

See Section 17.13, Time-Stamp Counter.

Functions

rdmsr

Read 64 bits msr register.

wrmsr

Write 64 bits to msr register.