var searchIndex = {};
searchIndex["x86"] = {"doc":"","items":[[0,"io","x86","I/O port functionality.",null,null],[5,"outb","x86::io","Write 8 bits to port",null,{"inputs":[{"name":"u16"},{"name":"u8"}],"output":null}],[5,"inb","","Read 8 bits from port",null,{"inputs":[{"name":"u16"}],"output":{"name":"u8"}}],[5,"outw","","Write 16 bits to port",null,{"inputs":[{"name":"u16"},{"name":"u16"}],"output":null}],[5,"inw","","Read 16 bits from port",null,{"inputs":[{"name":"u16"}],"output":{"name":"u16"}}],[5,"outl","","Write 32 bits to port",null,{"inputs":[{"name":"u16"},{"name":"u32"}],"output":null}],[5,"inl","","Read 32 bits from port",null,{"inputs":[{"name":"u16"}],"output":{"name":"u32"}}],[0,"controlregs","x86","Functions to read and write control registers.",null,null],[5,"cr0","x86::controlregs","",null,{"inputs":[],"output":{"name":"u64"}}],[5,"cr0_write","","Write cr0.",null,{"inputs":[{"name":"u64"}],"output":null}],[5,"cr2","","Contains page-fault linear address.",null,{"inputs":[],"output":{"name":"u64"}}],[5,"cr3","","Contains page-table root pointer.",null,{"inputs":[],"output":{"name":"u64"}}],[5,"cr3_write","","Switch page-table PML4 pointer.",null,{"inputs":[{"name":"u64"}],"output":null}],[5,"cr4","","Contains various flags to control operations in protected mode.",null,{"inputs":[],"output":{"name":"u64"}}],[5,"cr4_write","","Write cr4.",null,{"inputs":[{"name":"u64"}],"output":null}],[0,"msr","x86","MSR value list and function to read and write them.",null,null],[5,"wrmsr","x86::msr","Write 64 bits to msr register.",null,{"inputs":[{"name":"u32"},{"name":"u64"}],"output":null}],[5,"rdmsr","","Read 64 bits msr register.",null,{"inputs":[{"name":"u32"}],"output":{"name":"u64"}}],[17,"P5_MC_ADDR","","See Section 35.16, MSRs in Pentium Processors,  and see  Table 35-2.",null,null],[17,"IA32_P5_MC_ADDR","","See Section 35.16, MSRs in Pentium Processors.",null,null],[17,"P5_MC_TYPE","","See Section 35.16, MSRs in Pentium Processors,  and see  Table 35-2.",null,null],[17,"IA32_P5_MC_TYPE","","See Section 35.16, MSRs in Pentium Processors.",null,null],[17,"IA32_MONITOR_FILTER_SIZE","","See Section 8.10.5, Monitor/Mwait Address Range Determination,   and see Table 35-2.",null,null],[17,"IA32_MONITOR_FILTER_LINE_SIZE","","See Section 8.10.5, Monitor/Mwait Address  Range Determination.",null,null],[17,"IA32_TIME_STAMP_COUNTER","","See Section 17.13, Time-Stamp Counter,  and see Table 35-2.",null,null],[17,"TSC","","See Section 17.13, Time-Stamp Counter.",null,null],[17,"MSR_PLATFORM_ID","","Model Specific Platform ID (R)",null,null],[17,"IA32_PLATFORM_ID","","Platform ID (R)  See Table 35-2. The operating system can use this MSR to  determine slot  information for the processor and the proper microcode update to load.",null,null],[17,"APIC_BASE","","Section 10.4.4, Local APIC Status and Location.",null,null],[17,"IA32_APIC_BASE","","APIC Location and Status (R/W) See Table 35-2. See Section 10.4.4, Local APIC  Status and Location.",null,null],[17,"EBL_CR_POWERON","","Processor Hard Power-On Configuration  (R/W) Enables and disables processor features;  (R) indicates current processor configuration.",null,null],[17,"MSR_EBL_CR_POWERON","","Processor Hard Power-On Configuration (R/W) Enables and  disables processor features;  (R) indicates current processor configuration.",null,null],[17,"MSR_EBC_HARD_POWERON","","Processor Hard Power-On Configuration (R/W) Enables and disables processor features;  (R) indicates current processor configuration.",null,null],[17,"MSR_EBC_SOFT_POWERON","","Processor Soft Power-On Configuration (R/W)  Enables and disables processor features.",null,null],[17,"MSR_EBC_FREQUENCY_ID","","Processor Frequency Configuration The bit field layout of this MSR varies according to  the MODEL value in the CPUID version  information. The following bit field layout applies to Pentium 4 and Xeon Processors with MODEL  encoding equal or greater than 2.  (R) The field Indicates the current processor  frequency configuration.",null,null],[17,"TEST_CTL","","Test Control Register",null,null],[17,"MSR_SMI_COUNT","","SMI Counter (R/O)",null,null],[17,"IA32_FEATURE_CONTROL","","Control Features in IA-32 Processor (R/W) See Table 35-2 (If CPUID.01H:ECX.[bit 5])",null,null],[17,"IA32_TSC_ADJUST","","Per-Logical-Processor TSC ADJUST (R/W) See Table 35-2.",null,null],[17,"MSR_LASTBRANCH_0_FROM_IP","","Last Branch Record 0 From IP (R/W) One of eight pairs of last branch record registers on the last branch  record stack. This part of the stack contains pointers to the source  instruction for one of the last eight branches, exceptions, or  interrupts taken by the processor. See also: Last Branch Record Stack TOS at 1C9H Section 17.11, Last Branch, Interrupt, and Exception Recording  (Pentium M Processors).",null,null],[17,"MSR_LASTBRANCH_1","","Last Branch Record 1 (R/W) See description of MSR_LASTBRANCH_0.",null,null],[17,"MSR_LASTBRANCH_1_FROM_IP","","Last Branch Record 1 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_2_FROM_IP","","Last Branch Record 2 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_3_FROM_IP","","Last Branch Record 3 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_4","","Last Branch Record 4 (R/W) See description of MSR_LASTBRANCH_0.",null,null],[17,"MSR_LASTBRANCH_4_FROM_IP","","Last Branch Record 4 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_5","","Last Branch Record 5 (R/W) See description of MSR_LASTBRANCH_0.",null,null],[17,"MSR_LASTBRANCH_5_FROM_IP","","Last Branch Record 5 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_6","","Last Branch Record 6 (R/W) See description of MSR_LASTBRANCH_0.",null,null],[17,"MSR_LASTBRANCH_6_FROM_IP","","Last Branch Record 6 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_7","","Last Branch Record 7 (R/W) See description of MSR_LASTBRANCH_0.",null,null],[17,"MSR_LASTBRANCH_7_FROM_IP","","Last Branch Record 7 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_0_TO_IP","","Last Branch Record 0 (R/W)  One of 16 pairs of last branch record registers on  the last branch record stack (6C0H-6CFH). This  part of the stack contains pointers to the  destination instruction for one of the last 16  branches, exceptions, or interrupts that the  processor took. See Section 17.9, Last Branch, Interrupt, and  Exception Recording (Processors based on Intel  NetBurst® Microarchitecture).",null,null],[17,"MSR_LASTBRANCH_1_TO_IP","","Last Branch Record 1 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_2_TO_IP","","Last Branch Record 2 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_3_TO_IP","","Last Branch Record 3 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_4_TO_IP","","Last Branch Record 4 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_5_TO_IP","","Last Branch Record 5 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_6_TO_IP","","Last Branch Record 6 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_7_TO_IP","","Last Branch Record 7 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"IA32_BIOS_UPDT_TRIG","","BIOS Update Trigger Register (W)  See Table 35-2.",null,null],[17,"BIOS_UPDT_TRIG","","BIOS Update Trigger Register.",null,null],[17,"IA32_BIOS_SIGN_ID","","BIOS Update Signature ID (R/W) See Table 35-2.",null,null],[17,"IA32_SMM_MONITOR_CTL","","SMM Monitor Configuration (R/W) See Table 35-2.",null,null],[17,"IA32_SMBASE","","If IA32_VMX_MISC[bit 15])",null,null],[17,"MSR_SMRR_PHYSMASK","","System Management Mode Physical Address Mask register  (WO in SMM) Model-specific implementation of SMRR-like interface, read visible  and write only in SMM..",null,null],[17,"IA32_PMC0","","Performance Counter Register  See Table 35-2.",null,null],[17,"IA32_PMC1","","Performance Counter Register  See Table 35-2.",null,null],[17,"IA32_PMC2","","Performance Counter Register  See Table 35-2.",null,null],[17,"IA32_PMC3","","Performance Counter Register  See Table 35-2.",null,null],[17,"IA32_PMC4","","Performance Counter Register  See Table 35-2.",null,null],[17,"IA32_PMC5","","Performance Counter Register  See Table 35-2.",null,null],[17,"IA32_PMC6","","Performance Counter Register  See Table 35-2.",null,null],[17,"IA32_PMC7","","Performance Counter Register  See Table 35-2.",null,null],[17,"MSR_FSB_FREQ","","Scaleable Bus Speed(RO) This field indicates the intended scaleable bus clock speed for  processors based on Intel Atom microarchitecture:",null,null],[17,"MSR_PLATFORM_INFO","","see http://biosbits.org.",null,null],[17,"MSR_PKG_CST_CONFIG_CONTROL","","C-State Configuration Control (R/W)  Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C- States. See http://biosbits.org.",null,null],[17,"MSR_PMG_IO_CAPTURE_BASE","","Power Management IO Redirection in C-state (R/W)  See http://biosbits.org.",null,null],[17,"IA32_MPERF","","Maximum Performance Frequency Clock Count (RW)  See Table 35-2.",null,null],[17,"IA32_APERF","","Actual Performance Frequency Clock Count (RW)  See Table 35-2.",null,null],[17,"IA32_MTRRCAP","","MTRR Information See Section 11.11.1, MTRR Feature  Identification. .",null,null],[17,"MSR_BBL_CR_CTL","","",null,null],[17,"MSR_BBL_CR_CTL3","","",null,null],[17,"IA32_SYSENTER_CS","","CS register target for CPL 0 code (R/W) See Table 35-2. See Section 5.8.7, Performing Fast Calls to  System Procedures with the SYSENTER and  SYSEXIT Instructions.",null,null],[17,"SYSENTER_CS_MSR","","CS register target for CPL 0 code",null,null],[17,"IA32_SYSENTER_ESP","","Stack pointer for CPL 0 stack (R/W) See Table 35-2. See Section 5.8.7, Performing Fast Calls to  System Procedures with the SYSENTER and  SYSEXIT Instructions.",null,null],[17,"SYSENTER_ESP_MSR","","Stack pointer for CPL 0 stack",null,null],[17,"IA32_SYSENTER_EIP","","CPL 0 code entry point (R/W) See Table 35-2. See Section 5.8.7, Performing  Fast Calls to System Procedures with the SYSENTER and SYSEXIT Instructions.",null,null],[17,"SYSENTER_EIP_MSR","","CPL 0 code entry point",null,null],[17,"MCG_CAP","","",null,null],[17,"IA32_MCG_CAP","","Machine Check Capabilities (R) See Table 35-2. See Section 15.3.1.1,  IA32_MCG_CAP MSR.",null,null],[17,"IA32_MCG_STATUS","","Machine Check Status. (R) See Table 35-2. See Section 15.3.1.2,  IA32_MCG_STATUS MSR.",null,null],[17,"MCG_STATUS","","",null,null],[17,"MCG_CTL","","",null,null],[17,"IA32_MCG_CTL","","Machine Check Feature Enable (R/W) See Table 35-2. See Section 15.3.1.3, IA32_MCG_CTL MSR.",null,null],[17,"MSR_SMM_MCA_CAP","","Enhanced SMM Capabilities (SMM-RO) Reports SMM capability Enhancement. Accessible only while in  SMM.",null,null],[17,"MSR_ERROR_CONTROL","","MC Bank Error Configuration (R/W)",null,null],[17,"MSR_MCG_RAX","","Machine Check EAX/RAX Save State See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_RBX","","Machine Check EBX/RBX Save State See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_RCX","","Machine Check ECX/RCX Save State See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_RDX","","Machine Check EDX/RDX Save State See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_RSI","","Machine Check ESI/RSI Save State See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_RDI","","Machine Check EDI/RDI Save State See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_RBP","","Machine Check EBP/RBP Save State See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"IA32_PERFEVTSEL0","","Performance Event Select for Counter 0 (R/W) Supports all fields described inTable 35-2 and the fields below.",null,null],[17,"IA32_PERFEVTSEL1","","Performance Event Select for Counter 1 (R/W) Supports all fields described inTable 35-2 and the fields below.",null,null],[17,"IA32_PERFEVTSEL2","","Performance Event Select for Counter 2 (R/W) Supports all fields described inTable 35-2 and the fields below.",null,null],[17,"MSR_MCG_RFLAGS","","Machine Check EFLAGS/RFLAG Save State See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"IA32_PERFEVTSEL3","","Performance Event Select for Counter 3 (R/W) Supports all fields described inTable 35-2 and the fields below.",null,null],[17,"MSR_MCG_RIP","","Machine Check EIP/RIP Save State See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_MISC","","Machine Check Miscellaneous See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"IA32_PERFEVTSEL4","","See Table 35-2; If CPUID.0AH:EAX[15:8] = 8",null,null],[17,"IA32_PERFEVTSEL5","","See Table 35-2; If CPUID.0AH:EAX[15:8] = 8",null,null],[17,"IA32_PERFEVTSEL6","","See Table 35-2; If CPUID.0AH:EAX[15:8] = 8",null,null],[17,"IA32_PERFEVTSEL7","","See Table 35-2; If CPUID.0AH:EAX[15:8] = 8",null,null],[17,"MSR_MCG_R8","","Machine Check R8 See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_R9","","Machine Check R9D/R9 See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_R10","","Machine Check R10 See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_R11","","Machine Check R11 See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_R12","","Machine Check R12 See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_R13","","Machine Check R13 See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_MCG_R14","","Machine Check R14 See Section 15.3.2.6, IA32_MCG Extended  Machine Check State MSRs.",null,null],[17,"MSR_PERF_STATUS","","",null,null],[17,"IA32_PERF_STATUS","","See Table 35-2. See Section 14.1, Enhanced Intel  Speedstep® Technology.",null,null],[17,"IA32_PERF_CTL","","See Table 35-2. See Section 14.1, Enhanced Intel  Speedstep® Technology.",null,null],[17,"IA32_CLOCK_MODULATION","","Clock Modulation (R/W)  See Table 35-2. IA32_CLOCK_MODULATION MSR was originally named  IA32_THERM_CONTROL MSR.",null,null],[17,"IA32_THERM_INTERRUPT","","Thermal Interrupt Control (R/W) See Section 14.5.2, Thermal Monitor,  and see Table 35-2.",null,null],[17,"IA32_THERM_STATUS","","Thermal Monitor Status (R/W) See Section 14.5.2, Thermal Monitor,  and see  Table 35-2.",null,null],[17,"MSR_THERM2_CTL","","Thermal Monitor 2 Control.",null,null],[17,"IA32_MISC_ENABLE","","",null,null],[17,"MSR_PLATFORM_BRV","","Platform Feature Requirements (R)",null,null],[17,"MSR_TEMPERATURE_TARGET","","",null,null],[17,"MSR_OFFCORE_RSP_0","","Offcore Response Event Select Register (R/W)",null,null],[17,"MSR_OFFCORE_RSP_1","","Offcore Response Event Select Register (R/W)",null,null],[17,"MSR_MISC_PWR_MGMT","","See http://biosbits.org.",null,null],[17,"MSR_TURBO_POWER_CURRENT_LIMIT","","See http://biosbits.org.",null,null],[17,"MSR_TURBO_RATIO_LIMIT","","Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0, RW if MSR_PLATFORM_INFO.[28] = 1",null,null],[17,"IA32_ENERGY_PERF_BIAS","","if CPUID.6H:ECX[3] = 1",null,null],[17,"IA32_PACKAGE_THERM_STATUS","","If CPUID.06H: EAX[6] = 1",null,null],[17,"IA32_PACKAGE_THERM_INTERRUPT","","If CPUID.06H: EAX[6] = 1",null,null],[17,"MSR_LBR_SELECT","","Last Branch Record Filtering Select Register (R/W)  See Section 17.6.2, Filtering of Last Branch Records.",null,null],[17,"MSR_LASTBRANCH_TOS","","Last Branch Record Stack TOS (R/W)  Contains an index (0-3 or 0-15) that points to the  top of the last branch record stack (that is, that points the index of the MSR containing the most  recent branch record). See Section 17.9.2, LBR Stack for Processors Based on Intel NetBurst® Microarchitecture ; and  addresses 1DBH-1DEH and 680H-68FH.",null,null],[17,"DEBUGCTLMSR","","",null,null],[17,"MSR_DEBUGCTLA","","Debug Control (R/W)  Controls how several debug features are used. Bit  definitions are discussed in the referenced section. See Section 17.9.1, MSR_DEBUGCTLA MSR.",null,null],[17,"MSR_DEBUGCTLB","","Debug Control (R/W)  Controls how several debug features are used. Bit definitions are discussed in the referenced section. See Section 17.11, Last Branch, Interrupt, and Exception Recording  (Pentium M Processors).",null,null],[17,"IA32_DEBUGCTL","","Debug Control (R/W)  Controls how several debug features are used. Bit definitions are  discussed in the referenced section.",null,null],[17,"LASTBRANCHFROMIP","","",null,null],[17,"MSR_LASTBRANCH_0","","Last Branch Record 0 (R/W)  One of four last branch record registers on the last  branch record stack. It contains pointers to the  source and destination instruction for one of the  last four branches, exceptions, or interrupts that  the processor took. MSR_LASTBRANCH_0 through  MSR_LASTBRANCH_3 at 1DBH-1DEH are  available only on family 0FH, models 0H-02H.  They have been replaced by the MSRs at 680H- 68FH and 6C0H-6CFH.",null,null],[17,"LASTBRANCHTOIP","","",null,null],[17,"LASTINTFROMIP","","",null,null],[17,"MSR_LASTBRANCH_2","","Last Branch Record 2 See description of the MSR_LASTBRANCH_0 MSR at 1DBH.",null,null],[17,"MSR_LER_FROM_LIP","","Last Exception Record From Linear IP (R)  Contains a pointer to the last branch instruction that the processor  executed prior to the last exception that was generated or the last  interrupt that was handled. See Section 17.11, Last Branch, Interrupt, and Exception Recording  (Pentium M Processors)  and Section 17.12.2, Last Branch and Last  Exception MSRs.",null,null],[17,"LASTINTTOIP","","",null,null],[17,"MSR_LASTBRANCH_3","","Last Branch Record 3 See description of the MSR_LASTBRANCH_0 MSR  at 1DBH.",null,null],[17,"MSR_LER_TO_LIP","","Last Exception Record To Linear IP (R)  This area contains a pointer to the target of the last branch instruction  that the processor executed prior to the last exception that was  generated or the last interrupt that was handled. See Section 17.11, Last Branch, Interrupt, and Exception Recording  (Pentium M Processors)  and Section 17.12.2, Last Branch and Last  Exception MSRs.",null,null],[17,"ROB_CR_BKUPTMPDR6","","",null,null],[17,"IA32_SMRR_PHYSBASE","","See Table 35-2.",null,null],[17,"IA32_SMRR_PHYSMASK","","If IA32_MTRR_CAP[SMRR]  = 1",null,null],[17,"IA32_PLATFORM_DCA_CAP","","06_0FH",null,null],[17,"IA32_CPU_DCA_CAP","","",null,null],[17,"IA32_DCA_0_CAP","","06_2EH",null,null],[17,"MSR_POWER_CTL","","Power Control Register. See http://biosbits.org.",null,null],[17,"IA32_MTRR_PHYSBASE0","","Variable Range Base MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSMASK0","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSBASE1","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSMASK1","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSBASE2","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSMASK2","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs .",null,null],[17,"IA32_MTRR_PHYSBASE3","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSMASK3","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSBASE4","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSMASK4","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSBASE5","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSMASK5","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSBASE6","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSMASK6","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSBASE7","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSMASK7","","Variable Range Mask MTRR See Section 11.11.2.3, Variable Range MTRRs.",null,null],[17,"IA32_MTRR_PHYSBASE8","","if IA32_MTRR_CAP[7:0] >  8",null,null],[17,"IA32_MTRR_PHYSMASK8","","if IA32_MTRR_CAP[7:0] >  8",null,null],[17,"IA32_MTRR_PHYSBASE9","","if IA32_MTRR_CAP[7:0] >  9",null,null],[17,"IA32_MTRR_PHYSMASK9","","if IA32_MTRR_CAP[7:0] >  9",null,null],[17,"IA32_MTRR_FIX64K_00000","","Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.",null,null],[17,"IA32_MTRR_FIX16K_80000","","Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.",null,null],[17,"IA32_MTRR_FIX16K_A0000","","Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.",null,null],[17,"IA32_MTRR_FIX4K_C0000","","Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.",null,null],[17,"IA32_MTRR_FIX4K_C8000","","Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs .",null,null],[17,"IA32_MTRR_FIX4K_D0000","","Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs .",null,null],[17,"IA32_MTRR_FIX4K_D8000","","Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.",null,null],[17,"IA32_MTRR_FIX4K_E0000","","Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.",null,null],[17,"IA32_MTRR_FIX4K_E8000","","Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.",null,null],[17,"IA32_MTRR_FIX4K_F0000","","Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.",null,null],[17,"IA32_MTRR_FIX4K_F8000","","Fixed Range MTRR See Section 11.11.2.2, Fixed Range MTRRs.",null,null],[17,"IA32_PAT","","Page Attribute Table See Section 11.11.2.2, Fixed Range MTRRs.",null,null],[17,"IA32_MC0_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC1_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC2_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC3_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC4_CTL2","","See Table 35-2.",null,null],[17,"MSR_MC4_CTL2","","Always 0 (CMCI not supported).",null,null],[17,"IA32_MC5_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC6_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC7_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC8_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC9_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC10_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC11_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC12_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC13_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC14_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC15_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC16_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC17_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC18_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC19_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC20_CTL2","","See Table 35-2.",null,null],[17,"IA32_MC21_CTL2","","See Table 35-2.",null,null],[17,"IA32_MTRR_DEF_TYPE","","Default Memory Types (R/W)  Sets the memory type for the regions of physical memory that are not  mapped by the MTRRs.  See Section 11.11.2.1, IA32_MTRR_DEF_TYPE MSR.",null,null],[17,"MSR_BPU_COUNTER0","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_GQ_SNOOP_MESF","","",null,null],[17,"MSR_BPU_COUNTER1","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_BPU_COUNTER2","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_BPU_COUNTER3","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_MS_COUNTER0","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_MS_COUNTER1","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_MS_COUNTER2","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_MS_COUNTER3","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_FLAME_COUNTER0","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_PERF_FIXED_CTR0","","Fixed-Function Performance Counter Register 0 (R/W)",null,null],[17,"IA32_FIXED_CTR0","","Fixed-Function Performance Counter Register 0 (R/W)  See Table 35-2.",null,null],[17,"MSR_FLAME_COUNTER1","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_PERF_FIXED_CTR1","","Fixed-Function Performance Counter Register 1 (R/W)",null,null],[17,"IA32_FIXED_CTR1","","Fixed-Function Performance Counter Register 1 (R/W)  See Table 35-2.",null,null],[17,"MSR_FLAME_COUNTER2","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_PERF_FIXED_CTR2","","Fixed-Function Performance Counter Register 2 (R/W)",null,null],[17,"IA32_FIXED_CTR2","","Fixed-Function Performance Counter Register 2 (R/W)  See Table 35-2.",null,null],[17,"MSR_FLAME_COUNTER3","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_IQ_COUNTER4","","See Section 18.12.2, Performance Counters.",null,null],[17,"MSR_IQ_COUNTER5","","See Section 18.12.2, Performance Counters.",null,null],[17,"IA32_PERF_CAPABILITIES","","See Table 35-2. See Section 17.4.1, IA32_DEBUGCTL MSR.",null,null],[17,"MSR_PERF_CAPABILITIES","","RO. This applies to processors that do not support architectural  perfmon version 2.",null,null],[17,"MSR_BPU_CCCR0","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_BPU_CCCR1","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_BPU_CCCR2","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_BPU_CCCR3","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_MS_CCCR0","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_MS_CCCR1","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_MS_CCCR2","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_MS_CCCR3","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_FLAME_CCCR0","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_FLAME_CCCR1","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_FLAME_CCCR2","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_FLAME_CCCR3","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_IQ_CCCR0","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_IQ_CCCR1","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_IQ_CCCR2","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_IQ_CCCR3","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_IQ_CCCR4","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_IQ_CCCR5","","See Section 18.12.3, CCCR MSRs.",null,null],[17,"MSR_PERF_FIXED_CTR_CTRL","","Fixed-Function-Counter Control Register (R/W)",null,null],[17,"IA32_FIXED_CTR_CTRL","","Fixed-Function-Counter Control Register (R/W)  See Table 35-2.",null,null],[17,"MSR_PERF_GLOBAL_STAUS","","See Section 18.4.2, Global Counter Control Facilities.",null,null],[17,"IA32_PERF_GLOBAL_STAUS","","See Table 35-2. See Section 18.4.2, Global Counter Control  Facilities.",null,null],[17,"MSR_PERF_GLOBAL_CTRL","","See Section 18.4.2, Global Counter Control Facilities.",null,null],[17,"IA32_PERF_GLOBAL_CTRL","","See Table 35-2. See Section 18.4.2, Global Counter Control  Facilities.",null,null],[17,"MSR_PERF_GLOBAL_OVF_CTRL","","See Section 18.4.2, Global Counter Control Facilities.",null,null],[17,"IA32_PERF_GLOBAL_OVF_CTRL","","See Table 35-2. See Section 18.4.2, Global Counter Control  Facilities.",null,null],[17,"MSR_UNCORE_PERF_GLOBAL_CTRL","","See Section 18.7.2.1, Uncore Performance Monitoring  Management Facility.",null,null],[17,"MSR_UNC_PERF_GLOBAL_CTRL","","Uncore PMU global control",null,null],[17,"MSR_UNCORE_PERF_GLOBAL_STATUS","","See Section 18.7.2.1, Uncore Performance Monitoring  Management Facility.",null,null],[17,"MSR_UNC_PERF_GLOBAL_STATUS","","Uncore PMU main status",null,null],[17,"MSR_UNCORE_PERF_GLOBAL_OVF_CTRL","","See Section 18.7.2.1, Uncore Performance Monitoring  Management Facility.",null,null],[17,"MSR_UNCORE_FIXED_CTR0","","See Section 18.7.2.1, Uncore Performance Monitoring  Management Facility.",null,null],[17,"MSR_W_PMON_FIXED_CTR","","Uncore W-box perfmon fixed counter",null,null],[17,"MSR_UNC_PERF_FIXED_CTRL","","Uncore fixed counter control (R/W)",null,null],[17,"MSR_UNCORE_FIXED_CTR_CTRL","","See Section 18.7.2.1, Uncore Performance Monitoring  Management Facility.",null,null],[17,"MSR_W_PMON_FIXED_CTR_CTL","","Uncore U-box perfmon fixed counter control MSR",null,null],[17,"MSR_UNC_PERF_FIXED_CTR","","Uncore fixed counter",null,null],[17,"MSR_UNCORE_ADDR_OPCODE_MATCH","","See Section 18.7.2.3, Uncore Address/Opcode Match MSR.",null,null],[17,"MSR_UNC_CBO_CONFIG","","Uncore C-Box configuration information (R/O)",null,null],[17,"MSR_PEBS_NUM_ALT","","",null,null],[17,"MSR_BSU_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_BSU_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_FSB_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_FSB_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_FIRM_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_FIRM_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_FLAME_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_FLAME_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_DAC_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_DAC_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_MOB_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_MOB_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_PMH_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_PMH_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_SAAT_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_SAAT_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_U2L_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PMC0","","See Section 18.7.2.2, Uncore Performance Event Configuration  Facility.",null,null],[17,"MSR_UNC_ARB_PER_CTR0","","Uncore Arb unit, performance counter 0",null,null],[17,"MSR_U2L_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PMC1","","See Section 18.7.2.2, Uncore Performance Event Configuration  Facility.",null,null],[17,"MSR_UNC_ARB_PER_CTR1","","Uncore Arb unit, performance counter 1",null,null],[17,"MSR_BPU_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PMC2","","See Section 18.7.2.2, Uncore Performance Event Configuration  Facility.",null,null],[17,"MSR_UNC_ARB_PERFEVTSEL0","","Uncore Arb unit, counter 0 event select MSR",null,null],[17,"MSR_BPU_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PMC3","","See Section 18.7.2.2, Uncore Performance Event Configuration Facility.",null,null],[17,"MSR_UNC_ARB_PERFEVTSEL1","","Uncore Arb unit, counter 1 event select MSR",null,null],[17,"MSR_IS_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PMC4","","See Section 18.7.2.2, Uncore Performance Event Configuration Facility.",null,null],[17,"MSR_IS_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PMC5","","See Section 18.7.2.2, Uncore Performance Event Configuration  Facility.",null,null],[17,"MSR_ITLB_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PMC6","","See Section 18.7.2.2, Uncore Performance Event Configuration Facility.",null,null],[17,"MSR_ITLB_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PMC7","","See Section 18.7.2.2, Uncore Performance Event Configuration Facility.",null,null],[17,"MSR_CRU_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_CRU_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_IQ_ESCR0","","See Section 18.12.1, ESCR MSRs. This MSR is not available on later processors. It is  only available on processor family 0FH, models  01H-02H.",null,null],[17,"MSR_IQ_ESCR1","","See Section 18.12.1, ESCR MSRs. This MSR is not available on later processors. It is  only available on processor family 0FH, models  01H-02H.",null,null],[17,"MSR_RAT_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_RAT_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_SSU_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_MS_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PERFEVTSEL0","","See Section 18.7.2.2, Uncore Performance Event Configuration Facility.",null,null],[17,"MSR_MS_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PERFEVTSEL1","","See Section 18.7.2.2, Uncore Performance Event Configuration Facility.",null,null],[17,"MSR_TBPU_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PERFEVTSEL2","","See Section 18.7.2.2, Uncore Performance Event Configuration Facility.",null,null],[17,"MSR_TBPU_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PERFEVTSEL3","","See Section 18.7.2.2, Uncore Performance Event Configuration Facility.",null,null],[17,"MSR_TC_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PERFEVTSEL4","","See Section 18.7.2.2, Uncore Performance Event Configuration Facility.",null,null],[17,"MSR_TC_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_UNCORE_PERFEVTSEL5","","See Section 18.7.2.2, Uncore Performance Event Configuration Facility.",null,null],[17,"MSR_UNCORE_PERFEVTSEL6","","See Section 18.7.2.2, Uncore Performance Event Configuration Facility.",null,null],[17,"MSR_UNCORE_PERFEVTSEL7","","See Section 18.7.2.2, Uncore Performance Event Configuration Facility.",null,null],[17,"MSR_IX_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_ALF_ESCR0","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_ALF_ESCR1","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_CRU_ESCR2","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_CRU_ESCR3","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_CRU_ESCR4","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"MSR_CRU_ESCR5","","See Section 18.12.1, ESCR MSRs.",null,null],[17,"IA32_PEBS_ENABLE","","",null,null],[17,"MSR_PEBS_ENABLE","","Precise Event-Based Sampling (PEBS) (R/W)  Controls the enabling of precise event sampling  and replay tagging.",null,null],[17,"MSR_PEBS_MATRIX_VERT","","See Table 19-26.",null,null],[17,"MSR_PEBS_LD_LAT","","see See Section 18.7.1.2, Load Latency Performance Monitoring  Facility.",null,null],[17,"MSR_PKG_C3_RESIDENCY","","Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C- States.",null,null],[17,"MSR_PKG_C2_RESIDENCY","","Package C2 Residency Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C-States",null,null],[17,"MSR_PKG_C6C_RESIDENCY","","Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C- States.",null,null],[17,"MSR_PKG_C4_RESIDENCY","","Package C4 Residency Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States",null,null],[17,"MSR_PKG_C7_RESIDENCY","","Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C- States.",null,null],[17,"MSR_PKG_C6_RESIDENCY","","Package C6 Residency Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C-States",null,null],[17,"MSR_CORE_C3_RESIDENCY","","Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C- States.",null,null],[17,"MSR_CORE_C4_RESIDENCY","","Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C- States.",null,null],[17,"MSR_CORE_C6_RESIDENCY","","Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C- States.",null,null],[17,"MSR_CORE_C7_RESIDENCY","","Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C- States.",null,null],[17,"MC0_CTL","","",null,null],[17,"IA32_MC0_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"MC0_STATUS","","",null,null],[17,"IA32_MC0_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"MC0_ADDR","","",null,null],[17,"IA32_MC0_ADDR1","","P6 Family Processors",null,null],[17,"IA32_MC0_ADDR","","See Section 14.3.2.3., IA32_MCi_ADDR MSRs .  The IA32_MC0_ADDR register is either not implemented or contains no address if the ADDRV flag in the IA32_MC0_STATUS register is clear.  When not implemented in the processor, all reads and writes to this MSR  will cause a general-protection exception.",null,null],[17,"MC0_MISC","","Defined in MCA architecture but not implemented in the P6 family  processors.",null,null],[17,"IA32_MC0_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs. The IA32_MC0_MISC MSR is either not  implemented or does not contain additional  information if the MISCV flag in the  IA32_MC0_STATUS register is clear. When not implemented in the processor, all reads  and writes to this MSR will cause a general- protection exception.",null,null],[17,"MSR_MC0_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"MC1_CTL","","",null,null],[17,"IA32_MC1_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"MC1_STATUS","","Bit definitions same as MC0_STATUS.",null,null],[17,"IA32_MC1_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"MC1_ADDR","","",null,null],[17,"IA32_MC1_ADDR2","","P6 Family Processors",null,null],[17,"IA32_MC1_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The IA32_MC1_ADDR register is either not implemented or  contains no address if the ADDRV flag in the IA32_MC1_STATUS  register is clear.  When not implemented in the processor, all reads and writes to this  MSR will cause a general-protection exception.",null,null],[17,"MC1_MISC","","Defined in MCA architecture but not implemented in the P6 family  processors.",null,null],[17,"IA32_MC1_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs. The IA32_MC1_MISC MSR is either not  implemented or does not contain additional  information if the MISCV flag in the  IA32_MC1_STATUS register is clear. When not implemented in the processor, all reads  and writes to this MSR will cause a general- protection exception.",null,null],[17,"MSR_MC1_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"MC2_CTL","","",null,null],[17,"IA32_MC2_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"MC2_STATUS","","Bit definitions same as MC0_STATUS.",null,null],[17,"IA32_MC2_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"MC2_ADDR","","",null,null],[17,"IA32_MC2_ADDR1","","P6 Family Processors",null,null],[17,"IA32_MC2_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The IA32_MC2_ADDR register is either not  implemented or contains no address if the ADDRV  flag in the IA32_MC2_STATUS register is clear.  When not implemented in the processor, all reads  and writes to this MSR will cause a general- protection exception.",null,null],[17,"MC2_MISC","","Defined in MCA architecture but not implemented in the P6 family  processors.",null,null],[17,"IA32_MC2_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs. The IA32_MC2_MISC MSR is either not  implemented or does not contain additional  information if the MISCV flag in the IA32_MC2_STATUS register is clear.  When not implemented in the processor, all reads  and writes to this MSR will cause a general- protection exception.",null,null],[17,"MSR_MC2_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"MC4_CTL","","",null,null],[17,"IA32_MC3_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"MSR_MC4_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"MC4_STATUS","","Bit definitions same as MC0_STATUS, except bits 0, 4, 57, and 61 are  hardcoded to 1.",null,null],[17,"IA32_MC3_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"MSR_MC4_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS.",null,null],[17,"MC4_ADDR","","Defined in MCA architecture but not implemented in P6 Family processors.",null,null],[17,"IA32_MC3_ADDR1","","P6 Family Processors",null,null],[17,"IA32_MC3_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The IA32_MC3_ADDR register is either not  implemented or contains no address if the ADDRV  flag in the IA32_MC3_STATUS register is clear. When not implemented in the processor, all reads  and writes to this MSR will cause a general- protection exception.",null,null],[17,"MSR_MC4_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The MSR_MC4_ADDR register is either not implemented or  contains no address if the ADDRV flag in the MSR_MC4_STATUS  register is clear. When not implemented in the processor, all reads and writes to this  MSR will cause a general-protection exception.",null,null],[17,"MC4_MISC","","Defined in MCA architecture but not implemented in the P6 family  processors.",null,null],[17,"IA32_MC3_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs. The IA32_MC3_MISC MSR is either not  implemented or does not contain additional  information if the MISCV flag in the  IA32_MC3_STATUS register is clear. When not implemented in the processor, all reads  and writes to this MSR will cause a general- protection exception.",null,null],[17,"MC3_CTL","","",null,null],[17,"IA32_MC4_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"MSR_MC3_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"MC3_STATUS","","Bit definitions same as MC0_STATUS.",null,null],[17,"IA32_MC4_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"MSR_MC3_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS.",null,null],[17,"MC3_ADDR","","",null,null],[17,"IA32_MC4_ADDR1","","P6 Family Processors",null,null],[17,"IA32_MC4_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The IA32_MC2_ADDR register is either not  implemented or contains no address if the ADDRV  flag in the IA32_MC4_STATUS register is clear.  When not implemented in the processor, all reads  and writes to this MSR will cause a general- protection exception.",null,null],[17,"MSR_MC3_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The MSR_MC3_ADDR register is either not implemented or  contains no address if the ADDRV flag in the MSR_MC3_STATUS register is clear.  When not implemented in the processor, all reads and writes to this  MSR will cause a general-protection exception.",null,null],[17,"MSR_MC3_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"MC3_MISC","","Defined in MCA architecture but not implemented in the P6 family  processors.",null,null],[17,"IA32_MC4_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.   The IA32_MC2_MISC MSR is either not  implemented or does not contain additional  information if the MISCV flag in the  IA32_MC4_STATUS register is clear.  When not implemented in the processor, all reads  and writes to this MSR will cause a general- protection exception.",null,null],[17,"MSR_MC4_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"MSR_MC5_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC5_CTL","","06_0FH",null,null],[17,"MSR_MC5_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC5_STATUS","","06_0FH",null,null],[17,"MSR_MC5_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs. The MSR_MC4_ADDR register is either not implemented or  contains no address if the ADDRV flag in the MSR_MC4_STATUS  register is clear. When not implemented in the processor, all reads and writes to this  MSR will cause a general-protection exception.",null,null],[17,"IA32_MC5_ADDR1","","06_0FH",null,null],[17,"MSR_MC5_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC5_MISC","","06_0FH",null,null],[17,"IA32_MC6_CTL","","06_1DH",null,null],[17,"MSR_MC6_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC6_STATUS","","06_1DH",null,null],[17,"MSR_MC6_STATUS","","Apply to Intel Xeon processor 7400 series (processor signature  06_1D) only. See Section 15.3.2.2, IA32_MCi_STATUS MSRS.  and  Chapter 23.",null,null],[17,"IA32_MC6_ADDR1","","06_1DH",null,null],[17,"MSR_MC6_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC6_MISC","","Misc MAC information of Integrated I/O. (R/O) see Section 15.3.2.4",null,null],[17,"MSR_MC6_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC7_CTL","","06_1AH",null,null],[17,"MSR_MC7_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC7_STATUS","","06_1AH",null,null],[17,"MSR_MC7_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC7_ADDR1","","06_1AH",null,null],[17,"MSR_MC7_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC7_MISC","","06_1AH",null,null],[17,"MSR_MC7_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC8_CTL","","06_1AH",null,null],[17,"MSR_MC8_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC8_STATUS","","06_1AH",null,null],[17,"MSR_MC8_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC8_ADDR1","","06_1AH",null,null],[17,"MSR_MC8_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC8_MISC","","06_1AH",null,null],[17,"MSR_MC8_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC9_CTL","","06_2EH",null,null],[17,"MSR_MC9_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC9_STATUS","","06_2EH",null,null],[17,"MSR_MC9_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC9_ADDR1","","06_2EH",null,null],[17,"MSR_MC9_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC9_MISC","","06_2EH",null,null],[17,"MSR_MC9_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC10_CTL","","06_2EH",null,null],[17,"MSR_MC10_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC10_STATUS","","06_2EH",null,null],[17,"MSR_MC10_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC10_ADDR1","","06_2EH",null,null],[17,"MSR_MC10_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC10_MISC","","06_2EH",null,null],[17,"MSR_MC10_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC11_CTL","","06_2EH",null,null],[17,"MSR_MC11_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC11_STATUS","","06_2EH",null,null],[17,"MSR_MC11_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC11_ADDR1","","06_2EH",null,null],[17,"MSR_MC11_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC11_MISC","","06_2EH",null,null],[17,"MSR_MC11_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC12_CTL","","06_2EH",null,null],[17,"MSR_MC12_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC12_STATUS","","06_2EH",null,null],[17,"MSR_MC12_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC12_ADDR1","","06_2EH",null,null],[17,"MSR_MC12_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC12_MISC","","06_2EH",null,null],[17,"MSR_MC12_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC13_CTL","","06_2EH",null,null],[17,"MSR_MC13_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC13_STATUS","","06_2EH",null,null],[17,"MSR_MC13_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC13_ADDR1","","06_2EH",null,null],[17,"MSR_MC13_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC13_MISC","","06_2EH",null,null],[17,"MSR_MC13_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC14_CTL","","06_2EH",null,null],[17,"MSR_MC14_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC14_STATUS","","06_2EH",null,null],[17,"MSR_MC14_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC14_ADDR1","","06_2EH",null,null],[17,"MSR_MC14_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC14_MISC","","06_2EH",null,null],[17,"MSR_MC14_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC15_CTL","","06_2EH",null,null],[17,"MSR_MC15_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC15_STATUS","","06_2EH",null,null],[17,"MSR_MC15_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC15_ADDR1","","06_2EH",null,null],[17,"MSR_MC15_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC15_MISC","","06_2EH",null,null],[17,"MSR_MC15_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC16_CTL","","06_2EH",null,null],[17,"MSR_MC16_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC16_STATUS","","06_2EH",null,null],[17,"MSR_MC16_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC16_ADDR1","","06_2EH",null,null],[17,"MSR_MC16_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC16_MISC","","06_2EH",null,null],[17,"MSR_MC16_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC17_CTL","","06_2EH",null,null],[17,"MSR_MC17_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC17_STATUS","","06_2EH",null,null],[17,"MSR_MC17_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC17_ADDR1","","06_2EH",null,null],[17,"MSR_MC17_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC17_MISC","","06_2EH",null,null],[17,"MSR_MC17_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC18_CTL","","06_2EH",null,null],[17,"MSR_MC18_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC18_STATUS","","06_2EH",null,null],[17,"MSR_MC18_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC18_ADDR1","","06_2EH",null,null],[17,"MSR_MC18_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC18_MISC","","06_2EH",null,null],[17,"MSR_MC18_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC19_CTL","","06_2EH",null,null],[17,"MSR_MC19_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC19_STATUS","","06_2EH",null,null],[17,"MSR_MC19_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC19_ADDR1","","06_2EH",null,null],[17,"MSR_MC19_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC19_MISC","","06_2EH",null,null],[17,"MSR_MC19_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC20_CTL","","06_2EH",null,null],[17,"MSR_MC20_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC20_STATUS","","06_2EH",null,null],[17,"MSR_MC20_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC20_ADDR1","","06_2EH",null,null],[17,"MSR_MC20_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC20_MISC","","06_2EH",null,null],[17,"MSR_MC20_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_MC21_CTL","","06_2EH",null,null],[17,"MSR_MC21_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"IA32_MC21_STATUS","","06_2EH",null,null],[17,"MSR_MC21_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"IA32_MC21_ADDR1","","06_2EH",null,null],[17,"MSR_MC21_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"IA32_MC21_MISC","","06_2EH",null,null],[17,"MSR_MC21_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"MSR_MC22_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"MSR_MC22_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"MSR_MC22_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"MSR_MC22_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"MSR_MC23_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"MSR_MC23_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"MSR_MC23_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"MSR_MC23_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"MSR_MC24_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"MSR_MC24_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"MSR_MC24_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"MSR_MC24_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"MSR_MC25_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"MSR_MC25_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"MSR_MC25_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"MSR_MC25_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"MSR_MC26_CTL","","See Section 15.3.2.1,  IA32_MCi_CTL MSRs.",null,null],[17,"MSR_MC26_STATUS","","See Section 15.3.2.2, IA32_MCi_STATUS MSRS,  and Chapter 16.",null,null],[17,"MSR_MC26_ADDR","","See Section 15.3.2.3, IA32_MCi_ADDR MSRs.",null,null],[17,"MSR_MC26_MISC","","See Section 15.3.2.4,  IA32_MCi_MISC MSRs.",null,null],[17,"IA32_VMX_BASIC","","Reporting Register of Basic VMX Capabilities (R/O) See Table 35-2. See Appendix A.1, Basic VMX Information (If CPUID.01H:ECX.[bit 9])",null,null],[17,"IA32_VMX_PINBASED_CTLS","","Capability Reporting Register of Pin-based VM-execution  Controls (R/O) See Appendix A.3, VM-Execution Controls (If CPUID.01H:ECX.[bit 9])",null,null],[17,"IA32_VMX_PROCBASED_CTLS","","Capability Reporting Register of Primary Processor-based  VM-execution Controls (R/O) See Appendix A.3, VM-Execution Controls (If CPUID.01H:ECX.[bit 9])",null,null],[17,"IA32_VMX_EXIT_CTLS","","Capability Reporting Register of VM-exit Controls (R/O) See Appendix A.4, VM-Exit Controls (If CPUID.01H:ECX.[bit 9])",null,null],[17,"IA32_VMX_ENTRY_CTLS","","Capability Reporting Register of VM-entry Controls (R/O) See Appendix A.5, VM-Entry Controls (If CPUID.01H:ECX.[bit 9])",null,null],[17,"IA32_VMX_MISC","","Reporting Register of Miscellaneous VMX Capabilities (R/O) See Appendix A.6, Miscellaneous Data (If CPUID.01H:ECX.[bit 9])",null,null],[17,"IA32_VMX_CR0_FIXED0","","Capability Reporting Register of CR0 Bits Fixed to 0 (R/O) See Appendix A.7, VMX-Fixed Bits in CR0 (If CPUID.01H:ECX.[bit 9])",null,null],[17,"IA32_VMX_CRO_FIXED0","","If CPUID.01H:ECX.[bit 5] = 1",null,null],[17,"IA32_VMX_CR0_FIXED1","","Capability Reporting Register of CR0 Bits Fixed to 1 (R/O) See Appendix A.7, VMX-Fixed Bits in CR0 (If CPUID.01H:ECX.[bit 9])",null,null],[17,"IA32_VMX_CRO_FIXED1","","If CPUID.01H:ECX.[bit 5] = 1",null,null],[17,"IA32_VMX_CR4_FIXED0","","Capability Reporting Register of CR4 Bits Fixed to 0 (R/O) See Appendix A.8, VMX-Fixed Bits in CR4 (If CPUID.01H:ECX.[bit 9])",null,null],[17,"IA32_VMX_CR4_FIXED1","","Capability Reporting Register of CR4 Bits Fixed to 1 (R/O) See Appendix A.8, VMX-Fixed Bits in CR4 (If CPUID.01H:ECX.[bit 9])",null,null],[17,"IA32_VMX_VMCS_ENUM","","Capability Reporting Register of VMCS Field Enumeration (R/O) See Appendix A.9, VMCS Enumeration (If CPUID.01H:ECX.[bit 9])",null,null],[17,"IA32_VMX_PROCBASED_CTLS2","","Capability Reporting Register of Secondary Processor-based  VM-execution Controls (R/O) See Appendix A.3, VM-Execution Controls (If CPUID.01H:ECX.[bit 9] and  IA32_VMX_PROCBASED_CTLS[bit 63])",null,null],[17,"IA32_VMX_EPT_VPID_ENUM","","Capability Reporting Register of EPT and VPID (R/O)  See Table 35-2",null,null],[17,"IA32_VMX_EPT_VPID_CAP","","If ( CPUID.01H:ECX.[bit 5],  IA32_VMX_PROCBASED_C TLS[bit 63], and either  IA32_VMX_PROCBASED_C TLS2[bit 33] or  IA32_VMX_PROCBASED_C TLS2[bit 37])",null,null],[17,"IA32_VMX_TRUE_PINBASED_CTLS","","Capability Reporting Register of Pin-based VM-execution Flex  Controls (R/O) See Table 35-2",null,null],[17,"IA32_VMX_TRUE_PROCBASED_CTLS","","Capability Reporting Register of Primary Processor-based  VM-execution Flex Controls (R/O) See Table 35-2",null,null],[17,"IA32_VMX_TRUE_EXIT_CTLS","","Capability Reporting Register of VM-exit Flex Controls (R/O) See Table 35-2",null,null],[17,"IA32_VMX_TRUE_ENTRY_CTLS","","Capability Reporting Register of VM-entry Flex Controls (R/O) See Table 35-2",null,null],[17,"IA32_VMX_FMFUNC","","Capability Reporting Register of VM-function Controls (R/O) See Table 35-2",null,null],[17,"IA32_VMX_VMFUNC","","If( CPUID.01H:ECX.[bit 5] =  1 and IA32_VMX_BASIC[bit 55] )",null,null],[17,"IA32_A_PMC0","","(If CPUID.0AH: EAX[15:8] >  0) & IA32_PERF_CAPABILITIES[ 13] = 1",null,null],[17,"IA32_A_PMC1","","(If CPUID.0AH: EAX[15:8] >  1) & IA32_PERF_CAPABILITIES[ 13] = 1",null,null],[17,"IA32_A_PMC2","","(If CPUID.0AH: EAX[15:8] >  2) & IA32_PERF_CAPABILITIES[ 13] = 1",null,null],[17,"IA32_A_PMC3","","(If CPUID.0AH: EAX[15:8] >  3) & IA32_PERF_CAPABILITIES[ 13] = 1",null,null],[17,"IA32_A_PMC4","","(If CPUID.0AH: EAX[15:8] >  4) & IA32_PERF_CAPABILITIES[ 13] = 1",null,null],[17,"IA32_A_PMC5","","(If CPUID.0AH: EAX[15:8] >  5) & IA32_PERF_CAPABILITIES[ 13] = 1",null,null],[17,"IA32_A_PMC6","","(If CPUID.0AH: EAX[15:8] >  6) & IA32_PERF_CAPABILITIES[ 13] = 1",null,null],[17,"IA32_A_PMC7","","(If CPUID.0AH: EAX[15:8] >  7) & IA32_PERF_CAPABILITIES[ 13] = 1",null,null],[17,"MSR_SMM_FEATURE_CONTROL","","Enhanced SMM Feature Control (SMM-RW) Reports SMM capability Enhancement. Accessible only while in  SMM.",null,null],[17,"MSR_SMM_DELAYED","","SMM Delayed (SMM-RO) Reports the interruptible state of all logical processors in the  package . Available only while in SMM and  MSR_SMM_MCA_CAP[LONG_FLOW_INDICATION] == 1.",null,null],[17,"MSR_SMM_BLOCKED","","SMM Blocked (SMM-RO) Reports the blocked state of all logical processors in the package .  Available only while in SMM.",null,null],[17,"IA32_DS_AREA","","DS Save Area (R/W) See Table 35-2. Points to the DS buffer management area, which is used to manage the  BTS and PEBS buffers. See Section 18.12.4, Debug Store (DS)  Mechanism.",null,null],[17,"MSR_RAPL_POWER_UNIT","","Unit Multipliers used in RAPL Interfaces (R/O)  See Section 14.7.1, RAPL Interfaces.",null,null],[17,"MSR_PKGC3_IRTL","","Package C3 Interrupt Response Limit (R/W)  Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C- States.",null,null],[17,"MSR_PKGC6_IRTL","","Package C6 Interrupt Response Limit (R/W)  This MSR defines the budget allocated for the package to exit from  C6 to a C0 state, where interrupt request can be delivered to the  core and serviced. Additional core-exit latency amy be applicable  depending on the actual C-state the core is in.  Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C- States.",null,null],[17,"MSR_PKGC7_IRTL","","Package C7 Interrupt Response Limit (R/W)  This MSR defines the budget allocated for the package to exit from  C7 to a C0 state, where interrupt request can be delivered to the  core and serviced. Additional core-exit latency amy be applicable  depending on the actual C-state the core is in.  Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C-States.",null,null],[17,"MSR_PKG_POWER_LIMIT","","PKG RAPL Power Limit Control (R/W)  See Section 14.7.3, Package RAPL Domain.",null,null],[17,"MSR_PKG_ENERGY_STATUS","","PKG Energy Status (R/O)  See Section 14.7.3, Package RAPL Domain.",null,null],[17,"MSR_PKG_PERF_STATUS","","Package RAPL Perf Status (R/O)",null,null],[17,"MSR_PKG_POWER_INFO","","PKG RAPL Parameters (R/W) See Section 14.7.3,  Package RAPL  Domain.",null,null],[17,"MSR_DRAM_POWER_LIMIT","","DRAM RAPL Power Limit Control (R/W)  See Section 14.7.5, DRAM RAPL Domain.",null,null],[17,"MSR_DRAM_ENERGY_STATUS","","DRAM Energy Status (R/O)  See Section 14.7.5, DRAM RAPL Domain.",null,null],[17,"MSR_DRAM_PERF_STATUS","","DRAM Performance Throttling Status (R/O) See Section 14.7.5,  DRAM RAPL Domain.",null,null],[17,"MSR_DRAM_POWER_INFO","","DRAM RAPL Parameters (R/W) See Section 14.7.5, DRAM RAPL Domain.",null,null],[17,"MSR_PKG_C9_RESIDENCY","","Note: C-state values are processor specific C-state code names, unrelated to MWAIT extension C-state parameters or ACPI C-States.",null,null],[17,"MSR_PKG_C10_RESIDENCY","","Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C-States.",null,null],[17,"MSR_PP0_POWER_LIMIT","","PP0 RAPL Power Limit Control (R/W)  See Section 14.7.4, PP0/PP1 RAPL Domains.",null,null],[17,"MSR_PP0_ENERGY_STATUS","","PP0 Energy Status (R/O)  See Section 14.7.4, PP0/PP1 RAPL Domains.",null,null],[17,"MSR_PP0_POLICY","","PP0 Balance Policy (R/W)  See Section 14.7.4, PP0/PP1 RAPL Domains.",null,null],[17,"MSR_PP0_PERF_STATUS","","PP0 Performance Throttling Status (R/O) See Section 14.7.4,  PP0/PP1 RAPL Domains.",null,null],[17,"MSR_PP1_POWER_LIMIT","","PP1 RAPL Power Limit Control (R/W)  See Section 14.7.4, PP0/PP1 RAPL Domains.",null,null],[17,"MSR_PP1_ENERGY_STATUS","","PP1 Energy Status (R/O)  See Section 14.7.4, PP0/PP1 RAPL Domains.",null,null],[17,"MSR_PP1_POLICY","","PP1 Balance Policy (R/W)  See Section 14.7.4, PP0/PP1 RAPL Domains.",null,null],[17,"MSR_CONFIG_TDP_NOMINAL","","Nominal TDP Ratio (R/O)",null,null],[17,"MSR_CONFIG_TDP_LEVEL1","","ConfigTDP Level 1 ratio and power level (R/O)",null,null],[17,"MSR_CONFIG_TDP_LEVEL2","","ConfigTDP Level 2 ratio and power level (R/O)",null,null],[17,"MSR_CONFIG_TDP_CONTROL","","ConfigTDP Control (R/W)",null,null],[17,"MSR_TURBO_ACTIVATION_RATIO","","ConfigTDP Control (R/W)",null,null],[17,"MSR_CORE_C1_RESIDENCY","","Note: C-state values are processor specific C-state code names,  unrelated to MWAIT extension C-state parameters or ACPI C- States.",null,null],[17,"MSR_LASTBRANCH_8_FROM_IP","","Last Branch Record 8 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_9_FROM_IP","","Last Branch Record 9 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_10_FROM_IP","","Last Branch Record 10 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_11_FROM_IP","","Last Branch Record 11 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_12_FROM_IP","","Last Branch Record 12 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_13_FROM_IP","","Last Branch Record 13 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_14_FROM_IP","","Last Branch Record 14 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_15_FROM_IP","","Last Branch Record 15 From IP (R/W) See description of MSR_LASTBRANCH_0_FROM_IP.",null,null],[17,"MSR_LASTBRANCH_8_TO_IP","","Last Branch Record 8 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_9_TO_IP","","Last Branch Record 9 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_10_TO_IP","","Last Branch Record 10 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_11_TO_IP","","Last Branch Record 11 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_12_TO_IP","","Last Branch Record 12 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_13_TO_IP","","Last Branch Record 13 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_14_TO_IP","","Last Branch Record 14 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"MSR_LASTBRANCH_15_TO_IP","","Last Branch Record 15 To IP (R/W) See description of MSR_LASTBRANCH_0_TO_IP.",null,null],[17,"IA32_TSC_DEADLINE","","TSC Target of Local APIC s TSC Deadline Mode (R/W)  See Table 35-2",null,null],[17,"MSR_UNC_CBO_0_PERFEVTSEL0","","Uncore C-Box 0, counter 0 event select MSR",null,null],[17,"MSR_UNC_CBO_0_PERFEVTSEL1","","Uncore C-Box 0, counter 1 event select MSR",null,null],[17,"MSR_UNC_CBO_0_PER_CTR0","","Uncore C-Box 0, performance counter 0",null,null],[17,"MSR_UNC_CBO_0_PER_CTR1","","Uncore C-Box 0, performance counter 1",null,null],[17,"MSR_UNC_CBO_1_PERFEVTSEL0","","Uncore C-Box 1, counter 0 event select MSR",null,null],[17,"MSR_UNC_CBO_1_PERFEVTSEL1","","Uncore C-Box 1, counter 1 event select MSR",null,null],[17,"MSR_UNC_CBO_1_PER_CTR0","","Uncore C-Box 1, performance counter 0",null,null],[17,"MSR_UNC_CBO_1_PER_CTR1","","Uncore C-Box 1, performance counter 1",null,null],[17,"MSR_UNC_CBO_2_PERFEVTSEL0","","Uncore C-Box 2, counter 0 event select MSR",null,null],[17,"MSR_UNC_CBO_2_PERFEVTSEL1","","Uncore C-Box 2, counter 1 event select MSR",null,null],[17,"MSR_UNC_CBO_2_PER_CTR0","","Uncore C-Box 2, performance counter 0",null,null],[17,"MSR_UNC_CBO_2_PER_CTR1","","Uncore C-Box 2, performance counter 1",null,null],[17,"MSR_UNC_CBO_3_PERFEVTSEL0","","Uncore C-Box 3, counter 0 event select MSR",null,null],[17,"MSR_UNC_CBO_3_PERFEVTSEL1","","Uncore C-Box 3, counter 1 event select MSR.",null,null],[17,"MSR_UNC_CBO_3_PER_CTR0","","Uncore C-Box 3, performance counter 0.",null,null],[17,"MSR_UNC_CBO_3_PER_CTR1","","Uncore C-Box 3, performance counter 1.",null,null],[17,"IA32_X2APIC_APICID","","x2APIC ID register (R/O) See x2APIC Specification.",null,null],[17,"IA32_X2APIC_VERSION","","If ( CPUID.01H:ECX.[bit 21]  = 1 )",null,null],[17,"IA32_X2APIC_TPR","","x2APIC Task Priority register (R/W)",null,null],[17,"IA32_X2APIC_PPR","","x2APIC Processor Priority register (R/O)",null,null],[17,"IA32_X2APIC_EOI","","If ( CPUID.01H:ECX.[bit 21]  = 1 )",null,null],[17,"IA32_X2APIC_LDR","","x2APIC Logical Destination register (R/O)",null,null],[17,"IA32_X2APIC_SIVR","","x2APIC Spurious Interrupt Vector register (R/W)",null,null],[17,"IA32_X2APIC_ISR0","","x2APIC In-Service register bits [31:0] (R/O)",null,null],[17,"IA32_X2APIC_ISR1","","x2APIC In-Service register bits [63:32] (R/O)",null,null],[17,"IA32_X2APIC_ISR2","","x2APIC In-Service register bits [95:64] (R/O)",null,null],[17,"IA32_X2APIC_ISR3","","x2APIC In-Service register bits [127:96] (R/O)",null,null],[17,"IA32_X2APIC_ISR4","","x2APIC In-Service register bits [159:128] (R/O)",null,null],[17,"IA32_X2APIC_ISR5","","x2APIC In-Service register bits [191:160] (R/O)",null,null],[17,"IA32_X2APIC_ISR6","","x2APIC In-Service register bits [223:192] (R/O)",null,null],[17,"IA32_X2APIC_ISR7","","x2APIC In-Service register bits [255:224] (R/O)",null,null],[17,"IA32_X2APIC_TMR0","","x2APIC Trigger Mode register bits [31:0] (R/O)",null,null],[17,"IA32_X2APIC_TMR1","","x2APIC Trigger Mode register bits [63:32] (R/O)",null,null],[17,"IA32_X2APIC_TMR2","","x2APIC Trigger Mode register bits [95:64] (R/O)",null,null],[17,"IA32_X2APIC_TMR3","","x2APIC Trigger Mode register bits [127:96] (R/O)",null,null],[17,"IA32_X2APIC_TMR4","","x2APIC Trigger Mode register bits [159:128] (R/O)",null,null],[17,"IA32_X2APIC_TMR5","","x2APIC Trigger Mode register bits [191:160] (R/O)",null,null],[17,"IA32_X2APIC_TMR6","","x2APIC Trigger Mode register bits [223:192] (R/O)",null,null],[17,"IA32_X2APIC_TMR7","","x2APIC Trigger Mode register bits [255:224] (R/O)",null,null],[17,"IA32_X2APIC_IRR0","","x2APIC Interrupt Request register bits [31:0] (R/O)",null,null],[17,"IA32_X2APIC_IRR1","","x2APIC Interrupt Request register bits [63:32] (R/O)",null,null],[17,"IA32_X2APIC_IRR2","","x2APIC Interrupt Request register bits [95:64] (R/O)",null,null],[17,"IA32_X2APIC_IRR3","","x2APIC Interrupt Request register bits [127:96] (R/O)",null,null],[17,"IA32_X2APIC_IRR4","","x2APIC Interrupt Request register bits [159:128] (R/O)",null,null],[17,"IA32_X2APIC_IRR5","","x2APIC Interrupt Request register bits [191:160] (R/O)",null,null],[17,"IA32_X2APIC_IRR6","","x2APIC Interrupt Request register bits [223:192] (R/O)",null,null],[17,"IA32_X2APIC_IRR7","","x2APIC Interrupt Request register bits [255:224] (R/O)",null,null],[17,"IA32_X2APIC_ESR","","If ( CPUID.01H:ECX.[bit 21]  = 1 )",null,null],[17,"IA32_X2APIC_LVT_CMCI","","x2APIC LVT Corrected Machine Check Interrupt register (R/W)",null,null],[17,"IA32_X2APIC_ICR","","x2APIC Interrupt Command register (R/W)",null,null],[17,"IA32_X2APIC_LVT_TIMER","","x2APIC LVT Timer Interrupt register (R/W)",null,null],[17,"IA32_X2APIC_LVT_THERMAL","","x2APIC LVT Thermal Sensor Interrupt register (R/W)",null,null],[17,"IA32_X2APIC_LVT_PMI","","x2APIC LVT Performance Monitor register (R/W)",null,null],[17,"IA32_X2APIC_LVT_LINT0","","If ( CPUID.01H:ECX.[bit 21]  = 1 )",null,null],[17,"IA32_X2APIC_LVT_LINT1","","If ( CPUID.01H:ECX.[bit 21]  = 1 )",null,null],[17,"IA32_X2APIC_LVT_ERROR","","If ( CPUID.01H:ECX.[bit 21]  = 1 )",null,null],[17,"IA32_X2APIC_INIT_COUNT","","x2APIC Initial Count register (R/W)",null,null],[17,"IA32_X2APIC_CUR_COUNT","","x2APIC Current Count register (R/O)",null,null],[17,"IA32_X2APIC_DIV_CONF","","x2APIC Divide Configuration register (R/W)",null,null],[17,"IA32_X2APIC_SELF_IPI","","If ( CPUID.01H:ECX.[bit 21]  = 1 )",null,null],[17,"MSR_U_PMON_GLOBAL_CTRL","","Uncore U-box perfmon global control MSR.",null,null],[17,"MSR_U_PMON_GLOBAL_STATUS","","Uncore U-box perfmon global status MSR.",null,null],[17,"MSR_U_PMON_GLOBAL_OVF_CTRL","","Uncore U-box perfmon global overflow control MSR.",null,null],[17,"MSR_U_PMON_EVNT_SEL","","Uncore U-box perfmon event select MSR.",null,null],[17,"MSR_U_PMON_CTR","","Uncore U-box perfmon counter MSR.",null,null],[17,"MSR_B0_PMON_BOX_CTRL","","Uncore B-box 0 perfmon local box control MSR.",null,null],[17,"MSR_B0_PMON_BOX_STATUS","","Uncore B-box 0 perfmon local box status MSR.",null,null],[17,"MSR_B0_PMON_BOX_OVF_CTRL","","Uncore B-box 0 perfmon local box overflow control MSR.",null,null],[17,"MSR_B0_PMON_EVNT_SEL0","","Uncore B-box 0 perfmon event select MSR.",null,null],[17,"MSR_B0_PMON_CTR0","","Uncore B-box 0 perfmon counter MSR.",null,null],[17,"MSR_B0_PMON_EVNT_SEL1","","Uncore B-box 0 perfmon event select MSR.",null,null],[17,"MSR_B0_PMON_CTR1","","Uncore B-box 0 perfmon counter MSR.",null,null],[17,"MSR_B0_PMON_EVNT_SEL2","","Uncore B-box 0 perfmon event select MSR.",null,null],[17,"MSR_B0_PMON_CTR2","","Uncore B-box 0 perfmon counter MSR.",null,null],[17,"MSR_B0_PMON_EVNT_SEL3","","Uncore B-box 0 perfmon event select MSR.",null,null],[17,"MSR_B0_PMON_CTR3","","Uncore B-box 0 perfmon counter MSR.",null,null],[17,"MSR_S0_PMON_BOX_CTRL","","Uncore S-box 0 perfmon local box control MSR.",null,null],[17,"MSR_S0_PMON_BOX_STATUS","","Uncore S-box 0 perfmon local box status MSR.",null,null],[17,"MSR_S0_PMON_BOX_OVF_CTRL","","Uncore S-box 0 perfmon local box overflow control MSR.",null,null],[17,"MSR_S0_PMON_EVNT_SEL0","","Uncore S-box 0 perfmon event select MSR.",null,null],[17,"MSR_S0_PMON_CTR0","","Uncore S-box 0 perfmon counter MSR.",null,null],[17,"MSR_S0_PMON_EVNT_SEL1","","Uncore S-box 0 perfmon event select MSR.",null,null],[17,"MSR_S0_PMON_CTR1","","Uncore S-box 0 perfmon counter MSR.",null,null],[17,"MSR_S0_PMON_EVNT_SEL2","","Uncore S-box 0 perfmon event select MSR.",null,null],[17,"MSR_S0_PMON_CTR2","","Uncore S-box 0 perfmon counter MSR.",null,null],[17,"MSR_S0_PMON_EVNT_SEL3","","Uncore S-box 0 perfmon event select MSR.",null,null],[17,"MSR_S0_PMON_CTR3","","Uncore S-box 0 perfmon counter MSR.",null,null],[17,"MSR_B1_PMON_BOX_CTRL","","Uncore B-box 1 perfmon local box control MSR.",null,null],[17,"MSR_B1_PMON_BOX_STATUS","","Uncore B-box 1 perfmon local box status MSR.",null,null],[17,"MSR_B1_PMON_BOX_OVF_CTRL","","Uncore B-box 1 perfmon local box overflow control MSR.",null,null],[17,"MSR_B1_PMON_EVNT_SEL0","","Uncore B-box 1 perfmon event select MSR.",null,null],[17,"MSR_B1_PMON_CTR0","","Uncore B-box 1 perfmon counter MSR.",null,null],[17,"MSR_B1_PMON_EVNT_SEL1","","Uncore B-box 1 perfmon event select MSR.",null,null],[17,"MSR_B1_PMON_CTR1","","Uncore B-box 1 perfmon counter MSR.",null,null],[17,"MSR_B1_PMON_EVNT_SEL2","","Uncore B-box 1 perfmon event select MSR.",null,null],[17,"MSR_B1_PMON_CTR2","","Uncore B-box 1 perfmon counter MSR.",null,null],[17,"MSR_B1_PMON_EVNT_SEL3","","Uncore B-box 1vperfmon event select MSR.",null,null],[17,"MSR_B1_PMON_CTR3","","Uncore B-box 1 perfmon counter MSR.",null,null],[17,"MSR_W_PMON_BOX_CTRL","","Uncore W-box perfmon local box control MSR.",null,null],[17,"MSR_W_PMON_BOX_STATUS","","Uncore W-box perfmon local box status MSR.",null,null],[17,"MSR_W_PMON_BOX_OVF_CTRL","","Uncore W-box perfmon local box overflow control MSR.",null,null],[17,"IA32_QM_EVTSEL","","If ( CPUID.(EAX=07H,  ECX=0):EBX.[bit 12] = 1 )",null,null],[17,"IA32_QM_CTR","","If ( CPUID.(EAX=07H,  ECX=0):EBX.[bit 12] = 1 )",null,null],[17,"IA32_PQR_ASSOC","","If ( CPUID.(EAX=07H,  ECX=0):EBX.[bit 12] = 1 )",null,null],[17,"MSR_W_PMON_EVNT_SEL0","","Uncore W-box perfmon event select MSR.",null,null],[17,"MSR_W_PMON_CTR0","","Uncore W-box perfmon counter MSR.",null,null],[17,"MSR_W_PMON_EVNT_SEL1","","Uncore W-box perfmon event select MSR.",null,null],[17,"MSR_W_PMON_CTR1","","Uncore W-box perfmon counter MSR.",null,null],[17,"MSR_W_PMON_EVNT_SEL2","","Uncore W-box perfmon event select MSR.",null,null],[17,"MSR_W_PMON_CTR2","","Uncore W-box perfmon counter MSR.",null,null],[17,"MSR_W_PMON_EVNT_SEL3","","Uncore W-box perfmon event select MSR.",null,null],[17,"MSR_W_PMON_CTR3","","Uncore W-box perfmon counter MSR.",null,null],[17,"MSR_M0_PMON_BOX_CTRL","","Uncore M-box 0 perfmon local box control MSR.",null,null],[17,"MSR_M0_PMON_BOX_STATUS","","Uncore M-box 0 perfmon local box status MSR.",null,null],[17,"MSR_M0_PMON_BOX_OVF_CTRL","","Uncore M-box 0 perfmon local box overflow control MSR.",null,null],[17,"MSR_M0_PMON_TIMESTAMP","","Uncore M-box 0 perfmon time stamp unit select MSR.",null,null],[17,"MSR_M0_PMON_DSP","","Uncore M-box 0 perfmon DSP unit select MSR.",null,null],[17,"MSR_M0_PMON_ISS","","Uncore M-box 0 perfmon ISS unit select MSR.",null,null],[17,"MSR_M0_PMON_MAP","","Uncore M-box 0 perfmon MAP unit select MSR.",null,null],[17,"MSR_M0_PMON_MSC_THR","","Uncore M-box 0 perfmon MIC THR select MSR.",null,null],[17,"MSR_M0_PMON_PGT","","Uncore M-box 0 perfmon PGT unit select MSR.",null,null],[17,"MSR_M0_PMON_PLD","","Uncore M-box 0 perfmon PLD unit select MSR.",null,null],[17,"MSR_M0_PMON_ZDP","","Uncore M-box 0 perfmon ZDP unit select MSR.",null,null],[17,"MSR_M0_PMON_EVNT_SEL0","","Uncore M-box 0 perfmon event select MSR.",null,null],[17,"MSR_M0_PMON_CTR0","","Uncore M-box 0 perfmon counter MSR.",null,null],[17,"MSR_M0_PMON_EVNT_SEL1","","Uncore M-box 0 perfmon event select MSR.",null,null],[17,"MSR_M0_PMON_CTR1","","Uncore M-box 0 perfmon counter MSR.",null,null],[17,"MSR_M0_PMON_EVNT_SEL2","","Uncore M-box 0 perfmon event select MSR.",null,null],[17,"MSR_M0_PMON_CTR2","","Uncore M-box 0 perfmon counter MSR.",null,null],[17,"MSR_M0_PMON_EVNT_SEL3","","Uncore M-box 0 perfmon event select MSR.",null,null],[17,"MSR_M0_PMON_CTR3","","Uncore M-box 0 perfmon counter MSR.",null,null],[17,"MSR_M0_PMON_EVNT_SEL4","","Uncore M-box 0 perfmon event select MSR.",null,null],[17,"MSR_M0_PMON_CTR4","","Uncore M-box 0 perfmon counter MSR.",null,null],[17,"MSR_M0_PMON_EVNT_SEL5","","Uncore M-box 0 perfmon event select MSR.",null,null],[17,"MSR_M0_PMON_CTR5","","Uncore M-box 0 perfmon counter MSR.",null,null],[17,"MSR_S1_PMON_BOX_CTRL","","Uncore S-box 1 perfmon local box control MSR.",null,null],[17,"MSR_S1_PMON_BOX_STATUS","","Uncore S-box 1 perfmon local box status MSR.",null,null],[17,"MSR_S1_PMON_BOX_OVF_CTRL","","Uncore S-box 1 perfmon local box overflow control MSR.",null,null],[17,"MSR_S1_PMON_EVNT_SEL0","","Uncore S-box 1 perfmon event select MSR.",null,null],[17,"MSR_S1_PMON_CTR0","","Uncore S-box 1 perfmon counter MSR.",null,null],[17,"MSR_S1_PMON_EVNT_SEL1","","Uncore S-box 1 perfmon event select MSR.",null,null],[17,"MSR_S1_PMON_CTR1","","Uncore S-box 1 perfmon counter MSR.",null,null],[17,"MSR_S1_PMON_EVNT_SEL2","","Uncore S-box 1 perfmon event select MSR.",null,null],[17,"MSR_S1_PMON_CTR2","","Uncore S-box 1 perfmon counter MSR.",null,null],[17,"MSR_S1_PMON_EVNT_SEL3","","Uncore S-box 1 perfmon event select MSR.",null,null],[17,"MSR_S1_PMON_CTR3","","Uncore S-box 1 perfmon counter MSR.",null,null],[17,"MSR_M1_PMON_BOX_CTRL","","Uncore M-box 1 perfmon local box control MSR.",null,null],[17,"MSR_M1_PMON_BOX_STATUS","","Uncore M-box 1 perfmon local box status MSR.",null,null],[17,"MSR_M1_PMON_BOX_OVF_CTRL","","Uncore M-box 1 perfmon local box overflow control MSR.",null,null],[17,"MSR_M1_PMON_TIMESTAMP","","Uncore M-box 1 perfmon time stamp unit select MSR.",null,null],[17,"MSR_M1_PMON_DSP","","Uncore M-box 1 perfmon DSP unit select MSR.",null,null],[17,"MSR_M1_PMON_ISS","","Uncore M-box 1 perfmon ISS unit select MSR.",null,null],[17,"MSR_M1_PMON_MAP","","Uncore M-box 1 perfmon MAP unit select MSR.",null,null],[17,"MSR_M1_PMON_MSC_THR","","Uncore M-box 1 perfmon MIC THR select MSR.",null,null],[17,"MSR_M1_PMON_PGT","","Uncore M-box 1 perfmon PGT unit select MSR.",null,null],[17,"MSR_M1_PMON_PLD","","Uncore M-box 1 perfmon PLD unit select MSR.",null,null],[17,"MSR_M1_PMON_ZDP","","Uncore M-box 1 perfmon ZDP unit select MSR.",null,null],[17,"MSR_M1_PMON_EVNT_SEL0","","Uncore M-box 1 perfmon event select MSR.",null,null],[17,"MSR_M1_PMON_CTR0","","Uncore M-box 1 perfmon counter MSR.",null,null],[17,"MSR_M1_PMON_EVNT_SEL1","","Uncore M-box 1 perfmon event select MSR.",null,null],[17,"MSR_M1_PMON_CTR1","","Uncore M-box 1 perfmon counter MSR.",null,null],[17,"MSR_M1_PMON_EVNT_SEL2","","Uncore M-box 1 perfmon event select MSR.",null,null],[17,"MSR_M1_PMON_CTR2","","Uncore M-box 1 perfmon counter MSR.",null,null],[17,"MSR_M1_PMON_EVNT_SEL3","","Uncore M-box 1 perfmon event select MSR.",null,null],[17,"MSR_M1_PMON_CTR3","","Uncore M-box 1 perfmon counter MSR.",null,null],[17,"MSR_M1_PMON_EVNT_SEL4","","Uncore M-box 1 perfmon event select MSR.",null,null],[17,"MSR_M1_PMON_CTR4","","Uncore M-box 1 perfmon counter MSR.",null,null],[17,"MSR_M1_PMON_EVNT_SEL5","","Uncore M-box 1 perfmon event select MSR.",null,null],[17,"MSR_M1_PMON_CTR5","","Uncore M-box 1 perfmon counter MSR.",null,null],[17,"MSR_C0_PMON_BOX_CTRL","","Uncore C-box 0 perfmon local box control MSR.",null,null],[17,"MSR_C0_PMON_BOX_STATUS","","Uncore C-box 0 perfmon local box status MSR.",null,null],[17,"MSR_C0_PMON_BOX_OVF_CTRL","","Uncore C-box 0 perfmon local box overflow control MSR.",null,null],[17,"MSR_C0_PMON_EVNT_SEL0","","Uncore C-box 0 perfmon event select MSR.",null,null],[17,"MSR_C0_PMON_CTR0","","Uncore C-box 0 perfmon counter MSR.",null,null],[17,"MSR_C0_PMON_EVNT_SEL1","","Uncore C-box 0 perfmon event select MSR.",null,null],[17,"MSR_C0_PMON_CTR1","","Uncore C-box 0 perfmon counter MSR.",null,null],[17,"MSR_C0_PMON_EVNT_SEL2","","Uncore C-box 0 perfmon event select MSR.",null,null],[17,"MSR_C0_PMON_CTR2","","Uncore C-box 0 perfmon counter MSR.",null,null],[17,"MSR_C0_PMON_EVNT_SEL3","","Uncore C-box 0 perfmon event select MSR.",null,null],[17,"MSR_C0_PMON_CTR3","","Uncore C-box 0 perfmon counter MSR.",null,null],[17,"MSR_C0_PMON_EVNT_SEL4","","Uncore C-box 0 perfmon event select MSR.",null,null],[17,"MSR_C0_PMON_CTR4","","Uncore C-box 0 perfmon counter MSR.",null,null],[17,"MSR_C0_PMON_EVNT_SEL5","","Uncore C-box 0 perfmon event select MSR.",null,null],[17,"MSR_C0_PMON_CTR5","","Uncore C-box 0 perfmon counter MSR.",null,null],[17,"MSR_C4_PMON_BOX_CTRL","","Uncore C-box 4 perfmon local box control MSR.",null,null],[17,"MSR_C4_PMON_BOX_STATUS","","Uncore C-box 4 perfmon local box status MSR.",null,null],[17,"MSR_C4_PMON_BOX_OVF_CTRL","","Uncore C-box 4 perfmon local box overflow control MSR.",null,null],[17,"MSR_C4_PMON_EVNT_SEL0","","Uncore C-box 4 perfmon event select MSR.",null,null],[17,"MSR_C4_PMON_CTR0","","Uncore C-box 4 perfmon counter MSR.",null,null],[17,"MSR_C4_PMON_EVNT_SEL1","","Uncore C-box 4 perfmon event select MSR.",null,null],[17,"MSR_C4_PMON_CTR1","","Uncore C-box 4 perfmon counter MSR.",null,null],[17,"MSR_C4_PMON_EVNT_SEL2","","Uncore C-box 4 perfmon event select MSR.",null,null],[17,"MSR_C4_PMON_CTR2","","Uncore C-box 4 perfmon counter MSR.",null,null],[17,"MSR_C4_PMON_EVNT_SEL3","","Uncore C-box 4 perfmon event select MSR.",null,null],[17,"MSR_C4_PMON_CTR3","","Uncore C-box 4 perfmon counter MSR.",null,null],[17,"MSR_C4_PMON_EVNT_SEL4","","Uncore C-box 4 perfmon event select MSR.",null,null],[17,"MSR_C4_PMON_CTR4","","Uncore C-box 4 perfmon counter MSR.",null,null],[17,"MSR_C4_PMON_EVNT_SEL5","","Uncore C-box 4 perfmon event select MSR.",null,null],[17,"MSR_C4_PMON_CTR5","","Uncore C-box 4 perfmon counter MSR.",null,null],[17,"MSR_C2_PMON_BOX_CTRL","","Uncore C-box 2 perfmon local box control MSR.",null,null],[17,"MSR_C2_PMON_BOX_STATUS","","Uncore C-box 2 perfmon local box status MSR.",null,null],[17,"MSR_C2_PMON_BOX_OVF_CTRL","","Uncore C-box 2 perfmon local box overflow control MSR.",null,null],[17,"MSR_C2_PMON_EVNT_SEL0","","Uncore C-box 2 perfmon event select MSR.",null,null],[17,"MSR_C2_PMON_CTR0","","Uncore C-box 2 perfmon counter MSR.",null,null],[17,"MSR_C2_PMON_EVNT_SEL1","","Uncore C-box 2 perfmon event select MSR.",null,null],[17,"MSR_C2_PMON_CTR1","","Uncore C-box 2 perfmon counter MSR.",null,null],[17,"MSR_C2_PMON_EVNT_SEL2","","Uncore C-box 2 perfmon event select MSR.",null,null],[17,"MSR_C2_PMON_CTR2","","Uncore C-box 2 perfmon counter MSR.",null,null],[17,"MSR_C2_PMON_EVNT_SEL3","","Uncore C-box 2 perfmon event select MSR.",null,null],[17,"MSR_C2_PMON_CTR3","","Uncore C-box 2 perfmon counter MSR.",null,null],[17,"MSR_C2_PMON_EVNT_SEL4","","Uncore C-box 2 perfmon event select MSR.",null,null],[17,"MSR_C2_PMON_CTR4","","Uncore C-box 2 perfmon counter MSR.",null,null],[17,"MSR_C2_PMON_EVNT_SEL5","","Uncore C-box 2 perfmon event select MSR.",null,null],[17,"MSR_C2_PMON_CTR5","","Uncore C-box 2 perfmon counter MSR.",null,null],[17,"MSR_C6_PMON_BOX_CTRL","","Uncore C-box 6 perfmon local box control MSR.",null,null],[17,"MSR_C6_PMON_BOX_STATUS","","Uncore C-box 6 perfmon local box status MSR.",null,null],[17,"MSR_C6_PMON_BOX_OVF_CTRL","","Uncore C-box 6 perfmon local box overflow control MSR.",null,null],[17,"MSR_C6_PMON_EVNT_SEL0","","Uncore C-box 6 perfmon event select MSR.",null,null],[17,"MSR_C6_PMON_CTR0","","Uncore C-box 6 perfmon counter MSR.",null,null],[17,"MSR_C6_PMON_EVNT_SEL1","","Uncore C-box 6 perfmon event select MSR.",null,null],[17,"MSR_C6_PMON_CTR1","","Uncore C-box 6 perfmon counter MSR.",null,null],[17,"MSR_C6_PMON_EVNT_SEL2","","Uncore C-box 6 perfmon event select MSR.",null,null],[17,"MSR_C6_PMON_CTR2","","Uncore C-box 6 perfmon counter MSR.",null,null],[17,"MSR_C6_PMON_EVNT_SEL3","","Uncore C-box 6 perfmon event select MSR.",null,null],[17,"MSR_C6_PMON_CTR3","","Uncore C-box 6 perfmon counter MSR.",null,null],[17,"MSR_C6_PMON_EVNT_SEL4","","Uncore C-box 6 perfmon event select MSR.",null,null],[17,"MSR_C6_PMON_CTR4","","Uncore C-box 6 perfmon counter MSR.",null,null],[17,"MSR_C6_PMON_EVNT_SEL5","","Uncore C-box 6 perfmon event select MSR.",null,null],[17,"MSR_C6_PMON_CTR5","","Uncore C-box 6 perfmon counter MSR.",null,null],[17,"MSR_C1_PMON_BOX_CTRL","","Uncore C-box 1 perfmon local box control MSR.",null,null],[17,"MSR_C1_PMON_BOX_STATUS","","Uncore C-box 1 perfmon local box status MSR.",null,null],[17,"MSR_C1_PMON_BOX_OVF_CTRL","","Uncore C-box 1 perfmon local box overflow control MSR.",null,null],[17,"MSR_C1_PMON_EVNT_SEL0","","Uncore C-box 1 perfmon event select MSR.",null,null],[17,"MSR_C1_PMON_CTR0","","Uncore C-box 1 perfmon counter MSR.",null,null],[17,"MSR_C1_PMON_EVNT_SEL1","","Uncore C-box 1 perfmon event select MSR.",null,null],[17,"MSR_C1_PMON_CTR1","","Uncore C-box 1 perfmon counter MSR.",null,null],[17,"MSR_C1_PMON_EVNT_SEL2","","Uncore C-box 1 perfmon event select MSR.",null,null],[17,"MSR_C1_PMON_CTR2","","Uncore C-box 1 perfmon counter MSR.",null,null],[17,"MSR_C1_PMON_EVNT_SEL3","","Uncore C-box 1 perfmon event select MSR.",null,null],[17,"MSR_C1_PMON_CTR3","","Uncore C-box 1 perfmon counter MSR.",null,null],[17,"MSR_C1_PMON_EVNT_SEL4","","Uncore C-box 1 perfmon event select MSR.",null,null],[17,"MSR_C1_PMON_CTR4","","Uncore C-box 1 perfmon counter MSR.",null,null],[17,"MSR_C1_PMON_EVNT_SEL5","","Uncore C-box 1 perfmon event select MSR.",null,null],[17,"MSR_C1_PMON_CTR5","","Uncore C-box 1 perfmon counter MSR.",null,null],[17,"MSR_C5_PMON_BOX_CTRL","","Uncore C-box 5 perfmon local box control MSR.",null,null],[17,"MSR_C5_PMON_BOX_STATUS","","Uncore C-box 5 perfmon local box status MSR.",null,null],[17,"MSR_C5_PMON_BOX_OVF_CTRL","","Uncore C-box 5 perfmon local box overflow control MSR.",null,null],[17,"MSR_C5_PMON_EVNT_SEL0","","Uncore C-box 5 perfmon event select MSR.",null,null],[17,"MSR_C5_PMON_CTR0","","Uncore C-box 5 perfmon counter MSR.",null,null],[17,"MSR_C5_PMON_EVNT_SEL1","","Uncore C-box 5 perfmon event select MSR.",null,null],[17,"MSR_C5_PMON_CTR1","","Uncore C-box 5 perfmon counter MSR.",null,null],[17,"MSR_C5_PMON_EVNT_SEL2","","Uncore C-box 5 perfmon event select MSR.",null,null],[17,"MSR_C5_PMON_CTR2","","Uncore C-box 5 perfmon counter MSR.",null,null],[17,"MSR_C5_PMON_EVNT_SEL3","","Uncore C-box 5 perfmon event select MSR.",null,null],[17,"MSR_C5_PMON_CTR3","","Uncore C-box 5 perfmon counter MSR.",null,null],[17,"MSR_C5_PMON_EVNT_SEL4","","Uncore C-box 5 perfmon event select MSR.",null,null],[17,"MSR_C5_PMON_CTR4","","Uncore C-box 5 perfmon counter MSR.",null,null],[17,"MSR_C5_PMON_EVNT_SEL5","","Uncore C-box 5 perfmon event select MSR.",null,null],[17,"MSR_C5_PMON_CTR5","","Uncore C-box 5 perfmon counter MSR.",null,null],[17,"MSR_C3_PMON_BOX_CTRL","","Uncore C-box 3 perfmon local box control MSR.",null,null],[17,"MSR_C3_PMON_BOX_STATUS","","Uncore C-box 3 perfmon local box status MSR.",null,null],[17,"MSR_C3_PMON_BOX_OVF_CTRL","","Uncore C-box 3 perfmon local box overflow control MSR.",null,null],[17,"MSR_C3_PMON_EVNT_SEL0","","Uncore C-box 3 perfmon event select MSR.",null,null],[17,"MSR_C3_PMON_CTR0","","Uncore C-box 3 perfmon counter MSR.",null,null],[17,"MSR_C3_PMON_EVNT_SEL1","","Uncore C-box 3 perfmon event select MSR.",null,null],[17,"MSR_C3_PMON_CTR1","","Uncore C-box 3 perfmon counter MSR.",null,null],[17,"MSR_C3_PMON_EVNT_SEL2","","Uncore C-box 3 perfmon event select MSR.",null,null],[17,"MSR_C3_PMON_CTR2","","Uncore C-box 3 perfmon counter MSR.",null,null],[17,"MSR_C3_PMON_EVNT_SEL3","","Uncore C-box 3 perfmon event select MSR.",null,null],[17,"MSR_C3_PMON_CTR3","","Uncore C-box 3 perfmon counter MSR.",null,null],[17,"MSR_C3_PMON_EVNT_SEL4","","Uncore C-box 3 perfmon event select MSR.",null,null],[17,"MSR_C3_PMON_CTR4","","Uncore C-box 3 perfmon counter MSR.",null,null],[17,"MSR_C3_PMON_EVNT_SEL5","","Uncore C-box 3 perfmon event select MSR.",null,null],[17,"MSR_C3_PMON_CTR5","","Uncore C-box 3 perfmon counter MSR.",null,null],[17,"MSR_C7_PMON_BOX_CTRL","","Uncore C-box 7 perfmon local box control MSR.",null,null],[17,"MSR_C7_PMON_BOX_STATUS","","Uncore C-box 7 perfmon local box status MSR.",null,null],[17,"MSR_C7_PMON_BOX_OVF_CTRL","","Uncore C-box 7 perfmon local box overflow control MSR.",null,null],[17,"MSR_C7_PMON_EVNT_SEL0","","Uncore C-box 7 perfmon event select MSR.",null,null],[17,"MSR_C7_PMON_CTR0","","Uncore C-box 7 perfmon counter MSR.",null,null],[17,"MSR_C7_PMON_EVNT_SEL1","","Uncore C-box 7 perfmon event select MSR.",null,null],[17,"MSR_C7_PMON_CTR1","","Uncore C-box 7 perfmon counter MSR.",null,null],[17,"MSR_C7_PMON_EVNT_SEL2","","Uncore C-box 7 perfmon event select MSR.",null,null],[17,"MSR_C7_PMON_CTR2","","Uncore C-box 7 perfmon counter MSR.",null,null],[17,"MSR_C7_PMON_EVNT_SEL3","","Uncore C-box 7 perfmon event select MSR.",null,null],[17,"MSR_C7_PMON_CTR3","","Uncore C-box 7 perfmon counter MSR.",null,null],[17,"MSR_C7_PMON_EVNT_SEL4","","Uncore C-box 7 perfmon event select MSR.",null,null],[17,"MSR_C7_PMON_CTR4","","Uncore C-box 7 perfmon counter MSR.",null,null],[17,"MSR_C7_PMON_EVNT_SEL5","","Uncore C-box 7 perfmon event select MSR.",null,null],[17,"MSR_C7_PMON_CTR5","","Uncore C-box 7 perfmon counter MSR.",null,null],[17,"MSR_R0_PMON_BOX_CTRL","","Uncore R-box 0 perfmon local box control MSR.",null,null],[17,"MSR_R0_PMON_BOX_STATUS","","Uncore R-box 0 perfmon local box status MSR.",null,null],[17,"MSR_R0_PMON_BOX_OVF_CTRL","","Uncore R-box 0 perfmon local box overflow control MSR.",null,null],[17,"MSR_R0_PMON_IPERF0_P0","","Uncore R-box 0 perfmon IPERF0 unit Port 0 select MSR.",null,null],[17,"MSR_R0_PMON_IPERF0_P1","","Uncore R-box 0 perfmon IPERF0 unit Port 1 select MSR.",null,null],[17,"MSR_R0_PMON_IPERF0_P2","","Uncore R-box 0 perfmon IPERF0 unit Port 2 select MSR.",null,null],[17,"MSR_R0_PMON_IPERF0_P3","","Uncore R-box 0 perfmon IPERF0 unit Port 3 select MSR.",null,null],[17,"MSR_R0_PMON_IPERF0_P4","","Uncore R-box 0 perfmon IPERF0 unit Port 4 select MSR.",null,null],[17,"MSR_R0_PMON_IPERF0_P5","","Uncore R-box 0 perfmon IPERF0 unit Port 5 select MSR.",null,null],[17,"MSR_R0_PMON_IPERF0_P6","","Uncore R-box 0 perfmon IPERF0 unit Port 6 select MSR.",null,null],[17,"MSR_R0_PMON_IPERF0_P7","","Uncore R-box 0 perfmon IPERF0 unit Port 7 select MSR.",null,null],[17,"MSR_R0_PMON_QLX_P0","","Uncore R-box 0 perfmon QLX unit Port 0 select MSR.",null,null],[17,"MSR_R0_PMON_QLX_P1","","Uncore R-box 0 perfmon QLX unit Port 1 select MSR.",null,null],[17,"MSR_R0_PMON_QLX_P2","","Uncore R-box 0 perfmon QLX unit Port 2 select MSR.",null,null],[17,"MSR_R0_PMON_QLX_P3","","Uncore R-box 0 perfmon QLX unit Port 3 select MSR.",null,null],[17,"MSR_R0_PMON_EVNT_SEL0","","Uncore R-box 0 perfmon event select MSR.",null,null],[17,"MSR_R0_PMON_CTR0","","Uncore R-box 0 perfmon counter MSR.",null,null],[17,"MSR_R0_PMON_EVNT_SEL1","","Uncore R-box 0 perfmon event select MSR.",null,null],[17,"MSR_R0_PMON_CTR1","","Uncore R-box 0 perfmon counter MSR.",null,null],[17,"MSR_R0_PMON_EVNT_SEL2","","Uncore R-box 0 perfmon event select MSR.",null,null],[17,"MSR_R0_PMON_CTR2","","Uncore R-box 0 perfmon counter MSR.",null,null],[17,"MSR_R0_PMON_EVNT_SEL3","","Uncore R-box 0 perfmon event select MSR.",null,null],[17,"MSR_R0_PMON_CTR3","","Uncore R-box 0 perfmon counter MSR.",null,null],[17,"MSR_R0_PMON_EVNT_SEL4","","Uncore R-box 0 perfmon event select MSR.",null,null],[17,"MSR_R0_PMON_CTR4","","Uncore R-box 0 perfmon counter MSR.",null,null],[17,"MSR_R0_PMON_EVNT_SEL5","","Uncore R-box 0 perfmon event select MSR.",null,null],[17,"MSR_R0_PMON_CTR5","","Uncore R-box 0 perfmon counter MSR.",null,null],[17,"MSR_R0_PMON_EVNT_SEL6","","Uncore R-box 0 perfmon event select MSR.",null,null],[17,"MSR_R0_PMON_CTR6","","Uncore R-box 0 perfmon counter MSR.",null,null],[17,"MSR_R0_PMON_EVNT_SEL7","","Uncore R-box 0 perfmon event select MSR.",null,null],[17,"MSR_R0_PMON_CTR7","","Uncore R-box 0 perfmon counter MSR.",null,null],[17,"MSR_R1_PMON_BOX_CTRL","","Uncore R-box 1 perfmon local box control MSR.",null,null],[17,"MSR_R1_PMON_BOX_STATUS","","Uncore R-box 1 perfmon local box status MSR.",null,null],[17,"MSR_R1_PMON_BOX_OVF_CTRL","","Uncore R-box 1 perfmon local box overflow control MSR.",null,null],[17,"MSR_R1_PMON_IPERF1_P8","","Uncore R-box 1 perfmon IPERF1 unit Port 8 select MSR.",null,null],[17,"MSR_R1_PMON_IPERF1_P9","","Uncore R-box 1 perfmon IPERF1 unit Port 9 select MSR.",null,null],[17,"MSR_R1_PMON_IPERF1_P10","","Uncore R-box 1 perfmon IPERF1 unit Port 10 select MSR.",null,null],[17,"MSR_R1_PMON_IPERF1_P11","","Uncore R-box 1 perfmon IPERF1 unit Port 11 select MSR.",null,null],[17,"MSR_R1_PMON_IPERF1_P12","","Uncore R-box 1 perfmon IPERF1 unit Port 12 select MSR.",null,null],[17,"MSR_R1_PMON_IPERF1_P13","","Uncore R-box 1 perfmon IPERF1 unit Port 13 select MSR.",null,null],[17,"MSR_R1_PMON_IPERF1_P14","","Uncore R-box 1 perfmon IPERF1 unit Port 14 select MSR.",null,null],[17,"MSR_R1_PMON_IPERF1_P15","","Uncore R-box 1 perfmon IPERF1 unit Port 15 select MSR.",null,null],[17,"MSR_R1_PMON_QLX_P4","","Uncore R-box 1 perfmon QLX unit Port 4 select MSR.",null,null],[17,"MSR_R1_PMON_QLX_P5","","Uncore R-box 1 perfmon QLX unit Port 5 select MSR.",null,null],[17,"MSR_R1_PMON_QLX_P6","","Uncore R-box 1 perfmon QLX unit Port 6 select MSR.",null,null],[17,"MSR_R1_PMON_QLX_P7","","Uncore R-box 1 perfmon QLX unit Port 7 select MSR.",null,null],[17,"MSR_R1_PMON_EVNT_SEL8","","Uncore R-box 1 perfmon event select MSR.",null,null],[17,"MSR_R1_PMON_CTR8","","Uncore R-box 1 perfmon counter MSR.",null,null],[17,"MSR_R1_PMON_EVNT_SEL9","","Uncore R-box 1 perfmon event select MSR.",null,null],[17,"MSR_R1_PMON_CTR9","","Uncore R-box 1 perfmon counter MSR.",null,null],[17,"MSR_R1_PMON_EVNT_SEL10","","Uncore R-box 1 perfmon event select MSR.",null,null],[17,"MSR_R1_PMON_CTR10","","Uncore R-box 1 perfmon counter MSR.",null,null],[17,"MSR_R1_PMON_EVNT_SEL11","","Uncore R-box 1 perfmon event select MSR.",null,null],[17,"MSR_R1_PMON_CTR11","","Uncore R-box 1 perfmon counter MSR.",null,null],[17,"MSR_R1_PMON_EVNT_SEL12","","Uncore R-box 1 perfmon event select MSR.",null,null],[17,"MSR_R1_PMON_CTR12","","Uncore R-box 1 perfmon counter MSR.",null,null],[17,"MSR_R1_PMON_EVNT_SEL13","","Uncore R-box 1 perfmon event select MSR.",null,null],[17,"MSR_R1_PMON_CTR13","","Uncore R-box 1perfmon counter MSR.",null,null],[17,"MSR_R1_PMON_EVNT_SEL14","","Uncore R-box 1 perfmon event select MSR.",null,null],[17,"MSR_R1_PMON_CTR14","","Uncore R-box 1 perfmon counter MSR.",null,null],[17,"MSR_R1_PMON_EVNT_SEL15","","Uncore R-box 1 perfmon event select MSR.",null,null],[17,"MSR_R1_PMON_CTR15","","Uncore R-box 1 perfmon counter MSR.",null,null],[17,"MSR_B0_PMON_MATCH","","Uncore B-box 0 perfmon local box match MSR.",null,null],[17,"MSR_B0_PMON_MASK","","Uncore B-box 0 perfmon local box mask MSR.",null,null],[17,"MSR_S0_PMON_MATCH","","Uncore S-box 0 perfmon local box match MSR.",null,null],[17,"MSR_S0_PMON_MASK","","Uncore S-box 0 perfmon local box mask MSR.",null,null],[17,"MSR_B1_PMON_MATCH","","Uncore B-box 1 perfmon local box match MSR.",null,null],[17,"MSR_B1_PMON_MASK","","Uncore B-box 1 perfmon local box mask MSR.",null,null],[17,"MSR_M0_PMON_MM_CONFIG","","Uncore M-box 0 perfmon local box address match/mask config MSR.",null,null],[17,"MSR_M0_PMON_ADDR_MATCH","","Uncore M-box 0 perfmon local box address match MSR.",null,null],[17,"MSR_M0_PMON_ADDR_MASK","","Uncore M-box 0 perfmon local box address mask MSR.",null,null],[17,"MSR_S1_PMON_MATCH","","Uncore S-box 1 perfmon local box match MSR.",null,null],[17,"MSR_S1_PMON_MASK","","Uncore S-box 1 perfmon local box mask MSR.",null,null],[17,"MSR_M1_PMON_MM_CONFIG","","Uncore M-box 1 perfmon local box address match/mask config MSR.",null,null],[17,"MSR_M1_PMON_ADDR_MATCH","","Uncore M-box 1 perfmon local box address match MSR.",null,null],[17,"MSR_M1_PMON_ADDR_MASK","","Uncore M-box 1 perfmon local box address mask MSR.",null,null],[17,"MSR_C8_PMON_BOX_CTRL","","Uncore C-box 8 perfmon local box control MSR.",null,null],[17,"MSR_C8_PMON_BOX_STATUS","","Uncore C-box 8 perfmon local box status MSR.",null,null],[17,"MSR_C8_PMON_BOX_OVF_CTRL","","Uncore C-box 8 perfmon local box overflow control MSR.",null,null],[17,"MSR_C8_PMON_EVNT_SEL0","","Uncore C-box 8 perfmon event select MSR.",null,null],[17,"MSR_C8_PMON_CTR0","","Uncore C-box 8 perfmon counter MSR.",null,null],[17,"MSR_C8_PMON_EVNT_SEL1","","Uncore C-box 8 perfmon event select MSR.",null,null],[17,"MSR_C8_PMON_CTR1","","Uncore C-box 8 perfmon counter MSR.",null,null],[17,"MSR_C8_PMON_EVNT_SEL2","","Uncore C-box 8 perfmon event select MSR.",null,null],[17,"MSR_C8_PMON_CTR2","","Uncore C-box 8 perfmon counter MSR.",null,null],[17,"MSR_C8_PMON_EVNT_SEL3","","Uncore C-box 8 perfmon event select MSR.",null,null],[17,"MSR_C8_PMON_CTR3","","Uncore C-box 8 perfmon counter MSR.",null,null],[17,"MSR_C8_PMON_EVNT_SEL4","","Uncore C-box 8 perfmon event select MSR.",null,null],[17,"MSR_C8_PMON_CTR4","","Uncore C-box 8 perfmon counter MSR.",null,null],[17,"MSR_C8_PMON_EVNT_SEL5","","Uncore C-box 8 perfmon event select MSR.",null,null],[17,"MSR_C8_PMON_CTR5","","Uncore C-box 8 perfmon counter MSR.",null,null],[17,"MSR_C9_PMON_BOX_CTRL","","Uncore C-box 9 perfmon local box control MSR.",null,null],[17,"MSR_C9_PMON_BOX_STATUS","","Uncore C-box 9 perfmon local box status MSR.",null,null],[17,"MSR_C9_PMON_BOX_OVF_CTRL","","Uncore C-box 9 perfmon local box overflow control MSR.",null,null],[17,"MSR_C9_PMON_EVNT_SEL0","","Uncore C-box 9 perfmon event select MSR.",null,null],[17,"MSR_C9_PMON_CTR0","","Uncore C-box 9 perfmon counter MSR.",null,null],[17,"MSR_C9_PMON_EVNT_SEL1","","Uncore C-box 9 perfmon event select MSR.",null,null],[17,"MSR_C9_PMON_CTR1","","Uncore C-box 9 perfmon counter MSR.",null,null],[17,"MSR_C9_PMON_EVNT_SEL2","","Uncore C-box 9 perfmon event select MSR.",null,null],[17,"MSR_C9_PMON_CTR2","","Uncore C-box 9 perfmon counter MSR.",null,null],[17,"MSR_C9_PMON_EVNT_SEL3","","Uncore C-box 9 perfmon event select MSR.",null,null],[17,"MSR_C9_PMON_CTR3","","Uncore C-box 9 perfmon counter MSR.",null,null],[17,"MSR_C9_PMON_EVNT_SEL4","","Uncore C-box 9 perfmon event select MSR.",null,null],[17,"MSR_C9_PMON_CTR4","","Uncore C-box 9 perfmon counter MSR.",null,null],[17,"MSR_C9_PMON_EVNT_SEL5","","Uncore C-box 9 perfmon event select MSR.",null,null],[17,"MSR_C9_PMON_CTR5","","Uncore C-box 9 perfmon counter MSR.",null,null],[17,"MSR_EMON_L3_CTR_CTL0","","GBUSQ Event Control and Counter  Register (R/W) See Section 18.17, Performance  Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.",null,null],[17,"MSR_IFSB_BUSQ0","","IFSB BUSQ Event Control and Counter  Register (R/W) See Section 18.17, Performance  Monitoring on 64-bit Intel Xeon Processor  MP with Up to 8-MByte L3 Cache.",null,null],[17,"MSR_EMON_L3_CTR_CTL1","","GBUSQ Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature  06_1D) only. See Section 17.2.2",null,null],[17,"MSR_IFSB_BUSQ1","","IFSB BUSQ Event Control and Counter Register (R/W)",null,null],[17,"MSR_EMON_L3_CTR_CTL2","","GSNPQ Event Control and Counter  Register (R/W)  See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache.",null,null],[17,"MSR_IFSB_SNPQ0","","IFSB SNPQ Event Control and Counter  Register (R/W)  See Section 18.17, Performance  Monitoring on 64-bit Intel Xeon Processor  MP with Up to 8-MByte L3 Cache.",null,null],[17,"MSR_EMON_L3_CTR_CTL3","","GSNPQ Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature  06_1D) only. See Section 17.2.2",null,null],[17,"MSR_IFSB_SNPQ1","","IFSB SNPQ Event Control and Counter  Register (R/W)",null,null],[17,"MSR_EFSB_DRDY0","","EFSB DRDY Event Control and Counter Register (R/W)  See Section 18.17, Performance  Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache  for  details.",null,null],[17,"MSR_EMON_L3_CTR_CTL4","","FSB Event Control and Counter Register (R/W)  See Section 18.17, Performance  Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache  for  details.",null,null],[17,"MSR_EFSB_DRDY1","","EFSB DRDY Event Control and Counter  Register (R/W)",null,null],[17,"MSR_EMON_L3_CTR_CTL5","","FSB Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature  06_1D) only. See Section 17.2.2",null,null],[17,"MSR_EMON_L3_CTR_CTL6","","FSB Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature  06_1D) only. See Section 17.2.2",null,null],[17,"MSR_IFSB_CTL6","","IFSB Latency Event Control Register  (R/W) See Section 18.17, Performance  Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache  for  details.",null,null],[17,"MSR_EMON_L3_CTR_CTL7","","FSB Event Control/Counter Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature  06_1D) only. See Section 17.2.2",null,null],[17,"MSR_IFSB_CNTR7","","IFSB Latency Event Counter Register  (R/W)  See Section 18.17, Performance  Monitoring on 64-bit Intel Xeon Processor  MP with Up to 8-MByte L3 Cache.",null,null],[17,"MSR_EMON_L3_GL_CTL","","L3/FSB Common Control Register (R/W) Apply to Intel Xeon processor 7400 series (processor signature  06_1D) only. See Section 17.2.2",null,null],[17,"IA32_EFER","","If (  CPUID.80000001.EDX.[bit  20] or  CPUID.80000001.EDX.[bit 29])",null,null],[17,"IA32_STAR","","System Call Target Address (R/W)  See Table 35-2.",null,null],[17,"IA32_LSTAR","","IA-32e Mode System Call Target Address (R/W)  See Table 35-2.",null,null],[17,"IA32_FMASK","","System Call Flag Mask (R/W)  See Table 35-2.",null,null],[17,"IA32_FS_BASE","","Map of BASE Address of FS (R/W)  See Table 35-2.",null,null],[17,"IA32_GS_BASE","","Map of BASE Address of GS (R/W)  See Table 35-2.",null,null],[17,"IA32_KERNEL_GS_BASE","","If  CPUID.80000001.EDX.[bit  29] = 1",null,null],[17,"IA32_KERNEL_GSBASE","","Swap Target of BASE Address of GS (R/W) See Table 35-2.",null,null],[17,"IA32_TSC_AUX","","AUXILIARY TSC Signature. (R/W) See Table 35-2 and Section  17.13.2, IA32_TSC_AUX Register and RDTSCP Support.",null,null],[0,"time","x86","Functions to read time stamp counters on x86.",null,null],[5,"rdtsc","x86::time","Read the time stamp counter.",null,{"inputs":[],"output":{"name":"u64"}}],[5,"rdtscp","","Read the time stamp counter.",null,{"inputs":[],"output":{"name":"u64"}}],[0,"irq","x86","Interrupt description and set-up code.",null,null],[3,"InterruptDescription","x86::irq","x86 Exception description (see also Intel Vol. 3a Chapter 6).",null,null],[12,"vector","","",0,null],[12,"mnemonic","","",0,null],[12,"description","","",0,null],[12,"irqtype","","",0,null],[12,"source","","",0,null],[3,"IdtEntry","","A struct describing an interrupt gate.  See the Intel manual mentioned\nabove for details, specifically, the section "6.14.1 64-Bit Mode IDT"\nand "Table 3-2. System-Segment and Gate-Descriptor Types".",null,null],[12,"base_lo","","Lower 16 bits of ISR.",1,null],[12,"sel","","Segment selector.",1,null],[12,"res0","","This must always be zero.",1,null],[12,"flags","","Flags.",1,null],[12,"base_hi","","The upper 48 bits of ISR (the last 16 bits must be zero).",1,null],[12,"res1","","Must be zero.",1,null],[3,"PageFaultError","","",null,null],[5,"enable","","Enable Interrupts.",null,{"inputs":[],"output":null}],[5,"disable","","Disable Interrupts.",null,{"inputs":[],"output":null}],[7,"EXCEPTIONS","","x86 External Interrupts (1-16).",null,null],[17,"PFAULT_ERROR_P","","0: The fault was caused by a non-present page.\n1: The fault was caused by a page-level protection violation",null,null],[17,"PFAULT_ERROR_WR","","0: The access causing the fault was a read.\n1: The access causing the fault was a write.",null,null],[17,"PFAULT_ERROR_US","","0: The access causing the fault originated when the processor\nwas executing in supervisor mode.\n1: The access causing the fault originated when the processor\nwas executing in user mode.",null,null],[17,"PFAULT_ERROR_RSVD","","0: The fault was not caused by reserved bit violation.\n1: The fault was caused by reserved bits set to 1 in a page directory.",null,null],[17,"PFAULT_ERROR_ID","","0: The fault was not caused by an instruction fetch.\n1: The fault was caused by an instruction fetch.",null,null],[17,"PFAULT_ERROR_PK","","0: The fault was not by protection keys.\n1: There was a protection key violation.",null,null],[11,"fmt","","",0,null],[11,"fmt","","",0,null],[11,"clone","","",1,null],[11,"fmt","","",1,null],[11,"missing","","Create a "missing" IdtEntry.  This is a `const` function, so we can\ncall it at compile time to initialize static variables.",1,{"inputs":[],"output":{"name":"idtentry"}}],[11,"interrupt_gate","","Create a new IdtEntry pointing at `handler`, which must be a\nfunction with interrupt calling conventions.  (This must be\ncurrently defined in assembly language.)  The `gdt_code_selector`\nvalue must be the offset of code segment entry in the GDT.",1,null],[11,"hash","","",2,null],[11,"cmp","","",2,null],[11,"partial_cmp","","",2,null],[11,"lt","","",2,null],[11,"le","","",2,null],[11,"gt","","",2,null],[11,"ge","","",2,null],[11,"clone","","",2,null],[11,"eq","","",2,null],[11,"ne","","",2,null],[11,"empty","","Returns an empty set of flags.",2,{"inputs":[],"output":{"name":"pagefaulterror"}}],[11,"all","","Returns the set containing all flags.",2,{"inputs":[],"output":{"name":"pagefaulterror"}}],[11,"bits","","Returns the raw value of the flags currently stored.",2,null],[11,"from_bits","","Convert from underlying bit representation, unless that\nrepresentation contains bits that do not correspond to a flag.",2,{"inputs":[{"name":"u32"}],"output":{"name":"option"}}],[11,"from_bits_truncate","","Convert from underlying bit representation, dropping any bits\nthat do not correspond to flags.",2,{"inputs":[{"name":"u32"}],"output":{"name":"pagefaulterror"}}],[11,"is_empty","","Returns `true` if no flags are currently stored.",2,null],[11,"is_all","","Returns `true` if all flags are currently set.",2,null],[11,"intersects","","Returns `true` if there are flags common to both `self` and `other`.",2,null],[11,"contains","","Returns `true` all of the flags in `other` are contained within `self`.",2,null],[11,"insert","","Inserts the specified flags in-place.",2,null],[11,"remove","","Removes the specified flags in-place.",2,null],[11,"toggle","","Toggles the specified flags in-place.",2,null],[11,"bitor","","Returns the union of the two sets of flags.",2,null],[11,"bitxor","","Returns the left flags, but with all the right flags toggled.",2,null],[11,"bitand","","Returns the intersection between the two sets of flags.",2,null],[11,"sub","","Returns the set difference of the two sets of flags.",2,null],[11,"not","","Returns the complement of this set of flags.",2,null],[11,"fmt","","",2,null],[0,"rflags","x86","Description of RFlag values that store the results of operations and the state of the processor.",null,null],[3,"RFlags","x86::rflags","",null,null],[17,"RFLAGS_ID","","ID Flag (ID)",null,null],[17,"RFLAGS_VIP","","Virtual Interrupt Pending (VIP)",null,null],[17,"RFLAGS_VIF","","Virtual Interrupt Flag (VIF)",null,null],[17,"RFLAGS_AC","","Alignment Check (AC)",null,null],[17,"RFLAGS_VM","","Virtual-8086 Mode (VM)",null,null],[17,"RFLAGS_RF","","Resume Flag (RF)",null,null],[17,"RFLAGS_NT","","Nested Task (NT)",null,null],[17,"RFLAGS_IOPL0","","I/O Privilege Level (IOPL) 0",null,null],[17,"RFLAGS_IOPL1","","I/O Privilege Level (IOPL) 1",null,null],[17,"RFLAGS_IOPL2","","I/O Privilege Level (IOPL) 2",null,null],[17,"RFLAGS_IOPL3","","I/O Privilege Level (IOPL) 3",null,null],[17,"RFLAGS_OF","","Overflow Flag (OF)",null,null],[17,"RFLAGS_DF","","Direction Flag (DF)",null,null],[17,"RFLAGS_IF","","Interrupt Enable Flag (IF)",null,null],[17,"RFLAGS_TF","","Trap Flag (TF)",null,null],[17,"RFLAGS_SF","","Sign Flag (SF)",null,null],[17,"RFLAGS_ZF","","Zero Flag (ZF)",null,null],[17,"RFLAGS_AF","","Auxiliary Carry Flag (AF)",null,null],[17,"RFLAGS_PF","","Parity Flag (PF)",null,null],[17,"RFLAGS_A1","","Bit 1 is always 1.",null,null],[17,"RFLAGS_CF","","Carry Flag (CF)",null,null],[11,"hash","","",3,null],[11,"cmp","","",3,null],[11,"partial_cmp","","",3,null],[11,"lt","","",3,null],[11,"le","","",3,null],[11,"gt","","",3,null],[11,"ge","","",3,null],[11,"clone","","",3,null],[11,"eq","","",3,null],[11,"ne","","",3,null],[11,"empty","","Returns an empty set of flags.",3,{"inputs":[],"output":{"name":"rflags"}}],[11,"all","","Returns the set containing all flags.",3,{"inputs":[],"output":{"name":"rflags"}}],[11,"bits","","Returns the raw value of the flags currently stored.",3,null],[11,"from_bits","","Convert from underlying bit representation, unless that\nrepresentation contains bits that do not correspond to a flag.",3,{"inputs":[{"name":"u64"}],"output":{"name":"option"}}],[11,"from_bits_truncate","","Convert from underlying bit representation, dropping any bits\nthat do not correspond to flags.",3,{"inputs":[{"name":"u64"}],"output":{"name":"rflags"}}],[11,"is_empty","","Returns `true` if no flags are currently stored.",3,null],[11,"is_all","","Returns `true` if all flags are currently set.",3,null],[11,"intersects","","Returns `true` if there are flags common to both `self` and `other`.",3,null],[11,"contains","","Returns `true` all of the flags in `other` are contained within `self`.",3,null],[11,"insert","","Inserts the specified flags in-place.",3,null],[11,"remove","","Removes the specified flags in-place.",3,null],[11,"toggle","","Toggles the specified flags in-place.",3,null],[11,"bitor","","Returns the union of the two sets of flags.",3,null],[11,"bitxor","","Returns the left flags, but with all the right flags toggled.",3,null],[11,"bitand","","Returns the intersection between the two sets of flags.",3,null],[11,"sub","","Returns the set difference of the two sets of flags.",3,null],[11,"not","","Returns the complement of this set of flags.",3,null],[11,"new","","Creates a new RFlags entry. Ensures bit 1 is set.",3,{"inputs":[],"output":{"name":"rflags"}}],[0,"paging","x86","Description of the data-structures for IA-32e paging mode.",null,null],[3,"PAddr","x86::paging","Represents a physical memory address",null,null],[3,"VAddr","","Represent a virtual (linear) memory address",null,null],[3,"PML4Entry","","",null,null],[3,"PDPTEntry","","",null,null],[3,"PDEntry","","",null,null],[3,"PTEntry","","",null,null],[5,"pml4_index","","Given virtual address calculate corresponding entry in PML4.",null,{"inputs":[{"name":"vaddr"}],"output":{"name":"usize"}}],[5,"pdpt_index","","Given virtual address calculate corresponding entry in PDPT.",null,{"inputs":[{"name":"vaddr"}],"output":{"name":"usize"}}],[5,"pd_index","","Given virtual address calculate corresponding entry in PD.",null,{"inputs":[{"name":"vaddr"}],"output":{"name":"usize"}}],[5,"pt_index","","Given virtual address calculate corresponding entry in PT.",null,{"inputs":[{"name":"vaddr"}],"output":{"name":"usize"}}],[6,"PML4","","A PML4 table.\nIn practice this has only 4 entries but it still needs to be the size of a 4K page.",null,null],[6,"PDPT","","A page directory pointer table.",null,null],[6,"PD","","A page directory.",null,null],[6,"PT","","A page table.",null,null],[17,"BASE_PAGE_SIZE","","",null,null],[17,"LARGE_PAGE_SIZE","","",null,null],[17,"HUGE_PAGE_SIZE","","",null,null],[17,"CACHE_LINE_SIZE","","",null,null],[17,"MAXPHYADDR","","MAXPHYADDR, which is at most 52; (use CPUID for finding system value).",null,null],[17,"PML4_P","","Present; must be 1 to reference a page-directory-pointer table",null,null],[17,"PML4_RW","","Read/write; if 0, writes may not be allowed to the 512-GByte region\ncontrolled by this entry (see Section 4.6)",null,null],[17,"PML4_US","","User/supervisor; if 0, user-mode accesses are not allowed\nto the 512-GByte region controlled by this entry.",null,null],[17,"PML4_PWT","","Page-level write-through; indirectly determines the memory type used to\naccess the page-directory-pointer table referenced by this entry.",null,null],[17,"PML4_PCD","","Page-level cache disable; indirectly determines the memory type used to\naccess the page-directory-pointer table referenced by this entry.",null,null],[17,"PML4_A","","Accessed; indicates whether this entry has been used for linear-address translation.",null,null],[17,"PML4_XD","","If IA32_EFER.NXE = 1, execute-disable\nIf 1, instruction fetches are not allowed from the 512-GByte region.",null,null],[17,"PDPT_P","","Present; must be 1 to map a 1-GByte page or reference a page directory.",null,null],[17,"PDPT_RW","","Read/write; if 0, writes may not be allowed to the 1-GByte region controlled by this entry",null,null],[17,"PDPT_US","","User/supervisor; user-mode accesses are not allowed to the 1-GByte region controlled by this entry.",null,null],[17,"PDPT_PWT","","Page-level write-through.",null,null],[17,"PDPT_PCD","","Page-level cache disable.",null,null],[17,"PDPT_A","","Accessed; if PDPT_PS set indicates whether software has accessed the 1-GByte page\nelse indicates whether this entry has been used for linear-address translation",null,null],[17,"PDPT_D","","Dirty; if PDPT_PS indicates whether software has written to the 1-GByte page referenced by this entry.\nelse ignored.",null,null],[17,"PDPT_PS","","Page size; if set this entry maps a 1-GByte page; otherwise, this entry references a page directory.\nif not PDPT_PS this is ignored.",null,null],[17,"PDPT_G","","Global; if PDPT_PS && CR4.PGE = 1, determines whether the translation is global; ignored otherwise\nif not PDPT_PS this is ignored.",null,null],[17,"PDPT_PAT","","Indirectly determines the memory type used to access the 1-GByte page referenced by this entry.",null,null],[17,"PDPT_XD","","If IA32_EFER.NXE = 1, execute-disable\nIf 1, instruction fetches are not allowed from the 512-GByte region.",null,null],[17,"PD_P","","Present; must be 1 to map a 2-MByte page or reference a page table.",null,null],[17,"PD_RW","","Read/write; if 0, writes may not be allowed to the 2-MByte region controlled by this entry",null,null],[17,"PD_US","","User/supervisor; user-mode accesses are not allowed to the 2-MByte region controlled by this entry.",null,null],[17,"PD_PWT","","Page-level write-through.",null,null],[17,"PD_PCD","","Page-level cache disable.",null,null],[17,"PD_A","","Accessed; if PD_PS set indicates whether software has accessed the 2-MByte page\nelse indicates whether this entry has been used for linear-address translation",null,null],[17,"PD_D","","Dirty; if PD_PS indicates whether software has written to the 2-MByte page referenced by this entry.\nelse ignored.",null,null],[17,"PD_PS","","Page size; if set this entry maps a 2-MByte page; otherwise, this entry references a page directory.",null,null],[17,"PD_G","","Global; if PD_PS && CR4.PGE = 1, determines whether the translation is global; ignored otherwise\nif not PD_PS this is ignored.",null,null],[17,"PD_PAT","","Indirectly determines the memory type used to access the 2-MByte page referenced by this entry.\nif not PD_PS this is ignored.",null,null],[17,"PD_XD","","If IA32_EFER.NXE = 1, execute-disable\nIf 1, instruction fetches are not allowed from the 512-GByte region.",null,null],[17,"PT_P","","Present; must be 1 to map a 4-KByte page.",null,null],[17,"PT_RW","","Read/write; if 0, writes may not be allowed to the 4-KByte region controlled by this entry",null,null],[17,"PT_US","","User/supervisor; user-mode accesses are not allowed to the 4-KByte region controlled by this entry.",null,null],[17,"PT_PWT","","Page-level write-through.",null,null],[17,"PT_PCD","","Page-level cache disable.",null,null],[17,"PT_A","","Accessed; indicates whether software has accessed the 4-KByte page",null,null],[17,"PT_D","","Dirty; indicates whether software has written to the 4-KByte page referenced by this entry.",null,null],[17,"PT_G","","Global; if CR4.PGE = 1, determines whether the translation is global (see Section 4.10); ignored otherwise",null,null],[17,"PT_XD","","If IA32_EFER.NXE = 1, execute-disable\nIf 1, instruction fetches are not allowed from the 512-GByte region.",null,null],[11,"partial_cmp","","",4,null],[11,"lt","","",4,null],[11,"le","","",4,null],[11,"gt","","",4,null],[11,"ge","","",4,null],[11,"eq","","",4,null],[11,"ne","","",4,null],[11,"cmp","","",4,null],[11,"fmt","","",4,null],[11,"clone","","",4,null],[11,"partial_cmp","","",5,null],[11,"lt","","",5,null],[11,"le","","",5,null],[11,"gt","","",5,null],[11,"ge","","",5,null],[11,"eq","","",5,null],[11,"ne","","",5,null],[11,"cmp","","",5,null],[11,"fmt","","",5,null],[11,"clone","","",5,null],[11,"as_u64","","Convert to `u64`",4,null],[11,"from_u64","","Convert from `u64`",4,{"inputs":[{"name":"u64"}],"output":{"name":"self"}}],[11,"as_usize","","Convert to `usize`",5,null],[11,"from_usize","","Convert from `usize`",5,{"inputs":[{"name":"usize"}],"output":{"name":"self"}}],[11,"fmt","","",4,null],[11,"fmt","","",4,null],[11,"fmt","","",4,null],[11,"fmt","","",4,null],[11,"fmt","","",4,null],[11,"fmt","","",5,null],[11,"fmt","","",5,null],[11,"fmt","","",5,null],[11,"fmt","","",5,null],[11,"fmt","","",5,null],[11,"hash","","",6,null],[11,"cmp","","",6,null],[11,"partial_cmp","","",6,null],[11,"lt","","",6,null],[11,"le","","",6,null],[11,"gt","","",6,null],[11,"ge","","",6,null],[11,"clone","","",6,null],[11,"eq","","",6,null],[11,"ne","","",6,null],[11,"fmt","","",6,null],[11,"empty","","Returns an empty set of flags.",6,{"inputs":[],"output":{"name":"pml4entry"}}],[11,"all","","Returns the set containing all flags.",6,{"inputs":[],"output":{"name":"pml4entry"}}],[11,"bits","","Returns the raw value of the flags currently stored.",6,null],[11,"from_bits","","Convert from underlying bit representation, unless that\nrepresentation contains bits that do not correspond to a flag.",6,{"inputs":[{"name":"u64"}],"output":{"name":"option"}}],[11,"from_bits_truncate","","Convert from underlying bit representation, dropping any bits\nthat do not correspond to flags.",6,{"inputs":[{"name":"u64"}],"output":{"name":"pml4entry"}}],[11,"is_empty","","Returns `true` if no flags are currently stored.",6,null],[11,"is_all","","Returns `true` if all flags are currently set.",6,null],[11,"intersects","","Returns `true` if there are flags common to both `self` and `other`.",6,null],[11,"contains","","Returns `true` all of the flags in `other` are contained within `self`.",6,null],[11,"insert","","Inserts the specified flags in-place.",6,null],[11,"remove","","Removes the specified flags in-place.",6,null],[11,"toggle","","Toggles the specified flags in-place.",6,null],[11,"bitor","","Returns the union of the two sets of flags.",6,null],[11,"bitxor","","Returns the left flags, but with all the right flags toggled.",6,null],[11,"bitand","","Returns the intersection between the two sets of flags.",6,null],[11,"sub","","Returns the set difference of the two sets of flags.",6,null],[11,"not","","Returns the complement of this set of flags.",6,null],[11,"new","","Creates a new PML4Entry.",6,{"inputs":[{"name":"paddr"},{"name":"pml4entry"}],"output":{"name":"pml4entry"}}],[11,"get_address","","Retrieves the physical address in this entry.",6,null],[11,"is_present","","Is page present?",6,null],[11,"is_writeable","","Read/write; if 0, writes may not be allowed to the 512-GByte region, controlled by this entry (see Section 4.6)",6,null],[11,"is_user_mode_allowed","","User/supervisor; if 0, user-mode accesses are not allowed to the 512-GByte region controlled by this entry.",6,null],[11,"is_page_write_through","","Page-level write-through; indirectly determines the memory type used to access the page-directory-pointer table referenced by this entry.",6,null],[11,"is_page_level_cache_disabled","","Page-level cache disable; indirectly determines the memory type used to access the page-directory-pointer table referenced by this entry.",6,null],[11,"is_accessed","","Accessed; indicates whether this entry has been used for linear-address translation.",6,null],[11,"is_instruction_fetching_disabled","","If IA32_EFER.NXE = 1, execute-disable. If 1, instruction fetches are not allowed from the 512-GByte region.",6,null],[11,"hash","","",7,null],[11,"cmp","","",7,null],[11,"partial_cmp","","",7,null],[11,"lt","","",7,null],[11,"le","","",7,null],[11,"gt","","",7,null],[11,"ge","","",7,null],[11,"clone","","",7,null],[11,"eq","","",7,null],[11,"ne","","",7,null],[11,"fmt","","",7,null],[11,"empty","","Returns an empty set of flags.",7,{"inputs":[],"output":{"name":"pdptentry"}}],[11,"all","","Returns the set containing all flags.",7,{"inputs":[],"output":{"name":"pdptentry"}}],[11,"bits","","Returns the raw value of the flags currently stored.",7,null],[11,"from_bits","","Convert from underlying bit representation, unless that\nrepresentation contains bits that do not correspond to a flag.",7,{"inputs":[{"name":"u64"}],"output":{"name":"option"}}],[11,"from_bits_truncate","","Convert from underlying bit representation, dropping any bits\nthat do not correspond to flags.",7,{"inputs":[{"name":"u64"}],"output":{"name":"pdptentry"}}],[11,"is_empty","","Returns `true` if no flags are currently stored.",7,null],[11,"is_all","","Returns `true` if all flags are currently set.",7,null],[11,"intersects","","Returns `true` if there are flags common to both `self` and `other`.",7,null],[11,"contains","","Returns `true` all of the flags in `other` are contained within `self`.",7,null],[11,"insert","","Inserts the specified flags in-place.",7,null],[11,"remove","","Removes the specified flags in-place.",7,null],[11,"toggle","","Toggles the specified flags in-place.",7,null],[11,"bitor","","Returns the union of the two sets of flags.",7,null],[11,"bitxor","","Returns the left flags, but with all the right flags toggled.",7,null],[11,"bitand","","Returns the intersection between the two sets of flags.",7,null],[11,"sub","","Returns the set difference of the two sets of flags.",7,null],[11,"not","","Returns the complement of this set of flags.",7,null],[11,"new","","Creates a new PDPTEntry.",7,{"inputs":[{"name":"paddr"},{"name":"pdptentry"}],"output":{"name":"pdptentry"}}],[11,"get_address","","Retrieves the physical address in this entry.",7,null],[11,"is_present","","Is page present?",7,null],[11,"is_writeable","","Read/write; if 0, writes may not be allowed to the 1-GByte region controlled by this entry.",7,null],[11,"is_user_mode_allowed","","User/supervisor; user-mode accesses are not allowed to the 1-GByte region controlled by this entry.",7,null],[11,"is_page_write_through","","Page-level write-through.",7,null],[11,"is_page_level_cache_disabled","","Page-level cache disable.",7,null],[11,"is_accessed","","Accessed; indicates whether this entry has been used for linear-address translation.",7,null],[11,"is_pat","","Indirectly determines the memory type used to access the 1-GByte page referenced by this entry. if not PDPT_PS this is ignored.",7,null],[11,"is_instruction_fetching_disabled","","If IA32_EFER.NXE = 1, execute-disable. If 1, instruction fetches are not allowed from the 512-GByte region.",7,null],[11,"hash","","",8,null],[11,"cmp","","",8,null],[11,"partial_cmp","","",8,null],[11,"lt","","",8,null],[11,"le","","",8,null],[11,"gt","","",8,null],[11,"ge","","",8,null],[11,"clone","","",8,null],[11,"eq","","",8,null],[11,"ne","","",8,null],[11,"fmt","","",8,null],[11,"empty","","Returns an empty set of flags.",8,{"inputs":[],"output":{"name":"pdentry"}}],[11,"all","","Returns the set containing all flags.",8,{"inputs":[],"output":{"name":"pdentry"}}],[11,"bits","","Returns the raw value of the flags currently stored.",8,null],[11,"from_bits","","Convert from underlying bit representation, unless that\nrepresentation contains bits that do not correspond to a flag.",8,{"inputs":[{"name":"u64"}],"output":{"name":"option"}}],[11,"from_bits_truncate","","Convert from underlying bit representation, dropping any bits\nthat do not correspond to flags.",8,{"inputs":[{"name":"u64"}],"output":{"name":"pdentry"}}],[11,"is_empty","","Returns `true` if no flags are currently stored.",8,null],[11,"is_all","","Returns `true` if all flags are currently set.",8,null],[11,"intersects","","Returns `true` if there are flags common to both `self` and `other`.",8,null],[11,"contains","","Returns `true` all of the flags in `other` are contained within `self`.",8,null],[11,"insert","","Inserts the specified flags in-place.",8,null],[11,"remove","","Removes the specified flags in-place.",8,null],[11,"toggle","","Toggles the specified flags in-place.",8,null],[11,"bitor","","Returns the union of the two sets of flags.",8,null],[11,"bitxor","","Returns the left flags, but with all the right flags toggled.",8,null],[11,"bitand","","Returns the intersection between the two sets of flags.",8,null],[11,"sub","","Returns the set difference of the two sets of flags.",8,null],[11,"not","","Returns the complement of this set of flags.",8,null],[11,"new","","Creates a new PDEntry.",8,{"inputs":[{"name":"paddr"},{"name":"pdentry"}],"output":{"name":"pdentry"}}],[11,"get_address","","Retrieves the physical address in this entry.",8,null],[11,"is_present","","Present; must be 1 to map a 2-MByte page or reference a page table.",8,null],[11,"is_writeable","","Read/write; if 0, writes may not be allowed to the 2-MByte region controlled by this entry",8,null],[11,"is_user_mode_allowed","","User/supervisor; user-mode accesses are not allowed to the 2-MByte region controlled by this entry.",8,null],[11,"is_page_write_through","","Page-level write-through.",8,null],[11,"is_page_level_cache_disabled","","Page-level cache disable.",8,null],[11,"is_accessed","","Accessed; if PD_PS set indicates whether software has accessed the 2-MByte page else indicates whether this entry has been used for linear-address translation.",8,null],[11,"is_dirty","","Dirty; if PD_PS set indicates whether software has written to the 2-MByte page referenced by this entry else ignored.",8,null],[11,"is_page","","Page size; if set this entry maps a 2-MByte page; otherwise, this entry references a page directory.",8,null],[11,"is_global","","Global; if PD_PS && CR4.PGE = 1, determines whether the translation is global; ignored otherwise if not PD_PS this is ignored.",8,null],[11,"is_pat","","Indirectly determines the memory type used to access the 2-MByte page referenced by this entry. if not PD_PS this is ignored.",8,null],[11,"is_instruction_fetching_disabled","","If IA32_EFER.NXE = 1, execute-disable. If 1, instruction fetches are not allowed from the 2-Mbyte region.",8,null],[11,"hash","","",9,null],[11,"cmp","","",9,null],[11,"partial_cmp","","",9,null],[11,"lt","","",9,null],[11,"le","","",9,null],[11,"gt","","",9,null],[11,"ge","","",9,null],[11,"clone","","",9,null],[11,"eq","","",9,null],[11,"ne","","",9,null],[11,"fmt","","",9,null],[11,"empty","","Returns an empty set of flags.",9,{"inputs":[],"output":{"name":"ptentry"}}],[11,"all","","Returns the set containing all flags.",9,{"inputs":[],"output":{"name":"ptentry"}}],[11,"bits","","Returns the raw value of the flags currently stored.",9,null],[11,"from_bits","","Convert from underlying bit representation, unless that\nrepresentation contains bits that do not correspond to a flag.",9,{"inputs":[{"name":"u64"}],"output":{"name":"option"}}],[11,"from_bits_truncate","","Convert from underlying bit representation, dropping any bits\nthat do not correspond to flags.",9,{"inputs":[{"name":"u64"}],"output":{"name":"ptentry"}}],[11,"is_empty","","Returns `true` if no flags are currently stored.",9,null],[11,"is_all","","Returns `true` if all flags are currently set.",9,null],[11,"intersects","","Returns `true` if there are flags common to both `self` and `other`.",9,null],[11,"contains","","Returns `true` all of the flags in `other` are contained within `self`.",9,null],[11,"insert","","Inserts the specified flags in-place.",9,null],[11,"remove","","Removes the specified flags in-place.",9,null],[11,"toggle","","Toggles the specified flags in-place.",9,null],[11,"bitor","","Returns the union of the two sets of flags.",9,null],[11,"bitxor","","Returns the left flags, but with all the right flags toggled.",9,null],[11,"bitand","","Returns the intersection between the two sets of flags.",9,null],[11,"sub","","Returns the set difference of the two sets of flags.",9,null],[11,"not","","Returns the complement of this set of flags.",9,null],[11,"new","","Creates a new PTEntry.",9,{"inputs":[{"name":"paddr"},{"name":"ptentry"}],"output":{"name":"ptentry"}}],[11,"get_address","","Retrieves the physical address in this entry.",9,null],[11,"is_present","","Present; must be 1 to map a 4-KByte page or reference a page table.",9,null],[11,"is_writeable","","Read/write; if 0, writes may not be allowed to the 4-KByte region controlled by this entry",9,null],[11,"is_user_mode_allowed","","User/supervisor; user-mode accesses are not allowed to the 4-KByte region controlled by this entry.",9,null],[11,"is_page_write_through","","Page-level write-through.",9,null],[11,"is_page_level_cache_disabled","","Page-level cache disable.",9,null],[11,"is_accessed","","Accessed; if PT_PS set indicates whether software has accessed the 4-KByte page else indicates whether this entry has been used for linear-address translation.",9,null],[11,"is_dirty","","Dirty; if PD_PS set indicates whether software has written to the 4-KByte page referenced by this entry else ignored.",9,null],[11,"is_global","","Global; if PT_PS && CR4.PGE = 1, determines whether the translation is global; ignored otherwise if not PT_PS this is ignored.",9,null],[11,"is_instruction_fetching_disabled","","If IA32_EFER.NXE = 1, execute-disable. If 1, instruction fetches are not allowed from the 4-KByte region.",9,null],[0,"segmentation","x86","Program x86 segmentation hardware.",null,null],[3,"SegmentSelector","x86::segmentation","",null,null],[3,"SegmentDescriptor","","",null,null],[5,"load_ss","","Reload stack segment register.",null,{"inputs":[{"name":"segmentselector"}],"output":null}],[5,"load_ds","","Reload data segment register.",null,{"inputs":[{"name":"segmentselector"}],"output":null}],[5,"load_es","","Reload fs segment register.",null,{"inputs":[{"name":"segmentselector"}],"output":null}],[5,"load_fs","","Reload fs segment register.",null,{"inputs":[{"name":"segmentselector"}],"output":null}],[5,"load_gs","","Reload gs segment register.",null,{"inputs":[{"name":"segmentselector"}],"output":null}],[5,"load_cs","","Reload code segment register.\nNote this is special since we can not directly move\nto %cs. Instead we push the new segment selector\nand return value on the stack and use lretq\nto reload cs and continue at 1:.",null,{"inputs":[{"name":"segmentselector"}],"output":null}],[17,"RPL_0","","Requestor Privilege Level",null,null],[17,"RPL_1","","",null,null],[17,"RPL_2","","",null,null],[17,"RPL_3","","",null,null],[17,"TI_GDT","","Table Indicator (TI) 0 means GDT is used.",null,null],[17,"TI_LDT","","Table Indicator (TI) 1 means LDT is used.",null,null],[17,"DESC_S","","Descriptor type (0 = system; 1 = code or data).",null,null],[17,"DESC_DPL0","","Descriptor privilege level 0.",null,null],[17,"DESC_DPL1","","Descriptor privilege level 1.",null,null],[17,"DESC_DPL2","","Descriptor privilege level 2.",null,null],[17,"DESC_DPL3","","Descriptor privilege level 3.",null,null],[17,"DESC_P","","Descriptor is Present.",null,null],[17,"DESC_AVL","","Available for use by system software.",null,null],[17,"DESC_L","","64-bit code segment (IA-32e mode only).",null,null],[17,"DESC_DB","","Default operation size (0 = 16-bit segment, 1 = 32-bit segment)",null,null],[17,"DESC_G","","Granularity.",null,null],[17,"TYPE_SYS_LDT","","",null,null],[17,"TYPE_SYS_TSS_AVAILABLE","","",null,null],[17,"TYPE_SYS_TSS_BUSY","","",null,null],[17,"TYPE_SYS_CALL_GATE","","",null,null],[17,"TYPE_SYS_INTERRUPT_GATE","","",null,null],[17,"TYPE_SYS_TRAP_GATE","","",null,null],[17,"TYPE_D_RO","","Data Read-Only",null,null],[17,"TYPE_D_ROA","","Data Read-Only, accessed",null,null],[17,"TYPE_D_RW","","Data Read/Write",null,null],[17,"TYPE_D_RWA","","Data Read/Write, accessed",null,null],[17,"TYPE_D_ROEXD","","Data Read-Only, expand-down",null,null],[17,"TYPE_D_ROEXDA","","Data Read-Only, expand-down, accessed",null,null],[17,"TYPE_D_RWEXD","","Data Read/Write, expand-down",null,null],[17,"TYPE_D_RWEXDA","","Data Read/Write, expand-down, accessed",null,null],[17,"TYPE_C_EO","","Code Execute-Only",null,null],[17,"TYPE_C_EOA","","Code Execute-Only, accessed",null,null],[17,"TYPE_C_ER","","Code Execute/Read",null,null],[17,"TYPE_C_ERA","","Code Execute/Read, accessed",null,null],[17,"TYPE_C_EOC","","Code Execute-Only, conforming",null,null],[17,"TYPE_C_EOCA","","Code Execute-Only, conforming, accessed",null,null],[17,"TYPE_C_ERC","","Code Execute/Read, conforming",null,null],[17,"TYPE_C_ERCA","","Code Execute/Read, conforming, accessed",null,null],[11,"hash","","",10,null],[11,"cmp","","",10,null],[11,"partial_cmp","","",10,null],[11,"lt","","",10,null],[11,"le","","",10,null],[11,"gt","","",10,null],[11,"ge","","",10,null],[11,"clone","","",10,null],[11,"eq","","",10,null],[11,"ne","","",10,null],[11,"empty","","Returns an empty set of flags.",10,{"inputs":[],"output":{"name":"segmentselector"}}],[11,"all","","Returns the set containing all flags.",10,{"inputs":[],"output":{"name":"segmentselector"}}],[11,"bits","","Returns the raw value of the flags currently stored.",10,null],[11,"from_bits","","Convert from underlying bit representation, unless that\nrepresentation contains bits that do not correspond to a flag.",10,{"inputs":[{"name":"u16"}],"output":{"name":"option"}}],[11,"from_bits_truncate","","Convert from underlying bit representation, dropping any bits\nthat do not correspond to flags.",10,{"inputs":[{"name":"u16"}],"output":{"name":"segmentselector"}}],[11,"is_empty","","Returns `true` if no flags are currently stored.",10,null],[11,"is_all","","Returns `true` if all flags are currently set.",10,null],[11,"intersects","","Returns `true` if there are flags common to both `self` and `other`.",10,null],[11,"contains","","Returns `true` all of the flags in `other` are contained within `self`.",10,null],[11,"insert","","Inserts the specified flags in-place.",10,null],[11,"remove","","Removes the specified flags in-place.",10,null],[11,"toggle","","Toggles the specified flags in-place.",10,null],[11,"bitor","","Returns the union of the two sets of flags.",10,null],[11,"bitxor","","Returns the left flags, but with all the right flags toggled.",10,null],[11,"bitand","","Returns the intersection between the two sets of flags.",10,null],[11,"sub","","Returns the set difference of the two sets of flags.",10,null],[11,"not","","Returns the complement of this set of flags.",10,null],[11,"new","","Create a new SegmentSelector",10,{"inputs":[{"name":"u16"}],"output":{"name":"segmentselector"}}],[11,"from_raw","","",10,{"inputs":[{"name":"u16"}],"output":{"name":"segmentselector"}}],[11,"fmt","","",10,null],[11,"hash","","",11,null],[11,"cmp","","",11,null],[11,"partial_cmp","","",11,null],[11,"lt","","",11,null],[11,"le","","",11,null],[11,"gt","","",11,null],[11,"ge","","",11,null],[11,"clone","","",11,null],[11,"eq","","",11,null],[11,"ne","","",11,null],[11,"empty","","Returns an empty set of flags.",11,{"inputs":[],"output":{"name":"segmentdescriptor"}}],[11,"all","","Returns the set containing all flags.",11,{"inputs":[],"output":{"name":"segmentdescriptor"}}],[11,"bits","","Returns the raw value of the flags currently stored.",11,null],[11,"from_bits","","Convert from underlying bit representation, unless that\nrepresentation contains bits that do not correspond to a flag.",11,{"inputs":[{"name":"u64"}],"output":{"name":"option"}}],[11,"from_bits_truncate","","Convert from underlying bit representation, dropping any bits\nthat do not correspond to flags.",11,{"inputs":[{"name":"u64"}],"output":{"name":"segmentdescriptor"}}],[11,"is_empty","","Returns `true` if no flags are currently stored.",11,null],[11,"is_all","","Returns `true` if all flags are currently set.",11,null],[11,"intersects","","Returns `true` if there are flags common to both `self` and `other`.",11,null],[11,"contains","","Returns `true` all of the flags in `other` are contained within `self`.",11,null],[11,"insert","","Inserts the specified flags in-place.",11,null],[11,"remove","","Removes the specified flags in-place.",11,null],[11,"toggle","","Toggles the specified flags in-place.",11,null],[11,"bitor","","Returns the union of the two sets of flags.",11,null],[11,"bitxor","","Returns the left flags, but with all the right flags toggled.",11,null],[11,"bitand","","Returns the intersection between the two sets of flags.",11,null],[11,"sub","","Returns the set difference of the two sets of flags.",11,null],[11,"not","","Returns the complement of this set of flags.",11,null],[11,"new","","",11,{"inputs":[{"name":"u32"},{"name":"u32"}],"output":{"name":"segmentdescriptor"}}],[11,"fmt","","",11,null],[0,"task","x86","Helpers to program the task state segment.",null,null],[3,"TaskStateSegment","x86::task","In 64-bit mode the TSS holds information that is not\ndirectly related to the task-switch mechanism,\nbut is used for finding kernel level stack\nif interrupts arrive while in kernel mode.",null,null],[12,"reserved","","",12,null],[12,"rsp","","The full 64-bit canonical forms of the stack pointers (RSP) for privilege levels 0-2.",12,null],[12,"reserved2","","",12,null],[12,"ist","","The full 64-bit canonical forms of the interrupt stack table (IST) pointers.",12,null],[12,"reserved3","","",12,null],[12,"reserved4","","",12,null],[12,"iomap_base","","The 16-bit offset to the I/O permission bit map from the 64-bit TSS base.",12,null],[5,"load_ltr","","Load the task state register.",null,{"inputs":[{"name":"segmentselector"}],"output":null}],[6,"TaskStateDescriptorLow","","",null,null],[6,"TaskStateDescriptorHigh","","",null,null],[11,"fmt","","",12,null],[11,"new","","",12,{"inputs":[],"output":{"name":"taskstatesegment"}}],[0,"dtables","x86","Functions and data-structures to load descriptor tables.",null,null],[3,"DescriptorTablePointer","x86::dtables","A struct describing a pointer to a descriptor table (GDT / IDT).\nThis is in a format suitable for giving to 'lgdt' or 'lidt'.",null,null],[12,"limit","","Size of the DT.",13,null],[12,"base","","Pointer to the memory region containing the DT.",13,null],[5,"lgdt","","Load GDT table.",null,{"inputs":[{"name":"descriptortablepointer"}],"output":null}],[5,"lldt","","Load LDT table.",null,{"inputs":[{"name":"descriptortablepointer"}],"output":null}],[5,"lidt","","Load IDT table.",null,{"inputs":[{"name":"descriptortablepointer"}],"output":null}],[11,"fmt","","",13,null],[0,"syscall","x86","Invokes an OS system-call handler at privilege level 0.",null,null],[5,"syscall0","x86::syscall","",null,{"inputs":[{"name":"u64"}],"output":{"name":"u64"}}],[5,"syscall1","","",null,{"inputs":[{"name":"u64"},{"name":"u64"}],"output":{"name":"u64"}}],[5,"syscall2","","",null,{"inputs":[{"name":"u64"},{"name":"u64"},{"name":"u64"}],"output":{"name":"u64"}}],[5,"syscall3","","",null,{"inputs":[{"name":"u64"},{"name":"u64"},{"name":"u64"},{"name":"u64"}],"output":{"name":"u64"}}],[5,"syscall4","","",null,{"inputs":[{"name":"u64"},{"name":"u64"},{"name":"u64"},{"name":"u64"},{"name":"u64"}],"output":{"name":"u64"}}],[5,"syscall5","","",null,{"inputs":[{"name":"u64"},{"name":"u64"},{"name":"u64"},{"name":"u64"},{"name":"u64"},{"name":"u64"}],"output":{"name":"u64"}}],[5,"syscall6","","",null,{"inputs":[{"name":"u64"},{"name":"u64"},{"name":"u64"},{"name":"u64"},{"name":"u64"},{"name":"u64"},{"name":"u64"}],"output":{"name":"u64"}}],[0,"perfcnt","x86","Information about available performance counters.",null,null],[5,"core_counters","x86::perfcnt","Return all core performance counters for the running micro-architecture.",null,{"inputs":[],"output":{"name":"option"}}],[5,"uncore_counters","","Return all uncore performance counters for the running micro-architecture.",null,{"inputs":[],"output":{"name":"option"}}],[0,"intel","","Information about Intel's performance counters.",null,null],[0,"counters","x86::perfcnt::intel","Performance counter for all Intel architectures.",null,null],[7,"COUNTER_MAP","x86::perfcnt::intel::counters","",null,null],[17,"WESTMEREEP_SP_CORE","","",null,null],[17,"SILVERMONT_CORE","","",null,null],[17,"SANDYBRIDGE_UNCORE","","",null,null],[17,"IVYBRIDGE_UNCORE","","",null,null],[17,"BROADWELLDE_UNCORE","","",null,null],[17,"IVYTOWN_CORE","","",null,null],[17,"IVYBRIDGE_CORE","","",null,null],[17,"NEHALEMEX_CORE","","",null,null],[17,"NEHALEMEP_CORE","","",null,null],[17,"HASWELLX_UNCORE","","",null,null],[17,"HASWELL_CORE","","",null,null],[17,"JAKETOWN_CORE","","",null,null],[17,"BROADWELL_CORE","","",null,null],[17,"SANDYBRIDGE_CORE","","",null,null],[17,"BONNELL_CORE","","",null,null],[17,"HASWELL_UNCORE","","",null,null],[17,"BROADWELLDE_CORE","","",null,null],[17,"HASWELLX_CORE","","",null,null],[17,"WESTMEREEP_DP_CORE","","",null,null],[17,"SKYLAKE_CORE","","",null,null],[17,"BROADWELL_UNCORE","","",null,null],[17,"WESTMEREEX_CORE","","",null,null],[17,"JAKETOWN_UNCORE","","",null,null],[17,"IVYTOWN_UNCORE","","",null,null],[0,"description","x86::perfcnt::intel","",null,null],[3,"IntelPerformanceCounterDescription","x86::perfcnt::intel::description","",null,null],[12,"event_code","","This field maps to the Event Select field in the IA32_PERFEVTSELx[7:0]MSRs.",14,null],[12,"umask","","This field maps to the Unit Mask filed in the IA32_PERFEVTSELx[15:8] MSRs.",14,null],[12,"event_name","","It is a string of characters to identify the programming of an event.",14,null],[12,"brief_description","","This field contains a description of what is being counted by a particular event.",14,null],[12,"public_description","","In some cases, this field will contain a more detailed description of what is counted by an event.",14,null],[12,"counter","","This field lists the fixed (PERF_FIXED_CTRX) or programmable (IA32_PMCX)\ncounters that can be used to count the event.",14,null],[12,"counter_ht_off","","This field lists the counters where this event can be sampled\nwhen Intel® Hyper-Threading Technology (Intel® HT Technology) is\ndisabled.",14,null],[12,"pebs_counters","","This field is only relevant to PEBS events.",14,null],[12,"sample_after_value","","Sample After Value (SAV) is the value that can be preloaded\ninto the counter registers to set the point at which they will overflow.",14,null],[12,"msr_index","","Additional MSRs may be required for programming certain events.\nThis field gives the address of such MSRS.",14,null],[12,"msr_value","","When an MSRIndex is used (indicated by the MSRIndex column), this field will\ncontain the value that needs to be loaded into the\nregister whose address is given in MSRIndex column.",14,null],[12,"taken_alone","","This field is set for an event which can only be sampled or counted by itself,\nmeaning that when this event is being collected,\nthe remaining programmable counters are not available to count any other events.",14,null],[12,"counter_mask","","This field maps to the Counter Mask (CMASK) field in IA32_PERFEVTSELx[31:24] MSR.",14,null],[12,"invert","","This field corresponds to the Invert Counter Mask (INV) field in IA32_PERFEVTSELx[23] MSR.",14,null],[12,"any_thread","","This field corresponds to the Any Thread (ANY) bit of IA32_PERFEVTSELx[21] MSR.",14,null],[12,"edge_detect","","This field corresponds to the Edge Detect (E) bit of IA32_PERFEVTSELx[18] MSR.",14,null],[12,"pebs","","A '0' in this field means that the event cannot be programmed as a PEBS event.\nA '1' in this field means that the event is a  precise event and can be programmed\nin one of two ways – as a regular event or as a PEBS event.\nAnd a '2' in this field means that the event can only be programmed as a PEBS event.",14,null],[12,"precise_store","","A '1' in this field means the event uses the Precise Store feature and Bit 3 and\nbit 63 in IA32_PEBS_ENABLE MSR must be set to enable IA32_PMC3 as a PEBS counter\nand enable the precise store facility respectively.",14,null],[12,"data_la","","A '1' in this field means that when the event is configured as a PEBS event,\nthe Data Linear Address facility is supported.",14,null],[12,"l1_hit_indication","","A '1' in this field means that when the event is configured as a PEBS event,\nthe DCU hit field of the PEBS record is set to 1 when the store hits in the\nL1 cache and 0 when it misses.",14,null],[12,"errata","","This field lists the known bugs that apply to the events.",14,null],[12,"offcore","","There is only 1 file for core and offcore events in this format.\nThis field is set to 1 for offcore events and 0 for core events.",14,null],[12,"unit","","",14,null],[12,"filter","","",14,null],[12,"extsel","","",14,null],[4,"PebsType","","",null,null],[13,"Regular","","",15,null],[13,"PebsOrRegular","","",15,null],[13,"PebsOnly","","",15,null],[4,"Tuple","","",null,null],[13,"One","","",16,null],[13,"Two","","",16,null],[4,"MSRIndex","","",null,null],[13,"None","","",17,null],[13,"One","","",17,null],[13,"Two","","",17,null],[4,"Counter","","",null,null],[13,"Fixed","","Bit-mask containing the fixed counters\nusable with the corresponding performance event.",18,null],[13,"Programmable","","Bit-mask containing the programmable counters\nusable with the corresponding performance event.",18,null],[11,"fmt","","",15,null],[11,"fmt","","",16,null],[11,"fmt","","",17,null],[11,"fmt","","",18,null],[11,"fmt","","",14,null],[0,"cpuid","x86","",null,null],[0,"tlb","","Functions to flush the translation lookaside buffer (TLB).",null,null],[5,"flush","x86::tlb","Invalidate the given address in the TLB using the `invlpg` instruction.",null,{"inputs":[{"name":"usize"}],"output":null}],[5,"flush_all","","Invalidate the TLB completely by reloading the CR3 register.",null,{"inputs":[],"output":null}],[14,"int!","x86","Generate a software interrupt.\nThis is a macro argument needs to be an immediate.",null,null],[14,"syscall!","","",null,null]],"paths":[[3,"InterruptDescription"],[3,"IdtEntry"],[3,"PageFaultError"],[3,"RFlags"],[3,"PAddr"],[3,"VAddr"],[3,"PML4Entry"],[3,"PDPTEntry"],[3,"PDEntry"],[3,"PTEntry"],[3,"SegmentSelector"],[3,"SegmentDescriptor"],[3,"TaskStateSegment"],[3,"DescriptorTablePointer"],[3,"IntelPerformanceCounterDescription"],[4,"PebsType"],[4,"Tuple"],[4,"MSRIndex"],[4,"Counter"]]};
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