Constant x86::msr::MSR_EFSB_DRDY0

pub const MSR_EFSB_DRDY0: u32 = 0x107d0;

EFSB DRDY Event Control and Counter Register (R/W) See Section 18.17, Performance Monitoring on 64-bit Intel Xeon Processor MP with Up to 8-MByte L3 Cache for details.