[][src]Crate vl53l1_reg

A crate for low-level access to the registers on the VL53L1X.

Provides:

  • A type for every "entry" in the register map.
  • An Entry trait for abstracting over register entries.
  • An Index type for a dynamic representation of entry indices into the register map.
  • An State type for a dynamic representation of entry state.
  • write_* and read_* functions for writing and reading to and from the VL53L1X's registers.
  • A structs module with commonly grouped registers and generated methods for writing and reading these groups at once.

The generated code takes quite a while to compile (~7 secs) so it has been split into this separate crate and re-exported under the reg module in the main crate.

Re-exports

pub use structs::Entries;

Modules

settings
structs

Macros

write_all_entries

Structs

ALGO__CONSISTENCY_CHECK__TOLERANCE
ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS
ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_HI
ALGO__CROSSTALK_COMPENSATION_PLANE_OFFSET_KCPS_LO
ALGO__CROSSTALK_COMPENSATION_VALID_HEIGHT_MM
ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS
ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_HI
ALGO__CROSSTALK_COMPENSATION_X_PLANE_GRADIENT_KCPS_LO
ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS
ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_HI
ALGO__CROSSTALK_COMPENSATION_Y_PLANE_GRADIENT_KCPS_LO
ALGO__PART_TO_PART_RANGE_OFFSET_MM
ALGO__PART_TO_PART_RANGE_OFFSET_MM_HI
ALGO__PART_TO_PART_RANGE_OFFSET_MM_LO
ALGO__RANGE_IGNORE_THRESHOLD_MCPS
ALGO__RANGE_IGNORE_THRESHOLD_MCPS_HI
ALGO__RANGE_IGNORE_THRESHOLD_MCPS_LO
ALGO__RANGE_IGNORE_VALID_HEIGHT_MM
ALGO__RANGE_MIN_CLIP
ANA_CONFIG__FAST_OSC__CONFIG_CTRL
ANA_CONFIG__FAST_OSC__FREQ_SET
ANA_CONFIG__FAST_OSC__TRIM
ANA_CONFIG__FAST_OSC__TRIM_MAX
ANA_CONFIG__OSC_SLOW_CTRL
ANA_CONFIG__POWERDOWN_GO1
ANA_CONFIG__REF_BG_CTRL
ANA_CONFIG__REGDVDD1V2_CTRL
ANA_CONFIG__REG_AVDD1V2_SEL
ANA_CONFIG__SPAD_SEL_PSWIDTH
ANA_CONFIG__VCSEL_PULSE_WIDTH_OFFSET
ANA_CONFIG__VCSEL_SELION
ANA_CONFIG__VCSEL_SELION_MAX
ANA_CONFIG__VCSEL_TRIM
ANA_CONFIG__VHV_REF_SEL_VDDPIX
ANA_CONFIG__VHV_REF_SEL_VQUENCH
CAL_CONFIG__REPEAT_RATE
CAL_CONFIG__REPEAT_RATE_HI
CAL_CONFIG__REPEAT_RATE_LO
CAL_CONFIG__VCSEL_START
CLK_GATING__CTRL
CLK__CONFIG
DEBUG__CTRL
DSS_CALC__MODE_ROI_0
DSS_CALC__MODE_ROI_1
DSS_CALC__ROI_CTRL
DSS_CALC__SPARE_1
DSS_CALC__SPARE_2
DSS_CALC__SPARE_3
DSS_CALC__SPARE_4
DSS_CALC__SPARE_5
DSS_CALC__SPARE_6
DSS_CALC__SPARE_7
DSS_CALC__USER_ROI_0
DSS_CALC__USER_ROI_1
DSS_CALC__USER_ROI_SPAD_EN_0
DSS_CALC__USER_ROI_SPAD_EN_1
DSS_CALC__USER_ROI_SPAD_EN_2
DSS_CALC__USER_ROI_SPAD_EN_3
DSS_CALC__USER_ROI_SPAD_EN_4
DSS_CALC__USER_ROI_SPAD_EN_5
DSS_CALC__USER_ROI_SPAD_EN_6
DSS_CALC__USER_ROI_SPAD_EN_7
DSS_CALC__USER_ROI_SPAD_EN_8
DSS_CALC__USER_ROI_SPAD_EN_9
DSS_CALC__USER_ROI_SPAD_EN_10
DSS_CALC__USER_ROI_SPAD_EN_11
DSS_CALC__USER_ROI_SPAD_EN_12
DSS_CALC__USER_ROI_SPAD_EN_13
DSS_CALC__USER_ROI_SPAD_EN_14
DSS_CALC__USER_ROI_SPAD_EN_15
DSS_CALC__USER_ROI_SPAD_EN_16
DSS_CALC__USER_ROI_SPAD_EN_17
DSS_CALC__USER_ROI_SPAD_EN_18
DSS_CALC__USER_ROI_SPAD_EN_19
DSS_CALC__USER_ROI_SPAD_EN_20
DSS_CALC__USER_ROI_SPAD_EN_21
DSS_CALC__USER_ROI_SPAD_EN_22
DSS_CALC__USER_ROI_SPAD_EN_23
DSS_CALC__USER_ROI_SPAD_EN_24
DSS_CALC__USER_ROI_SPAD_EN_25
DSS_CALC__USER_ROI_SPAD_EN_26
DSS_CALC__USER_ROI_SPAD_EN_27
DSS_CALC__USER_ROI_SPAD_EN_28
DSS_CALC__USER_ROI_SPAD_EN_29
DSS_CALC__USER_ROI_SPAD_EN_30
DSS_CALC__USER_ROI_SPAD_EN_31
DSS_CONFIG__APERTURE_ATTENUATION
DSS_CONFIG__MANUAL_BLOCK_SELECT
DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT
DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI
DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO
DSS_CONFIG__MAX_SPADS_LIMIT
DSS_CONFIG__MIN_SPADS_LIMIT
DSS_CONFIG__ROI_MODE_CONTROL
DSS_CONFIG__TARGET_TOTAL_RATE_MCPS
DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_HI
DSS_CONFIG__TARGET_TOTAL_RATE_MCPS_LO
DSS_RESULT__ENABLED_BLOCKS
DSS_RESULT__NUM_REQUESTED_SPADS
DSS_RESULT__NUM_REQUESTED_SPADS_HI
DSS_RESULT__NUM_REQUESTED_SPADS_LO
DSS_RESULT__TOTAL_RATE_PER_SPAD
DSS_RESULT__TOTAL_RATE_PER_SPAD_HI
DSS_RESULT__TOTAL_RATE_PER_SPAD_LO
FIRMWARE__CAL_REPEAT_RATE_COUNTER
FIRMWARE__CAL_REPEAT_RATE_COUNTER_HI
FIRMWARE__CAL_REPEAT_RATE_COUNTER_LO
FIRMWARE__ENABLE
FIRMWARE__HISTOGRAM_BIN
FIRMWARE__INTERNAL_STREAM_COUNTER_VAL
FIRMWARE__INTERNAL_STREAM_COUNT_DIV
FIRMWARE__MODE_STATUS
FIRMWARE__SECONDARY_MODE_STATUS
FIRMWARE__SYSTEM_STATUS
GLOBAL_CONFIG__REF_EN_START_SELECT
GLOBAL_CONFIG__SPAD_ENABLES_REF_0
GLOBAL_CONFIG__SPAD_ENABLES_REF_1
GLOBAL_CONFIG__SPAD_ENABLES_REF_2
GLOBAL_CONFIG__SPAD_ENABLES_REF_3
GLOBAL_CONFIG__SPAD_ENABLES_REF_4
GLOBAL_CONFIG__SPAD_ENABLES_REF_5
GLOBAL_CONFIG__SPAD_ENABLES_RTN_0
GLOBAL_CONFIG__SPAD_ENABLES_RTN_1
GLOBAL_CONFIG__SPAD_ENABLES_RTN_2
GLOBAL_CONFIG__SPAD_ENABLES_RTN_3
GLOBAL_CONFIG__SPAD_ENABLES_RTN_4
GLOBAL_CONFIG__SPAD_ENABLES_RTN_5
GLOBAL_CONFIG__SPAD_ENABLES_RTN_6
GLOBAL_CONFIG__SPAD_ENABLES_RTN_7
GLOBAL_CONFIG__SPAD_ENABLES_RTN_8
GLOBAL_CONFIG__SPAD_ENABLES_RTN_9
GLOBAL_CONFIG__SPAD_ENABLES_RTN_10
GLOBAL_CONFIG__SPAD_ENABLES_RTN_11
GLOBAL_CONFIG__SPAD_ENABLES_RTN_12
GLOBAL_CONFIG__SPAD_ENABLES_RTN_13
GLOBAL_CONFIG__SPAD_ENABLES_RTN_14
GLOBAL_CONFIG__SPAD_ENABLES_RTN_15
GLOBAL_CONFIG__SPAD_ENABLES_RTN_16
GLOBAL_CONFIG__SPAD_ENABLES_RTN_17
GLOBAL_CONFIG__SPAD_ENABLES_RTN_18
GLOBAL_CONFIG__SPAD_ENABLES_RTN_19
GLOBAL_CONFIG__SPAD_ENABLES_RTN_20
GLOBAL_CONFIG__SPAD_ENABLES_RTN_21
GLOBAL_CONFIG__SPAD_ENABLES_RTN_22
GLOBAL_CONFIG__SPAD_ENABLES_RTN_23
GLOBAL_CONFIG__SPAD_ENABLES_RTN_24
GLOBAL_CONFIG__SPAD_ENABLES_RTN_25
GLOBAL_CONFIG__SPAD_ENABLES_RTN_26
GLOBAL_CONFIG__SPAD_ENABLES_RTN_27
GLOBAL_CONFIG__SPAD_ENABLES_RTN_28
GLOBAL_CONFIG__SPAD_ENABLES_RTN_29
GLOBAL_CONFIG__SPAD_ENABLES_RTN_30
GLOBAL_CONFIG__SPAD_ENABLES_RTN_31
GLOBAL_CONFIG__STREAM_DIVIDER
GLOBAL_CONFIG__VCSEL_WIDTH
GO2_HOST_BANK_ACCESS__OVERRIDE
GPH_CONFIG__STREAM_COUNT_UPDATE_VALUE
GPH__DSS_CONFIG__MANUAL_BLOCK_SELECT
GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT
GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_HI
GPH__DSS_CONFIG__MANUAL_EFFECTIVE_SPADS_SELECT_LO
GPH__DSS_CONFIG__MAX_SPADS_LIMIT
GPH__DSS_CONFIG__MIN_SPADS_LIMIT
GPH__DSS_CONFIG__ROI_MODE_CONTROL
GPH__GPH_ID
GPH__MM_CONFIG__TIMEOUT_MACROP_A_HI
GPH__MM_CONFIG__TIMEOUT_MACROP_A_LO
GPH__MM_CONFIG__TIMEOUT_MACROP_B_HI
GPH__MM_CONFIG__TIMEOUT_MACROP_B_LO
GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS
GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI
GPH__RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO
GPH__RANGE_CONFIG__SIGMA_THRESH
GPH__RANGE_CONFIG__SIGMA_THRESH_HI
GPH__RANGE_CONFIG__SIGMA_THRESH_LO
GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_HI
GPH__RANGE_CONFIG__TIMEOUT_MACROP_A_LO
GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_HI
GPH__RANGE_CONFIG__TIMEOUT_MACROP_B_LO
GPH__RANGE_CONFIG__VALID_PHASE_HIGH
GPH__RANGE_CONFIG__VALID_PHASE_LOW
GPH__RANGE_CONFIG__VCSEL_PERIOD_A
GPH__RANGE_CONFIG__VCSEL_PERIOD_B
GPH__ROI_CONFIG__USER_ROI_CENTRE_SPAD
GPH__ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE
GPH__SD_CONFIG__FIRST_ORDER_SELECT
GPH__SD_CONFIG__INITIAL_PHASE_SD0
GPH__SD_CONFIG__INITIAL_PHASE_SD1
GPH__SD_CONFIG__QUANTIFIER
GPH__SD_CONFIG__WOI_SD0
GPH__SD_CONFIG__WOI_SD1
GPH__SPARE_0
GPH__SYSTEM__ENABLE_XTALK_PER_QUADRANT
GPH__SYSTEM__INTERRUPT_CONFIG_GPIO
GPH__SYSTEM__SEQUENCE_CONFIG
GPH__SYSTEM__THRESH_HIGH
GPH__SYSTEM__THRESH_HIGH_HI
GPH__SYSTEM__THRESH_HIGH_LO
GPH__SYSTEM__THRESH_LOW
GPH__SYSTEM__THRESH_LOW_HI
GPH__SYSTEM__THRESH_LOW_LO
GPH__SYSTEM__THRESH_RATE_HIGH
GPH__SYSTEM__THRESH_RATE_HIGH_HI
GPH__SYSTEM__THRESH_RATE_HIGH_LO
GPH__SYSTEM__THRESH_RATE_LOW
GPH__SYSTEM__THRESH_RATE_LOW_HI
GPH__SYSTEM__THRESH_RATE_LOW_LO
GPIO_HV_MUX__CTRL
GPIO_HV_PAD__CTRL
GPIO_LV_MUX__CTRL
GPIO_LV_PAD__CTRL
GPIO__FIO_HV_STATUS
GPIO__TIO_HV_STATUS
HOST_IF__STATUS
HOST_IF__STATUS_GO1
I2C_SLAVE__DEVICE_ADDRESS
IDENTIFICATION__MODEL_ID
IDENTIFICATION__MODULE_ID
IDENTIFICATION__MODULE_ID_HI
IDENTIFICATION__MODULE_ID_LO
IDENTIFICATION__MODULE_TYPE
IDENTIFICATION__REVISION_ID
INTERRUPT_MANAGER__CLEAR
INTERRUPT_MANAGER__ENABLES
INTERRUPT_MANAGER__STATUS
INTERRUPT_SCHEDULER__DATA_OUT
INTERRUPT_SCHEDULER__DATA_OUT_0
INTERRUPT_SCHEDULER__DATA_OUT_1
INTERRUPT_SCHEDULER__DATA_OUT_2
INTERRUPT_SCHEDULER__DATA_OUT_3
LASER_SAFETY__CLIP
LASER_SAFETY__KEY
LASER_SAFETY__KEY_RO
LASER_SAFETY__MULT
MCU_CLK_GATING__CTRL
MCU_GENERAL_PURPOSE__GP_0
MCU_GENERAL_PURPOSE__GP_1
MCU_GENERAL_PURPOSE__GP_2
MCU_GENERAL_PURPOSE__GP_3
MCU_RANGE_CALC__ALGO_ACCUM_PHASE
MCU_RANGE_CALC__ALGO_ACCUM_PHASE_0
MCU_RANGE_CALC__ALGO_ACCUM_PHASE_1
MCU_RANGE_CALC__ALGO_ACCUM_PHASE_2
MCU_RANGE_CALC__ALGO_ACCUM_PHASE_3
MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD
MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_HI
MCU_RANGE_CALC__ALGO_ADJUST_VCSEL_PERIOD_LO
MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS
MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_0
MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_1
MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_2
MCU_RANGE_CALC__ALGO_AMBIENT_EVENTS_3
MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS
MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_0
MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_1
MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_2
MCU_RANGE_CALC__ALGO_SIGNAL_EVENTS_3
MCU_RANGE_CALC__ALGO_TOTAL_PERIODS
MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_HI
MCU_RANGE_CALC__ALGO_TOTAL_PERIODS_LO
MCU_RANGE_CALC__ALGO_VCSEL_PERIOD
MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC
MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_HI
MCU_RANGE_CALC__AMBIENT_DURATION_PRE_CALC_LO
MCU_RANGE_CALC__AMBIENT_RATE_MCPS
MCU_RANGE_CALC__AMBIENT_RATE_MCPS_HI
MCU_RANGE_CALC__AMBIENT_RATE_MCPS_LO
MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS
MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_HI
MCU_RANGE_CALC__AVG_SIGNAL_RATE_MCPS_LO
MCU_RANGE_CALC__CALC_STATUS
MCU_RANGE_CALC__CONFIG
MCU_RANGE_CALC__DEBUG
MCU_RANGE_CALC__NUM_SPADS
MCU_RANGE_CALC__NUM_SPADS_HI
MCU_RANGE_CALC__NUM_SPADS_LO
MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE
MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_HI
MCU_RANGE_CALC__OFFSET_CORRECTED_RANGE_LO
MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS
MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_HI
MCU_RANGE_CALC__PEAK_SIGNAL_RATE_MCPS_LO
MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS
MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_HI
MCU_RANGE_CALC__PEAK_SIGNAL_RATE_XTALK_CORR_MCPS_LO
MCU_RANGE_CALC__PHASE_OUTPUT
MCU_RANGE_CALC__PHASE_OUTPUT_HI
MCU_RANGE_CALC__PHASE_OUTPUT_LO
MCU_RANGE_CALC__RATE_PER_SPAD_MCPS
MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_0
MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_1
MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_2
MCU_RANGE_CALC__RATE_PER_SPAD_MCPS_3
MCU_RANGE_CALC__SPARE_0
MCU_RANGE_CALC__SPARE_1
MCU_RANGE_CALC__SPARE_2
MCU_RANGE_CALC__SPARE_3
MCU_RANGE_CALC__SPARE_4
MCU_RANGE_CALC__SPARE_4_0
MCU_RANGE_CALC__SPARE_4_1
MCU_RANGE_CALC__SPARE_4_2
MCU_RANGE_CALC__SPARE_4_3
MCU_RANGE_CALC__SPARE_5
MCU_RANGE_CALC__SPARE_6
MCU_RANGE_CALC__SPARE_6_HI
MCU_RANGE_CALC__SPARE_6_LO
MCU_RANGE_CALC__SPARE_7
MCU_RANGE_CALC__SPARE_8
MCU_RANGE_CALC__XTALK
MCU_RANGE_CALC__XTALK_HI
MCU_RANGE_CALC__XTALK_LO
MCU_TO_HOST_BANK__WR_ACCESS_EN
MCU_UTIL_DIVIDER__DIVIDEND
MCU_UTIL_DIVIDER__DIVIDEND_0
MCU_UTIL_DIVIDER__DIVIDEND_1
MCU_UTIL_DIVIDER__DIVIDEND_2
MCU_UTIL_DIVIDER__DIVIDEND_3
MCU_UTIL_DIVIDER__DIVISOR
MCU_UTIL_DIVIDER__DIVISOR_0
MCU_UTIL_DIVIDER__DIVISOR_1
MCU_UTIL_DIVIDER__DIVISOR_2
MCU_UTIL_DIVIDER__DIVISOR_3
MCU_UTIL_DIVIDER__QUOTIENT
MCU_UTIL_DIVIDER__QUOTIENT_0
MCU_UTIL_DIVIDER__QUOTIENT_1
MCU_UTIL_DIVIDER__QUOTIENT_2
MCU_UTIL_DIVIDER__QUOTIENT_3
MCU_UTIL_DIVIDER__START
MCU_UTIL_DIVIDER__STATUS
MCU_UTIL_MULTIPLIER__MULTIPLICAND
MCU_UTIL_MULTIPLIER__MULTIPLICAND_0
MCU_UTIL_MULTIPLIER__MULTIPLICAND_1
MCU_UTIL_MULTIPLIER__MULTIPLICAND_2
MCU_UTIL_MULTIPLIER__MULTIPLICAND_3
MCU_UTIL_MULTIPLIER__MULTIPLIER
MCU_UTIL_MULTIPLIER__MULTIPLIER_0
MCU_UTIL_MULTIPLIER__MULTIPLIER_1
MCU_UTIL_MULTIPLIER__MULTIPLIER_2
MCU_UTIL_MULTIPLIER__MULTIPLIER_3
MCU_UTIL_MULTIPLIER__PRODUCT_HI
MCU_UTIL_MULTIPLIER__PRODUCT_HI_0
MCU_UTIL_MULTIPLIER__PRODUCT_HI_1
MCU_UTIL_MULTIPLIER__PRODUCT_HI_2
MCU_UTIL_MULTIPLIER__PRODUCT_HI_3
MCU_UTIL_MULTIPLIER__PRODUCT_LO
MCU_UTIL_MULTIPLIER__PRODUCT_LO_0
MCU_UTIL_MULTIPLIER__PRODUCT_LO_1
MCU_UTIL_MULTIPLIER__PRODUCT_LO_2
MCU_UTIL_MULTIPLIER__PRODUCT_LO_3
MCU_UTIL_MULTIPLIER__START
MCU_UTIL_MULTIPLIER__STATUS
MM_CONFIG__INNER_OFFSET_MM
MM_CONFIG__INNER_OFFSET_MM_HI
MM_CONFIG__INNER_OFFSET_MM_LO
MM_CONFIG__OUTER_OFFSET_MM
MM_CONFIG__OUTER_OFFSET_MM_HI
MM_CONFIG__OUTER_OFFSET_MM_LO
MM_CONFIG__TIMEOUT_MACROP_A_HI
MM_CONFIG__TIMEOUT_MACROP_A_LO
MM_CONFIG__TIMEOUT_MACROP_B_HI
MM_CONFIG__TIMEOUT_MACROP_B_LO
MM_RESULT__INNER_INTERSECTION_RATE
MM_RESULT__INNER_INTERSECTION_RATE_HI
MM_RESULT__INNER_INTERSECTION_RATE_LO
MM_RESULT__OUTER_COMPLEMENT_RATE
MM_RESULT__OUTER_COMPLEMENT_RATE_HI
MM_RESULT__OUTER_COMPLEMENT_RATE_LO
MM_RESULT__TOTAL_OFFSET
MM_RESULT__TOTAL_OFFSET_HI
MM_RESULT__TOTAL_OFFSET_LO
NVM_BIST__COMPLETE
NVM_BIST__CTRL
NVM_BIST__NUM_NVM_WORDS
NVM_BIST__START_ADDRESS
NVM_BIST__STATUS
OSC_MEASURED__FAST_OSC__FREQUENCY
OSC_MEASURED__FAST_OSC__FREQUENCY_HI
OSC_MEASURED__FAST_OSC__FREQUENCY_LO
PAD_I2C_HV__CONFIG
PAD_I2C_HV__EXTSUP_CONFIG
PAD_I2C_LV__CONFIG
PAD_STARTUP_MODE__VALUE_CTRL
PAD_STARTUP_MODE__VALUE_RO
PAD_STARTUP_MODE__VALUE_RO_GO1
PATCH__ADDRESS_0
PATCH__ADDRESS_0_HI
PATCH__ADDRESS_0_LO
PATCH__ADDRESS_1
PATCH__ADDRESS_1_HI
PATCH__ADDRESS_1_LO
PATCH__ADDRESS_2
PATCH__ADDRESS_2_HI
PATCH__ADDRESS_2_LO
PATCH__ADDRESS_3
PATCH__ADDRESS_3_HI
PATCH__ADDRESS_3_LO
PATCH__ADDRESS_4
PATCH__ADDRESS_4_HI
PATCH__ADDRESS_4_LO
PATCH__ADDRESS_5
PATCH__ADDRESS_5_HI
PATCH__ADDRESS_5_LO
PATCH__ADDRESS_6
PATCH__ADDRESS_6_HI
PATCH__ADDRESS_6_LO
PATCH__ADDRESS_7
PATCH__ADDRESS_7_HI
PATCH__ADDRESS_7_LO
PATCH__ADDRESS_8
PATCH__ADDRESS_8_HI
PATCH__ADDRESS_8_LO
PATCH__ADDRESS_9
PATCH__ADDRESS_9_HI
PATCH__ADDRESS_9_LO
PATCH__ADDRESS_10
PATCH__ADDRESS_10_HI
PATCH__ADDRESS_10_LO
PATCH__ADDRESS_11
PATCH__ADDRESS_11_HI
PATCH__ADDRESS_11_LO
PATCH__ADDRESS_12
PATCH__ADDRESS_12_HI
PATCH__ADDRESS_12_LO
PATCH__ADDRESS_13
PATCH__ADDRESS_13_HI
PATCH__ADDRESS_13_LO
PATCH__ADDRESS_14
PATCH__ADDRESS_14_HI
PATCH__ADDRESS_14_LO
PATCH__ADDRESS_15
PATCH__ADDRESS_15_HI
PATCH__ADDRESS_15_LO
PATCH__CTRL
PATCH__DATA_ENABLES
PATCH__DATA_ENABLES_HI
PATCH__DATA_ENABLES_LO
PATCH__JMP_ENABLES
PATCH__JMP_ENABLES_HI
PATCH__JMP_ENABLES_LO
PATCH__OFFSET_0
PATCH__OFFSET_0_HI
PATCH__OFFSET_0_LO
PATCH__OFFSET_1
PATCH__OFFSET_1_HI
PATCH__OFFSET_1_LO
PATCH__OFFSET_2
PATCH__OFFSET_2_HI
PATCH__OFFSET_2_LO
PATCH__OFFSET_3
PATCH__OFFSET_3_HI
PATCH__OFFSET_3_LO
PATCH__OFFSET_4
PATCH__OFFSET_4_HI
PATCH__OFFSET_4_LO
PATCH__OFFSET_5
PATCH__OFFSET_5_HI
PATCH__OFFSET_5_LO
PATCH__OFFSET_6
PATCH__OFFSET_6_HI
PATCH__OFFSET_6_LO
PATCH__OFFSET_7
PATCH__OFFSET_7_HI
PATCH__OFFSET_7_LO
PATCH__OFFSET_8
PATCH__OFFSET_8_HI
PATCH__OFFSET_8_LO
PATCH__OFFSET_9
PATCH__OFFSET_9_HI
PATCH__OFFSET_9_LO
PATCH__OFFSET_10
PATCH__OFFSET_10_HI
PATCH__OFFSET_10_LO
PATCH__OFFSET_11
PATCH__OFFSET_11_HI
PATCH__OFFSET_11_LO
PATCH__OFFSET_12
PATCH__OFFSET_12_HI
PATCH__OFFSET_12_LO
PATCH__OFFSET_13
PATCH__OFFSET_13_HI
PATCH__OFFSET_13_LO
PATCH__OFFSET_14
PATCH__OFFSET_14_HI
PATCH__OFFSET_14_LO
PATCH__OFFSET_15
PATCH__OFFSET_15_HI
PATCH__OFFSET_15_LO
PHASECAL_CONFIG__OVERRIDE
PHASECAL_CONFIG__TARGET
PHASECAL_CONFIG__TIMEOUT_MACROP
PHASECAL_RESULT__PHASE_OUTPUT_REF
PHASECAL_RESULT__PHASE_OUTPUT_REF_HI
PHASECAL_RESULT__PHASE_OUTPUT_REF_LO
PHASECAL_RESULT__REFERENCE_PHASE
PHASECAL_RESULT__REFERENCE_PHASE_HI
PHASECAL_RESULT__REFERENCE_PHASE_LO
PHASECAL_RESULT__VCSEL_START
PLL_PERIOD_US
PLL_PERIOD_US_0
PLL_PERIOD_US_1
PLL_PERIOD_US_2
PLL_PERIOD_US_3
POWER_MANAGEMENT__GO1_POWER_FORCE
POWER_MANAGEMENT__GO1_RESET_STATUS
PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0
PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1
PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2
PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3
PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1
PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0
PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1
PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2
PREV_SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3
PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0
PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0
PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1
PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2
PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3
PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1
PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0
PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1
PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2
PREV_SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3
PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0
PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0
PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1
PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2
PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3
PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1
PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0
PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1
PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2
PREV_SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3
PREV_SHADOW_RESULT_CORE__SPARE_0
PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0
PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0
PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1
PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2
PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3
PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1
PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0
PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1
PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2
PREV_SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3
PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0
PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI
PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO
PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1
PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI
PREV_SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO
PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0
PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI
PREV_SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO
PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0
PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI
PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO
PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1
PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI
PREV_SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO
PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0
PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI
PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO
PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1
PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI
PREV_SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO
PREV_SHADOW_RESULT__INTERRUPT_STATUS
PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0
PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI
PREV_SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO
PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0
PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI
PREV_SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO
PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0
PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI
PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO
PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0
PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI
PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO
PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1
PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI
PREV_SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO
PREV_SHADOW_RESULT__PHASE_SD0
PREV_SHADOW_RESULT__PHASE_SD0_HI
PREV_SHADOW_RESULT__PHASE_SD0_LO
PREV_SHADOW_RESULT__PHASE_SD1
PREV_SHADOW_RESULT__PHASE_SD1_HI
PREV_SHADOW_RESULT__PHASE_SD1_LO
PREV_SHADOW_RESULT__RANGE_STATUS
PREV_SHADOW_RESULT__REPORT_STATUS
PREV_SHADOW_RESULT__SIGMA_SD0
PREV_SHADOW_RESULT__SIGMA_SD0_HI
PREV_SHADOW_RESULT__SIGMA_SD0_LO
PREV_SHADOW_RESULT__SIGMA_SD1
PREV_SHADOW_RESULT__SIGMA_SD1_HI
PREV_SHADOW_RESULT__SIGMA_SD1_LO
PREV_SHADOW_RESULT__SPARE_0_SD1
PREV_SHADOW_RESULT__SPARE_0_SD1_HI
PREV_SHADOW_RESULT__SPARE_0_SD1_LO
PREV_SHADOW_RESULT__SPARE_1_SD1
PREV_SHADOW_RESULT__SPARE_1_SD1_HI
PREV_SHADOW_RESULT__SPARE_1_SD1_LO
PREV_SHADOW_RESULT__SPARE_2_SD1
PREV_SHADOW_RESULT__SPARE_2_SD1_HI
PREV_SHADOW_RESULT__SPARE_2_SD1_LO
PREV_SHADOW_RESULT__SPARE_3_SD1
PREV_SHADOW_RESULT__SPARE_3_SD1_HI
PREV_SHADOW_RESULT__SPARE_3_SD1_LO
PREV_SHADOW_RESULT__STREAM_COUNT
PRIVATE__PATCH_BASE_ADDR_RSLV
PROTECTED_LASER_SAFETY__LOCK_BIT
RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS
RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_HI
RANGE_CONFIG__MIN_COUNT_RATE_RTN_LIMIT_MCPS_LO
RANGE_CONFIG__SIGMA_THRESH
RANGE_CONFIG__SIGMA_THRESH_HI
RANGE_CONFIG__SIGMA_THRESH_LO
RANGE_CONFIG__TIMEOUT_MACROP_A_HI
RANGE_CONFIG__TIMEOUT_MACROP_A_LO
RANGE_CONFIG__TIMEOUT_MACROP_B_HI
RANGE_CONFIG__TIMEOUT_MACROP_B_LO
RANGE_CONFIG__VALID_PHASE_HIGH
RANGE_CONFIG__VALID_PHASE_LOW
RANGE_CONFIG__VCSEL_PERIOD_A
RANGE_CONFIG__VCSEL_PERIOD_B
RANGE_RESULT__ACCUM_PHASE
RANGE_RESULT__ACCUM_PHASE_0
RANGE_RESULT__ACCUM_PHASE_1
RANGE_RESULT__ACCUM_PHASE_2
RANGE_RESULT__ACCUM_PHASE_3
RANGE_RESULT__OFFSET_CORRECTED_RANGE
RANGE_RESULT__OFFSET_CORRECTED_RANGE_HI
RANGE_RESULT__OFFSET_CORRECTED_RANGE_LO
RANGING_CORE__AMBIENT_MISMATCH_LL
RANGING_CORE__AMBIENT_MISMATCH_LM
RANGING_CORE__AMBIENT_MISMATCH_MM
RANGING_CORE__AMBIENT_MISMATCH_REF_LL
RANGING_CORE__AMBIENT_MISMATCH_REF_LM
RANGING_CORE__AMBIENT_MISMATCH_REF_MM
RANGING_CORE__AMBIENT_OFFSET_1_LSB
RANGING_CORE__AMBIENT_OFFSET_1_MSB
RANGING_CORE__AMBIENT_OFFSET_REF_1_LSB
RANGING_CORE__AMBIENT_OFFSET_REF_1_MSB
RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLL
RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LLM
RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_LMM
RANGING_CORE__AMBIENT_WINDOW_EVENTS_1_MMM
RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLL
RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LLM
RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_LMM
RANGING_CORE__AMBIENT_WINDOW_EVENTS_REF_1_MMM
RANGING_CORE__CALIB_1
RANGING_CORE__CALIB_2
RANGING_CORE__CALIB_2__A0
RANGING_CORE__CALIB_3
RANGING_CORE__CLK_CTRL1
RANGING_CORE__CLK_CTRL2
RANGING_CORE__CPUMP_1
RANGING_CORE__CPUMP_1__A0
RANGING_CORE__CPUMP_2
RANGING_CORE__CPUMP_3
RANGING_CORE__CUSTOM_FE
RANGING_CORE__CUSTOM_FE_2
RANGING_CORE__CUSTOM_FE_2__A0
RANGING_CORE__DEVICE_ID
RANGING_CORE__FILTER_STRENGTH_1
RANGING_CORE__FILTER_STRENGTH_REF_1
RANGING_CORE__FORCE_CONTINUOUS_AMBIENT
RANGING_CORE__FORCE_DN_IN
RANGING_CORE__FORCE_HW
RANGING_CORE__FORCE_UP_IN
RANGING_CORE__GPIO_CONFIG__A0
RANGING_CORE__GPIO_DIR
RANGING_CORE__GPIO_OUT_TESTMUX
RANGING_CORE__HIGH_LIMIT_1
RANGING_CORE__HIGH_LIMIT_REF_1
RANGING_CORE__INITIAL_PHASE_VALUE_1
RANGING_CORE__INITIAL_PHASE_VALUE_REF_1
RANGING_CORE__INTR_MANAGER__A0
RANGING_CORE__INVERT_HW
RANGING_CORE__INVERT_UP_DN
RANGING_CORE__LASER_CONTINUITY_STATE
RANGING_CORE__LASER_SAFETY_2
RANGING_CORE__LOW_LIMIT_1
RANGING_CORE__LOW_LIMIT_REF_1
RANGING_CORE__MONITOR_UP_DN
RANGING_CORE__NVM_CTRL__ADDR
RANGING_CORE__NVM_CTRL__DATAIN_LLL
RANGING_CORE__NVM_CTRL__DATAIN_LLM
RANGING_CORE__NVM_CTRL__DATAIN_LMM
RANGING_CORE__NVM_CTRL__DATAIN_MMM
RANGING_CORE__NVM_CTRL__DATAOUT_ECC
RANGING_CORE__NVM_CTRL__DATAOUT_LLL
RANGING_CORE__NVM_CTRL__DATAOUT_LLM
RANGING_CORE__NVM_CTRL__DATAOUT_LMM
RANGING_CORE__NVM_CTRL__DATAOUT_MMM
RANGING_CORE__NVM_CTRL__HV_FALL_LSB
RANGING_CORE__NVM_CTRL__HV_FALL_MSB
RANGING_CORE__NVM_CTRL__HV_RISE_LSB
RANGING_CORE__NVM_CTRL__HV_RISE_MSB
RANGING_CORE__NVM_CTRL__MODE
RANGING_CORE__NVM_CTRL__PDN
RANGING_CORE__NVM_CTRL__PROGN
RANGING_CORE__NVM_CTRL__PULSE_WIDTH_LSB
RANGING_CORE__NVM_CTRL__PULSE_WIDTH_MSB
RANGING_CORE__NVM_CTRL__READN
RANGING_CORE__NVM_CTRL__TESTREAD
RANGING_CORE__NVM_CTRL__TST
RANGING_CORE__OSC_1
RANGING_CORE__PLL_1
RANGING_CORE__PLL_2
RANGING_CORE__POWER_FSM_TIME_OSC__A0
RANGING_CORE__QUANTIFIER_1_LSB
RANGING_CORE__QUANTIFIER_1_MSB
RANGING_CORE__QUANTIFIER_REF_1_LSB
RANGING_CORE__QUANTIFIER_REF_1_MSB
RANGING_CORE__RANGE_1_LLL
RANGING_CORE__RANGE_1_LLM
RANGING_CORE__RANGE_1_LMM
RANGING_CORE__RANGE_1_MMM
RANGING_CORE__RANGE_REF_1_LLL
RANGING_CORE__RANGE_REF_1_LLM
RANGING_CORE__RANGE_REF_1_LMM
RANGING_CORE__RANGE_REF_1_MMM
RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLL
RANGING_CORE__RANGING_TOTAL_EVENTS_1_LLM
RANGING_CORE__RANGING_TOTAL_EVENTS_1_LMM
RANGING_CORE__RANGING_TOTAL_EVENTS_1_MMM
RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLL
RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LLM
RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_LMM
RANGING_CORE__RANGING_TOTAL_EVENTS_REF_1_MMM
RANGING_CORE__READOUT_CFG__A0
RANGING_CORE__REFERENCE_1
RANGING_CORE__REFERENCE_2__A0
RANGING_CORE__REFERENCE_3
RANGING_CORE__REFERENCE_4
RANGING_CORE__REFERENCE_5
RANGING_CORE__REF_EN_START_SELECT
RANGING_CORE__REF_SPAD_EN_0__EWOK
RANGING_CORE__REF_SPAD_EN_1__EWOK
RANGING_CORE__REF_SPAD_EN_2__EWOK
RANGING_CORE__REF_SPAD_EN_3__EWOK
RANGING_CORE__REF_SPAD_EN_4__EWOK
RANGING_CORE__REF_SPAD_EN_5__EWOK
RANGING_CORE__REGAVDD1V2
RANGING_CORE__REGAVDD1V2__A0
RANGING_CORE__REGDVDD1V2_ATEST__EWOK
RANGING_CORE__RESET_CONTROL__A0
RANGING_CORE__RET_SPAD_EN_0
RANGING_CORE__RET_SPAD_EN_1
RANGING_CORE__RET_SPAD_EN_2
RANGING_CORE__RET_SPAD_EN_3
RANGING_CORE__RET_SPAD_EN_4
RANGING_CORE__RET_SPAD_EN_5
RANGING_CORE__RET_SPAD_EN_6
RANGING_CORE__RET_SPAD_EN_7
RANGING_CORE__RET_SPAD_EN_8
RANGING_CORE__RET_SPAD_EN_9
RANGING_CORE__RET_SPAD_EN_10
RANGING_CORE__RET_SPAD_EN_11
RANGING_CORE__RET_SPAD_EN_12
RANGING_CORE__RET_SPAD_EN_13
RANGING_CORE__RET_SPAD_EN_14
RANGING_CORE__RET_SPAD_EN_15
RANGING_CORE__RET_SPAD_EN_16
RANGING_CORE__RET_SPAD_EN_17
RANGING_CORE__RET_SPAD_EN_18
RANGING_CORE__RET_SPAD_EN_19
RANGING_CORE__RET_SPAD_EN_20
RANGING_CORE__RET_SPAD_EN_21
RANGING_CORE__RET_SPAD_EN_22
RANGING_CORE__RET_SPAD_EN_23
RANGING_CORE__RET_SPAD_EN_24
RANGING_CORE__RET_SPAD_EN_25
RANGING_CORE__RET_SPAD_EN_26
RANGING_CORE__RET_SPAD_EN_27
RANGING_CORE__RET_SPAD_EN_28
RANGING_CORE__RET_SPAD_EN_29
RANGING_CORE__RET_SPAD_EN_30
RANGING_CORE__RET_SPAD_EN_31
RANGING_CORE__REVISION_ID
RANGING_CORE__SIGNAL_EVENT_LIMIT_1_LSB
RANGING_CORE__SIGNAL_EVENT_LIMIT_1_MSB
RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_LSB
RANGING_CORE__SIGNAL_EVENT_LIMIT_REF_1_MSB
RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLL
RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LLM
RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_LMM
RANGING_CORE__SIGNAL_TOTAL_EVENTS_1_MMM
RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLL
RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LLM
RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_LMM
RANGING_CORE__SIGNAL_TOTAL_EVENTS_REF_1_MMM
RANGING_CORE__SPAD_DISABLE_CTRL
RANGING_CORE__SPAD_EN_SHIFT_OUT_DEBUG
RANGING_CORE__SPAD_PS
RANGING_CORE__SPAD_READOUT
RANGING_CORE__SPAD_READOUT_1
RANGING_CORE__SPAD_READOUT_2
RANGING_CORE__SPAD_READOUT__A0
RANGING_CORE__SPAD_SHIFT_EN
RANGING_CORE__SPARE_REGISTER__A0
RANGING_CORE__SPI_MODE
RANGING_CORE__START_RANGING
RANGING_CORE__STATIC_DN_VALUE_1
RANGING_CORE__STATIC_DN_VALUE_REF_1
RANGING_CORE__STATIC_HW_VALUE
RANGING_CORE__STATIC_UP_VALUE_1
RANGING_CORE__STATIC_UP_VALUE_REF_1
RANGING_CORE__STATUS
RANGING_CORE__STATUS_RESET__A0
RANGING_CORE__STOP_CONDITION__A0
RANGING_CORE__TEST_PHASE_SELECT_TO_FILTER
RANGING_CORE__TEST_PHASE_SELECT_TO_TIMING_GEN
RANGING_CORE__TIMEOUT_OVERALL_PERIODS_LSB
RANGING_CORE__TIMEOUT_OVERALL_PERIODS_MSB
RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LL
RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_LM
RANGING_CORE__TOTAL_PERIODS_ELAPSED_1_MM
RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LL
RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_LM
RANGING_CORE__TOTAL_PERIODS_ELAPSED_REF_1_MM
RANGING_CORE__TST_MUX
RANGING_CORE__TST_MUX_SEL1
RANGING_CORE__TST_MUX_SEL2
RANGING_CORE__TST_MUX__A0
RANGING_CORE__VCSEL_1
RANGING_CORE__VCSEL_ATEST__A0
RANGING_CORE__VCSEL_CONT_STAGE5_BYPASS__A0
RANGING_CORE__VCSEL_DELAY__A0
RANGING_CORE__VCSEL_PERIOD
RANGING_CORE__VCSEL_PERIOD_CLIPPED__A0
RANGING_CORE__VCSEL_START
RANGING_CORE__VCSEL_STATUS
RANGING_CORE__VCSEL_STOP
RANGING_CORE__VCSEL_STOP_CLIPPED__A0
RANGING_CORE__WINDOW_SETTING__A0
RANGING_CORE__WOI_1
RANGING_CORE__WOI_REF_1
REF_SPAD_CHAR_RESULT__NUM_ACTUAL_REF_SPADS
REF_SPAD_CHAR_RESULT__REF_LOCATION
REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS
REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_HI
REF_SPAD_CHAR__TOTAL_RATE_TARGET_MCPS_LO
REF_SPAD_MAN__NUM_REQUESTED_REF_SPADS
REF_SPAD_MAN__REF_LOCATION
RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0
RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1
RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2
RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3
RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1
RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0
RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1
RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2
RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3
RESULT_CORE__RANGING_TOTAL_EVENTS_SD0
RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0
RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1
RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2
RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3
RESULT_CORE__RANGING_TOTAL_EVENTS_SD1
RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0
RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1
RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2
RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3
RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0
RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0
RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1
RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2
RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3
RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1
RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0
RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1
RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2
RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3
RESULT_CORE__SPARE_0
RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0
RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0
RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1
RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2
RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3
RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1
RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0
RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1
RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2
RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3
RESULT__AMBIENT_COUNT_RATE_MCPS_SD0
RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI
RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO
RESULT__AMBIENT_COUNT_RATE_MCPS_SD1
RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI
RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO
RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0
RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI
RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO
RESULT__DEBUG_STAGE
RESULT__DEBUG_STATUS
RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0
RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI
RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO
RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1
RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI
RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO
RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0
RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI
RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO
RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1
RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI
RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO
RESULT__INTERRUPT_STATUS
RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0
RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI
RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO
RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0
RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI
RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO
RESULT__OSC_CALIBRATE_VAL
RESULT__OSC_CALIBRATE_VAL_HI
RESULT__OSC_CALIBRATE_VAL_LO
RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0
RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI
RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO
RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0
RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI
RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO
RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1
RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI
RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO
RESULT__PHASE_SD0
RESULT__PHASE_SD0_HI
RESULT__PHASE_SD0_LO
RESULT__PHASE_SD1
RESULT__PHASE_SD1_HI
RESULT__PHASE_SD1_LO
RESULT__RANGE_STATUS
RESULT__REPORT_STATUS
RESULT__SIGMA_SD0
RESULT__SIGMA_SD0_HI
RESULT__SIGMA_SD0_LO
RESULT__SIGMA_SD1
RESULT__SIGMA_SD1_HI
RESULT__SIGMA_SD1_LO
RESULT__SPARE_0_SD1
RESULT__SPARE_0_SD1_HI
RESULT__SPARE_0_SD1_LO
RESULT__SPARE_1_SD1
RESULT__SPARE_1_SD1_HI
RESULT__SPARE_1_SD1_LO
RESULT__SPARE_2_SD1
RESULT__SPARE_2_SD1_HI
RESULT__SPARE_2_SD1_LO
RESULT__SPARE_3_SD1
RESULT__STREAM_COUNT
RESULT__THRESH_INFO
ROI_CONFIG__MODE_ROI_CENTRE_SPAD
ROI_CONFIG__MODE_ROI_XY_SIZE
ROI_CONFIG__USER_ROI_CENTRE_SPAD
ROI_CONFIG__USER_ROI_REQUESTED_GLOBAL_XY_SIZE
SD_CONFIG__FIRST_ORDER_SELECT
SD_CONFIG__INITIAL_PHASE_SD0
SD_CONFIG__INITIAL_PHASE_SD1
SD_CONFIG__QUANTIFIER
SD_CONFIG__RESET_STAGES_LSB
SD_CONFIG__RESET_STAGES_MSB
SD_CONFIG__WOI_SD0
SD_CONFIG__WOI_SD1
SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_HI
SHADOW_PHASECAL_RESULT__REFERENCE_PHASE_LO
SHADOW_PHASECAL_RESULT__VCSEL_START
SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0
SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_0
SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_1
SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_2
SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD0_3
SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1
SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_0
SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_1
SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_2
SHADOW_RESULT_CORE__AMBIENT_WINDOW_EVENTS_SD1_3
SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0
SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_0
SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_1
SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_2
SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD0_3
SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1
SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_0
SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_1
SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_2
SHADOW_RESULT_CORE__RANGING_TOTAL_EVENTS_SD1_3
SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0
SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_0
SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_1
SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_2
SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD0_3
SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1
SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_0
SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_1
SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_2
SHADOW_RESULT_CORE__SIGNAL_TOTAL_EVENTS_SD1_3
SHADOW_RESULT_CORE__SPARE_0
SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0
SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_0
SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_1
SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_2
SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD0_3
SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1
SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_0
SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_1
SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_2
SHADOW_RESULT_CORE__TOTAL_PERIODS_ELAPSED_SD1_3
SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0
SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_HI
SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD0_LO
SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1
SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_HI
SHADOW_RESULT__AMBIENT_COUNT_RATE_MCPS_SD1_LO
SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0
SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_HI
SHADOW_RESULT__AVG_SIGNAL_COUNT_RATE_MCPS_SD0_LO
SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0
SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_HI
SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD0_LO
SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1
SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_HI
SHADOW_RESULT__DSS_ACTUAL_EFFECTIVE_SPADS_SD1_LO
SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0
SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_HI
SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD0_LO
SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1
SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_HI
SHADOW_RESULT__FINAL_CROSSTALK_CORRECTED_RANGE_MM_SD1_LO
SHADOW_RESULT__INTERRUPT_STATUS
SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0
SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_HI
SHADOW_RESULT__MM_INNER_ACTUAL_EFFECTIVE_SPADS_SD0_LO
SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0
SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_HI
SHADOW_RESULT__MM_OUTER_ACTUAL_EFFECTIVE_SPADS_SD0_LO
SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0
SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_HI
SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_CROSSTALK_CORRECTED_MCPS_SD0_LO
SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0
SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_HI
SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD0_LO
SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1
SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_HI
SHADOW_RESULT__PEAK_SIGNAL_COUNT_RATE_MCPS_SD1_LO
SHADOW_RESULT__PHASE_SD0
SHADOW_RESULT__PHASE_SD0_HI
SHADOW_RESULT__PHASE_SD0_LO
SHADOW_RESULT__PHASE_SD1
SHADOW_RESULT__PHASE_SD1_HI
SHADOW_RESULT__PHASE_SD1_LO
SHADOW_RESULT__RANGE_STATUS
SHADOW_RESULT__REPORT_STATUS
SHADOW_RESULT__SIGMA_SD0
SHADOW_RESULT__SIGMA_SD0_HI
SHADOW_RESULT__SIGMA_SD0_LO
SHADOW_RESULT__SIGMA_SD1
SHADOW_RESULT__SIGMA_SD1_HI
SHADOW_RESULT__SIGMA_SD1_LO
SHADOW_RESULT__SPARE_0_SD1
SHADOW_RESULT__SPARE_0_SD1_HI
SHADOW_RESULT__SPARE_0_SD1_LO
SHADOW_RESULT__SPARE_1_SD1
SHADOW_RESULT__SPARE_1_SD1_HI
SHADOW_RESULT__SPARE_1_SD1_LO
SHADOW_RESULT__SPARE_2_SD1
SHADOW_RESULT__SPARE_2_SD1_HI
SHADOW_RESULT__SPARE_2_SD1_LO
SHADOW_RESULT__SPARE_3_SD1
SHADOW_RESULT__STREAM_COUNT
SHADOW_RESULT__THRESH_INFO
SIGMA_ESTIMATOR_CALC__SPARE_0
SIGMA_ESTIMATOR__EFFECTIVE_AMBIENT_WIDTH_NS
SIGMA_ESTIMATOR__EFFECTIVE_PULSE_WIDTH_NS
SIGMA_ESTIMATOR__SIGMA_REF_MM
SOFT_RESET
SOFT_RESET_GO1
SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_0
SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_1
SPARE_HOST_CONFIG__STATIC_CONFIG_SPARE_2
SPI_ASYNC_MUX__CTRL
SYSTEM__ENABLE_XTALK_PER_QUADRANT
SYSTEM__FRACTIONAL_ENABLE
SYSTEM__GROUPED_PARAMETER_HOLD
SYSTEM__GROUPED_PARAMETER_HOLD_0
SYSTEM__GROUPED_PARAMETER_HOLD_1
SYSTEM__INTERMEASUREMENT_PERIOD
SYSTEM__INTERMEASUREMENT_PERIOD_0
SYSTEM__INTERMEASUREMENT_PERIOD_1
SYSTEM__INTERMEASUREMENT_PERIOD_2
SYSTEM__INTERMEASUREMENT_PERIOD_3
SYSTEM__INTERRUPT_CLEAR
SYSTEM__INTERRUPT_CONFIG_GPIO
SYSTEM__INTERRUPT_SET
SYSTEM__MODE_START
SYSTEM__SEED_CONFIG
SYSTEM__SEQUENCE_CONFIG
SYSTEM__STREAM_COUNT_CTRL
SYSTEM__THRESH_HIGH
SYSTEM__THRESH_HIGH_HI
SYSTEM__THRESH_HIGH_LO
SYSTEM__THRESH_LOW
SYSTEM__THRESH_LOW_HI
SYSTEM__THRESH_LOW_LO
SYSTEM__THRESH_RATE_HIGH
SYSTEM__THRESH_RATE_HIGH_HI
SYSTEM__THRESH_RATE_HIGH_LO
SYSTEM__THRESH_RATE_LOW
SYSTEM__THRESH_RATE_LOW_HI
SYSTEM__THRESH_RATE_LOW_LO
TEST_MODE__CTRL
TEST_MODE__STATUS
TEST__BIST_RAM_CTRL
TEST__BIST_RAM_RESULT
TEST__BIST_ROM_CTRL
TEST__BIST_ROM_MCU_SIG
TEST__BIST_ROM_MCU_SIG_HI
TEST__BIST_ROM_MCU_SIG_LO
TEST__BIST_ROM_RESULT
TEST__PLL_BIST_COUNT_OUT
TEST__PLL_BIST_COUNT_OUT_HI
TEST__PLL_BIST_COUNT_OUT_LO
TEST__PLL_BIST_CTRL
TEST__PLL_BIST_GONOGO
TEST__PLL_BIST_MAX_THRESHOLD
TEST__PLL_BIST_MAX_THRESHOLD_HI
TEST__PLL_BIST_MAX_THRESHOLD_LO
TEST__PLL_BIST_MIN_THRESHOLD
TEST__PLL_BIST_MIN_THRESHOLD_HI
TEST__PLL_BIST_MIN_THRESHOLD_LO
TEST__TMC
TIMER0__CTRL
TIMER0__VALUE_IN
TIMER0__VALUE_IN_0
TIMER0__VALUE_IN_1
TIMER0__VALUE_IN_2
TIMER0__VALUE_IN_3
TIMER1__CTRL
TIMER1__VALUE_IN
TIMER1__VALUE_IN_0
TIMER1__VALUE_IN_1
TIMER1__VALUE_IN_2
TIMER1__VALUE_IN_3
VHV_CONFIG__COUNT_THRESH
VHV_CONFIG__INIT
VHV_CONFIG__OFFSET
VHV_CONFIG__TIMEOUT_MACROP_LOOP_BOUND
VHV_RESULT__COLDBOOT_STATUS
VHV_RESULT__LATEST_SETTING
VHV_RESULT__PEAK_SIGNAL_RATE_MCPS
VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_HI
VHV_RESULT__PEAK_SIGNAL_RATE_MCPS_LO
VHV_RESULT__SEARCH_RESULT
VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF
VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_0
VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_1
VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_2
VHV_RESULT__SIGNAL_TOTAL_EVENTS_REF_3
XTALK_CALC__XTALK_FOR_ENABLED_SPADS
XTALK_CALC__XTALK_FOR_ENABLED_SPADS_0
XTALK_CALC__XTALK_FOR_ENABLED_SPADS_1
XTALK_CALC__XTALK_FOR_ENABLED_SPADS_2
XTALK_CALC__XTALK_FOR_ENABLED_SPADS_3
XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS
XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_0
XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_1
XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_2
XTALK_RESULT__AVG_XTALK_MM_INNER_ROI_KCPS_3
XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS
XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_0
XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_1
XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_2
XTALK_RESULT__AVG_XTALK_MM_OUTER_ROI_KCPS_3
XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS
XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_0
XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_1
XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_2
XTALK_RESULT__AVG_XTALK_USER_ROI_KCPS_3

Enums

Index

A dynamic representation of an entry's 16-bit index within the register map.

State

A dynamic representation of entry state.

Constants

MAX_SLICE_LEN

The maximum amount of data that may be written to write_slice at once.

SLAVE_ADDR

The slave address of the VL53L1X. Note that embedded-hal I2C API adds the w/r bit for us.

Traits

Entry

Implemented for all entries within the register map.

Functions

read_byte

Shorthand for reading a single byte from the register at the given index.

read_entry

Read the value for a single entry.

read_slice

Read the value at the given index into the given slice.

read_word

Shorthand for reading two consecutive bytes from the given index.

write_byte

Shorthand for writing a slice with a single byte.

write_entry

Read the the given entry.

write_slice

Write given slice of data to the device at the given index.

write_word

Shorthand for writing a slice with a single word.