Module stm32wl::stm32wle5::tim17::cr1[−][src]

Expand description

TIM16/TIM17 control register 1

Structs

ARPE_R

Field ARPE reader - Auto-reload preload enable

ARPE_W

Field ARPE writer - Auto-reload preload enable

CEN_R

Field CEN reader - Counter enable

CEN_W

Field CEN writer - Counter enable

CKD_R

Field CKD reader - Clock division

CKD_W

Field CKD writer - Clock division

CR1_SPEC

TIM16/TIM17 control register 1

OPM_R

Field OPM reader - One pulse mode

OPM_W

Field OPM writer - One pulse mode

R

Register CR1 reader

UDIS_R

Field UDIS reader - Update disable

UDIS_W

Field UDIS writer - Update disable

UIFREMAP_R

Field UIFREMAP reader - UIF status bit remapping

UIFREMAP_W

Field UIFREMAP writer - UIF status bit remapping

URS_R

Field URS reader - Update request source

URS_W

Field URS writer - Update request source

W

Register CR1 writer

Enums

ARPE_A

Auto-reload preload enable

CEN_A

Counter enable

CKD_A

Clock division

UDIS_A

Update disable

UIFREMAP_A

UIF status bit remapping

URS_A

Update request source