[−][src]Module stm32wb_pac::tim1
Advanced-timers
Modules
| af1 | DMA address for full transfer |
| af2 | DMA address for full transfer |
| arr | auto-reload register |
| bdtr | break and dead-time register |
| ccer | capture/compare enable register |
| ccmr1_input | capture/compare mode register 1 (output mode) |
| ccmr1_output | capture/compare mode register 1 (output mode) |
| ccmr2_input | capture/compare mode register 2 (output mode) |
| ccmr2_output | capture/compare mode register 2 (output mode) |
| ccmr3_output | capture/compare mode register 2 (output mode) |
| ccr1 | capture/compare register 1 |
| ccr2 | capture/compare register 2 |
| ccr3 | capture/compare register 3 |
| ccr4 | capture/compare register 4 |
| ccr5 | capture/compare register 4 |
| ccr6 | capture/compare register 4 |
| cnt | counter |
| cr1 | control register 1 |
| cr2 | control register 2 |
| dcr | DMA control register |
| dier | DMA/Interrupt enable register |
| dmar | DMA address for full transfer |
| egr | event generation register |
| or | DMA address for full transfer |
| psc | prescaler |
| rcr | repetition counter register |
| smcr | slave mode control register |
| sr | status register |
Structs
| RegisterBlock | Register block |
Type Definitions
| AF1 | DMA address for full transfer |
| AF2 | DMA address for full transfer |
| ARR | auto-reload register |
| BDTR | break and dead-time register |
| CCER | capture/compare enable register |
| CCMR1_INPUT | capture/compare mode register 1 (output mode) |
| CCMR1_OUTPUT | capture/compare mode register 1 (output mode) |
| CCMR2_INPUT | capture/compare mode register 2 (output mode) |
| CCMR2_OUTPUT | capture/compare mode register 2 (output mode) |
| CCMR3_OUTPUT | capture/compare mode register 2 (output mode) |
| CCR1 | capture/compare register 1 |
| CCR2 | capture/compare register 2 |
| CCR3 | capture/compare register 3 |
| CCR4 | capture/compare register 4 |
| CCR5 | capture/compare register 4 |
| CCR6 | capture/compare register 4 |
| CNT | counter |
| CR1 | control register 1 |
| CR2 | control register 2 |
| DCR | DMA control register |
| DIER | DMA/Interrupt enable register |
| DMAR | DMA address for full transfer |
| EGR | event generation register |
| OR | DMA address for full transfer |
| PSC | prescaler |
| RCR | repetition counter register |
| SMCR | slave mode control register |
| SR | status register |