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#[doc = "Reader of register PLLSAI1CFGR"] pub type R = crate::R<u32, super::PLLSAI1CFGR>; #[doc = "Writer for register PLLSAI1CFGR"] pub type W = crate::W<u32, super::PLLSAI1CFGR>; #[doc = "Register PLLSAI1CFGR `reset()`'s with value 0x2204_0100"] impl crate::ResetValue for super::PLLSAI1CFGR { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0x2204_0100 } } #[doc = "Reader of field `PLLR`"] pub type PLLR_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PLLR`"] pub struct PLLR_W<'a> { w: &'a mut W, } impl<'a> PLLR_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 29)) | (((value as u32) & 0x07) << 29); self.w } } #[doc = "Reader of field `PLLREN`"] pub type PLLREN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PLLREN`"] pub struct PLLREN_W<'a> { w: &'a mut W, } impl<'a> PLLREN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 28)) | (((value as u32) & 0x01) << 28); self.w } } #[doc = "Reader of field `PLLQ`"] pub type PLLQ_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PLLQ`"] pub struct PLLQ_W<'a> { w: &'a mut W, } impl<'a> PLLQ_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 25)) | (((value as u32) & 0x07) << 25); self.w } } #[doc = "Reader of field `PLLQEN`"] pub type PLLQEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PLLQEN`"] pub struct PLLQEN_W<'a> { w: &'a mut W, } impl<'a> PLLQEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); self.w } } #[doc = "Reader of field `PLLP`"] pub type PLLP_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PLLP`"] pub struct PLLP_W<'a> { w: &'a mut W, } impl<'a> PLLP_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x1f << 17)) | (((value as u32) & 0x1f) << 17); self.w } } #[doc = "Reader of field `PLLPEN`"] pub type PLLPEN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `PLLPEN`"] pub struct PLLPEN_W<'a> { w: &'a mut W, } impl<'a> PLLPEN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); self.w } } #[doc = "Reader of field `PLLN`"] pub type PLLN_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PLLN`"] pub struct PLLN_W<'a> { w: &'a mut W, } impl<'a> PLLN_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x7f << 8)) | (((value as u32) & 0x7f) << 8); self.w } } impl R { #[doc = "Bits 29:31 - PLLSAI division factor R for PLLADC1CLK (ADC clock)"] #[inline(always)] pub fn pllr(&self) -> PLLR_R { PLLR_R::new(((self.bits >> 29) & 0x07) as u8) } #[doc = "Bit 28 - PLLSAI PLLADC1CLK output enable"] #[inline(always)] pub fn pllren(&self) -> PLLREN_R { PLLREN_R::new(((self.bits >> 28) & 0x01) != 0) } #[doc = "Bits 25:27 - SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)"] #[inline(always)] pub fn pllq(&self) -> PLLQ_R { PLLQ_R::new(((self.bits >> 25) & 0x07) as u8) } #[doc = "Bit 24 - SAIPLL PLLSAIUSBCLK output enable"] #[inline(always)] pub fn pllqen(&self) -> PLLQEN_R { PLLQEN_R::new(((self.bits >> 24) & 0x01) != 0) } #[doc = "Bits 17:21 - SAI1PLL division factor P for PLLSAICLK (SAI1clock)"] #[inline(always)] pub fn pllp(&self) -> PLLP_R { PLLP_R::new(((self.bits >> 17) & 0x1f) as u8) } #[doc = "Bit 16 - SAIPLL PLLSAI1CLK output enable"] #[inline(always)] pub fn pllpen(&self) -> PLLPEN_R { PLLPEN_R::new(((self.bits >> 16) & 0x01) != 0) } #[doc = "Bits 8:14 - SAIPLL multiplication factor for VCO"] #[inline(always)] pub fn plln(&self) -> PLLN_R { PLLN_R::new(((self.bits >> 8) & 0x7f) as u8) } } impl W { #[doc = "Bits 29:31 - PLLSAI division factor R for PLLADC1CLK (ADC clock)"] #[inline(always)] pub fn pllr(&mut self) -> PLLR_W { PLLR_W { w: self } } #[doc = "Bit 28 - PLLSAI PLLADC1CLK output enable"] #[inline(always)] pub fn pllren(&mut self) -> PLLREN_W { PLLREN_W { w: self } } #[doc = "Bits 25:27 - SAIPLL division factor Q for PLLSAIUSBCLK (48 MHz clock)"] #[inline(always)] pub fn pllq(&mut self) -> PLLQ_W { PLLQ_W { w: self } } #[doc = "Bit 24 - SAIPLL PLLSAIUSBCLK output enable"] #[inline(always)] pub fn pllqen(&mut self) -> PLLQEN_W { PLLQEN_W { w: self } } #[doc = "Bits 17:21 - SAI1PLL division factor P for PLLSAICLK (SAI1clock)"] #[inline(always)] pub fn pllp(&mut self) -> PLLP_W { PLLP_W { w: self } } #[doc = "Bit 16 - SAIPLL PLLSAI1CLK output enable"] #[inline(always)] pub fn pllpen(&mut self) -> PLLPEN_W { PLLPEN_W { w: self } } #[doc = "Bits 8:14 - SAIPLL multiplication factor for VCO"] #[inline(always)] pub fn plln(&mut self) -> PLLN_W { PLLN_W { w: self } } }