1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54
#[doc = "Reader of register DIFSEL"] pub type R = crate::R<u32, super::DIFSEL>; #[doc = "Writer for register DIFSEL"] pub type W = crate::W<u32, super::DIFSEL>; #[doc = "Register DIFSEL `reset()`'s with value 0"] impl crate::ResetValue for super::DIFSEL { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0 } } #[doc = "Reader of field `DIFSEL_0`"] pub type DIFSEL_0_R = crate::R<bool, bool>; #[doc = "Reader of field `DIFSEL_1_15`"] pub type DIFSEL_1_15_R = crate::R<u16, u16>; #[doc = "Write proxy for field `DIFSEL_1_15`"] pub struct DIFSEL_1_15_W<'a> { w: &'a mut W, } impl<'a> DIFSEL_1_15_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u16) -> &'a mut W { self.w.bits = (self.w.bits & !(0x7fff << 1)) | (((value as u32) & 0x7fff) << 1); self.w } } #[doc = "Reader of field `DIFSEL_16_18`"] pub type DIFSEL_16_18_R = crate::R<u8, u8>; impl R { #[doc = "Bit 0 - ADC channel differential or single-ended mode for channel 0"] #[inline(always)] pub fn difsel_0(&self) -> DIFSEL_0_R { DIFSEL_0_R::new((self.bits & 0x01) != 0) } #[doc = "Bits 1:15 - ADC channel differential or single-ended mode for channels 1 to 15"] #[inline(always)] pub fn difsel_1_15(&self) -> DIFSEL_1_15_R { DIFSEL_1_15_R::new(((self.bits >> 1) & 0x7fff) as u16) } #[doc = "Bits 16:18 - ADC channel differential or single-ended mode for channels 18 to 16"] #[inline(always)] pub fn difsel_16_18(&self) -> DIFSEL_16_18_R { DIFSEL_16_18_R::new(((self.bits >> 16) & 0x07) as u8) } } impl W { #[doc = "Bits 1:15 - ADC channel differential or single-ended mode for channels 1 to 15"] #[inline(always)] pub fn difsel_1_15(&mut self) -> DIFSEL_1_15_W { DIFSEL_1_15_W { w: self } } }