[−][src]Module stm32l4xx_hal::rcc
Reset and Clock Control
Structs
| AHB1 | AMBA High-performance Bus 1 (AHB1) registers |
| AHB2 | AMBA High-performance Bus 2 (AHB2) registers |
| AHB3 | AMBA High-performance Bus (AHB3) registers |
| APB2 | Advanced Peripheral Bus 2 (APB2) registers |
| APB1R1 | Advanced Peripheral Bus 1 (APB1) register 1 registers |
| APB1R2 | Advanced Peripheral Bus 1 (APB1) register 2 registers |
| BDCR | BDCR Backup domain control register registers |
| CFGR | Clock configuration |
| CRRCR | Clock recovery RC register |
| CSR | CSR Control/Status Register |
| Clocks | Frozen clock frequencies |
| PllConfig | Pll Configuration - Calculation = ((SourceClk / m) * n) / r |
| Rcc | Constrained RCC peripheral |
Enums
| MsiFreq |
Traits
| RccExt | Extension trait that constrains the |