Module stm32l4xx_hal::rcc

source ·
Expand description

Reset and Clock Control

Structs

AMBA High-performance Bus 1 (AHB1) registers
AMBA High-performance Bus 2 (AHB2) registers
AMBA High-performance Bus (AHB3) registers
Advanced Peripheral Bus 1 (APB1) register 1 registers
Advanced Peripheral Bus 1 (APB1) register 2 registers
Advanced Peripheral Bus 2 (APB2) registers
BDCR Backup domain control register registers
Clock configuration
CSR Control/Status Register
Frozen clock frequencies
Pll Configuration - Calculation = ((SourceClk / m) * n) / r
Constrained RCC peripheral

Traits

Extension trait that constrains the RCC peripheral