[−][src]Module stm32h7xx_hal::stm32::adc3::cfgr

ADC configuration register 1

Structs

AUTDLY_W	Write proxy for field `AUTDLY`
AWD1CH_W	Write proxy for field `AWD1CH`
AWD1EN_W	Write proxy for field `AWD1EN`
AWD1SGL_W	Write proxy for field `AWD1SGL`
CONT_W	Write proxy for field `CONT`
DISCEN_W	Write proxy for field `DISCEN`
DISCNUM_W	Write proxy for field `DISCNUM`
DMNGT_W	Write proxy for field `DMNGT`
EXTEN_W	Write proxy for field `EXTEN`
EXTSEL_W	Write proxy for field `EXTSEL`
JAUTO_W	Write proxy for field `JAUTO`
JAWD1EN_W	Write proxy for field `JAWD1EN`
JDISCEN_W	Write proxy for field `JDISCEN`
JQDIS_W	Write proxy for field `JQDIS`
JQM_W	Write proxy for field `JQM`
OVRMOD_W	Write proxy for field `OVRMOD`
RES_W	Write proxy for field `RES`

AUTDLY_A	ADC low power auto wait
AWD1EN_A	ADC analog watchdog 1 enable on scope ADC group regular
AWD1SGL_A	ADC analog watchdog 1 monitoring a single channel or all channels
CONT_A	ADC group regular continuous conversion mode
DISCEN_A	ADC group regular sequencer discontinuous mode
DMNGT_A	ADC DMA transfer enable
EXTEN_A	ADC group regular external trigger polarity
EXTSEL_A	ADC group regular external trigger source
JAUTO_A	ADC group injected automatic trigger mode
JAWD1EN_A	ADC analog watchdog 1 enable on scope ADC group injected
JDISCEN_A	ADC group injected sequencer discontinuous mode
JQDIS_A	ADC group injected contexts queue disable
JQM_A	ADC group injected contexts queue mode
OVRMOD_A	ADC group regular overrun configuration
RES_A	ADC data resolution