Struct stm32f7xx_hal::pac::dma2d::RegisterBlock

source · 
#[repr(C)]
pub struct RegisterBlock {
Show 22 fields
    pub cr: Reg<CR_SPEC>,
    pub isr: Reg<ISR_SPEC>,
    pub ifcr: Reg<IFCR_SPEC>,
    pub fgmar: Reg<FGMAR_SPEC>,
    pub fgor: Reg<FGOR_SPEC>,
    pub bgmar: Reg<BGMAR_SPEC>,
    pub bgor: Reg<BGOR_SPEC>,
    pub fgpfccr: Reg<FGPFCCR_SPEC>,
    pub fgcolr: Reg<FGCOLR_SPEC>,
    pub bgpfccr: Reg<BGPFCCR_SPEC>,
    pub bgcolr: Reg<BGCOLR_SPEC>,
    pub fgcmar: Reg<FGCMAR_SPEC>,
    pub bgcmar: Reg<BGCMAR_SPEC>,
    pub opfccr: Reg<OPFCCR_SPEC>,
    pub ocolr: Reg<OCOLR_SPEC>,
    pub omar: Reg<OMAR_SPEC>,
    pub oor: Reg<OOR_SPEC>,
    pub nlr: Reg<NLR_SPEC>,
    pub lwr: Reg<LWR_SPEC>,
    pub amtcr: Reg<AMTCR_SPEC>,
    pub fgclut: Reg<FGCLUT_SPEC>,
    pub bgclut: Reg<BGCLUT_SPEC>,
    /* private fields */

}
Expand description

Register block

Fields§

§cr: Reg<CR_SPEC>

0x00 - control register

§isr: Reg<ISR_SPEC>

0x04 - Interrupt Status Register

§ifcr: Reg<IFCR_SPEC>

0x08 - interrupt flag clear register

§fgmar: Reg<FGMAR_SPEC>

0x0c - foreground memory address register

§fgor: Reg<FGOR_SPEC>

0x10 - foreground offset register

§bgmar: Reg<BGMAR_SPEC>

0x14 - background memory address register

§bgor: Reg<BGOR_SPEC>

0x18 - background offset register

§fgpfccr: Reg<FGPFCCR_SPEC>

0x1c - foreground PFC control register

§fgcolr: Reg<FGCOLR_SPEC>

0x20 - foreground color register

§bgpfccr: Reg<BGPFCCR_SPEC>

0x24 - background PFC control register

§bgcolr: Reg<BGCOLR_SPEC>

0x28 - background color register

§fgcmar: Reg<FGCMAR_SPEC>

0x2c - foreground CLUT memory address register

§bgcmar: Reg<BGCMAR_SPEC>

0x30 - background CLUT memory address register

§opfccr: Reg<OPFCCR_SPEC>

0x34 - output PFC control register

§ocolr: Reg<OCOLR_SPEC>

0x38 - output color register

§omar: Reg<OMAR_SPEC>

0x3c - output memory address register

§oor: Reg<OOR_SPEC>

0x40 - output offset register

§nlr: Reg<NLR_SPEC>

0x44 - number of line register

§lwr: Reg<LWR_SPEC>

0x48 - line watermark register

§amtcr: Reg<AMTCR_SPEC>

0x4c - AHB master timer configuration register

§fgclut: Reg<FGCLUT_SPEC>

0x400 - FGCLUT

§bgclut: Reg<BGCLUT_SPEC>

0x800 - BGCLUT

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