use crate::hal::timer::{CountDown, Periodic};
#[cfg(any(
feature = "stm32f301",
feature = "stm32f302",
feature = "stm32f303",
feature = "stm32f334",
feature = "stm32f318",
feature = "stm32f328",
feature = "stm32f358",
feature = "stm32f398",
))]
use crate::pac::TIM1;
#[cfg(any(
feature = "stm32f303",
feature = "stm32f328",
feature = "stm32f358",
feature = "stm32f398"
))]
use crate::pac::TIM20;
#[cfg(any(
feature = "stm32f303",
feature = "stm32f328",
feature = "stm32f358",
feature = "stm32f373",
feature = "stm32f378",
feature = "stm32f398"
))]
use crate::pac::TIM4;
#[cfg(any(
feature = "stm32f303",
feature = "stm32f328",
feature = "stm32f358",
feature = "stm32f398",
))]
use crate::pac::TIM8;
#[cfg(any(feature = "stm32f373", feature = "stm32f378"))]
use crate::pac::{TIM12, TIM13, TIM14, TIM18, TIM19, TIM5};
use crate::pac::{TIM15, TIM16, TIM17, TIM2, TIM6};
#[cfg(any(
feature = "stm32f303",
feature = "stm32f328",
feature = "stm32f334",
feature = "stm32f358",
feature = "stm32f373",
feature = "stm32f378",
feature = "stm32f398"
))]
use crate::pac::{TIM3, TIM7};
use cast::{u16, u32};
use void::Void;
use crate::rcc::{Clocks, APB1, APB2};
use crate::time::Hertz;
pub trait PclkSrc {
fn get_clk(clocks: &Clocks) -> Hertz;
}
pub struct Timer<TIM> {
clocks: Clocks,
tim: TIM,
}
pub enum Event {
Update,
}
#[derive(Clone, Copy, Debug)]
pub enum Alignment {
Edge,
Center1,
Center2,
Center3,
}
#[derive(Clone, Copy, Debug)]
pub enum Channel {
One,
Two,
Three,
Four,
}
#[repr(u8)]
#[derive(Clone, Copy, Debug)]
pub enum CaptureCompare {
Output = 0b00,
InputTi1 = 0b01,
InputTi2 = 0b10,
InputTrc = 0b11,
}
#[derive(Clone, Copy, Debug)]
pub enum Polarity {
ActiveHigh,
ActiveLow,
}
impl Polarity {
fn bit(&self) -> bool {
match self {
Self::ActiveHigh => false,
Self::ActiveLow => true,
}
}
}
#[derive(Clone, Copy, Debug)]
#[repr(u8)]
pub enum OutputCompare {
Frozen = 0b0000,
Active = 0b0001,
Inactive = 0b0010,
ForceInactive = 0b0100,
ForceActive = 0b0101,
Pwm1 = 0b0110,
Pwm2 = 0b0111,
RetriggerableOpmMode1 = 0b1000,
RetriggerableOpmMode2 = 0b1001,
CombinedPwm1 = 0b1100,
CombinedPwm2 = 0b1101,
AsymmetricPwm1 = 0b1110,
AsymmetricPwm2 = 0b1111,
}
impl OutputCompare {
pub fn left_bit(&self) -> bool {
match self {
Self::RetriggerableOpmMode1 => true,
Self::RetriggerableOpmMode2 => true,
Self::CombinedPwm1 => true,
Self::CombinedPwm2 => true,
Self::AsymmetricPwm1 => true,
Self::AsymmetricPwm2 => true,
_ => false,
}
}
}
macro_rules! basic_timer {
($({
$TIMX:ident: ($tim:ident, $timXen:ident, $timXrst:ident),
$APB:ident: ($apb:ident, $pclkX:ident),
$res:ident,
},)+) => {
$(
impl PclkSrc for $TIMX {
fn get_clk(clocks: &Clocks) -> Hertz {
clocks.$pclkX()
}
}
impl Periodic for Timer<$TIMX> {}
impl CountDown for Timer<$TIMX> {
type Time = Hertz;
fn start<T>(&mut self, timeout: T)
where
T: Into<Hertz>,
{
self.stop();
let frequency = timeout.into().0;
let timer_clock = $TIMX::get_clk(&self.clocks);
let ticks = timer_clock.0 * if self.clocks.ppre1() == 1 { 1 } else { 2 }
/ frequency;
let psc = u16((ticks - 1) / (1 << 16)).unwrap();
self.tim.psc.write(|w| w.psc().bits(psc));
let arr = u16(ticks / u32(psc + 1)).unwrap();
self.tim.arr.write(|w| unsafe { w.bits(u32(arr)) });
self.tim.egr.write(|w| w.ug().update());
self.clear_update_interrupt_flag();
self.tim.cr1.modify(|_, w| w.cen().enabled());
}
fn wait(&mut self) -> nb::Result<(), Void> {
if self.tim.sr.read().uif().is_clear() {
Err(nb::Error::WouldBlock)
} else {
self.clear_update_interrupt_flag();
Ok(())
}
}
}
impl Timer<$TIMX> {
pub fn $tim<T>(tim: $TIMX, timeout: T, clocks: Clocks, $apb: &mut $APB) -> Self
where
T: Into<Hertz>,
{
$apb.enr().modify(|_, w| w.$timXen().enabled());
$apb.rstr().modify(|_, w| w.$timXrst().reset());
$apb.rstr().modify(|_, w| w.$timXrst().clear_bit());
let mut timer = Timer { clocks, tim };
timer.start(timeout);
timer
}
pub fn listen(&mut self, event: Event) {
match event {
Event::Update => self.tim.dier.write(|w| w.uie().enabled()),
}
}
pub fn unlisten(&mut self, event: Event) {
match event {
Event::Update => self.tim.dier.write(|w| w.uie().disabled()),
}
}
pub fn stop(&mut self) {
self.tim.cr1.modify(|_, w| w.cen().disabled());
}
pub fn clear_update_interrupt_flag(&mut self) {
self.tim.sr.modify(|_, w| w.uif().clear());
}
pub fn release(mut self) -> $TIMX {
self.stop();
self.tim
}
pub fn set_resolution(&mut self, word: $res) {
self.tim.arr.write(|w| unsafe { w.arr().bits(word) } );
}
pub fn get_max_duty(&self) -> $res {
self.tim.arr.read().arr().bits()
}
}
)+
}
}
macro_rules! advanced_timer {
($({
$TIMX:ident: ($tim:ident, $timXen:ident, $timXrst:ident),
$APB:ident: ($apb:ident, $pclkX:ident),
$res:ident,
},)+) => {
$(
impl PclkSrc for $TIMX {
fn get_clk(clocks: &Clocks) -> Hertz {
clocks.$pclkX()
}
}
impl Periodic for Timer<$TIMX> {}
impl CountDown for Timer<$TIMX> {
type Time = Hertz;
fn start<T>(&mut self, timeout: T)
where
T: Into<Hertz>,
{
self.stop();
let frequency = timeout.into().0;
let timer_clock = $TIMX::get_clk(&self.clocks);
let ticks = timer_clock.0 * if self.clocks.ppre1() == 1 { 1 } else { 2 }
/ frequency;
let psc = u16((ticks - 1) / (1 << 16)).unwrap();
self.tim.psc.write(|w| w.psc().bits(psc));
let arr = u16(ticks / u32(psc + 1)).unwrap();
self.tim.arr.write(|w| unsafe { w.bits(u32(arr)) });
self.tim.egr.write(|w| w.ug().update());
self.clear_update_interrupt_flag();
self.tim.cr1.modify(|_, w| w.cen().enabled());
}
fn wait(&mut self) -> nb::Result<(), Void> {
if self.tim.sr.read().uif().is_clear() {
Err(nb::Error::WouldBlock)
} else {
self.clear_update_interrupt_flag();
Ok(())
}
}
}
impl Timer<$TIMX> {
pub fn $tim<T>(tim: $TIMX, timeout: T, clocks: Clocks, $apb: &mut $APB) -> Self
where
T: Into<Hertz>,
{
$apb.enr().modify(|_, w| w.$timXen().enabled());
$apb.rstr().modify(|_, w| w.$timXrst().reset());
$apb.rstr().modify(|_, w| w.$timXrst().clear_bit());
let mut timer = Timer { clocks, tim };
timer.start(timeout);
timer
}
pub fn listen(&mut self, event: Event) {
match event {
Event::Update => self.tim.dier.write(|w| w.uie().enabled()),
}
}
pub fn unlisten(&mut self, event: Event) {
match event {
Event::Update => self.tim.dier.write(|w| w.uie().disabled()),
}
}
pub fn stop(&mut self) {
self.tim.cr1.modify(|_, w| w.cen().disabled());
}
pub fn clear_update_interrupt_flag(&mut self) {
self.tim.sr.modify(|_, w| w.uif().clear());
}
pub fn release(mut self) -> $TIMX {
self.stop();
self.tim
}
pub fn set_alignment(&mut self, alignment: Alignment) {
let word = match alignment {
Alignment::Edge => 0b00,
Alignment::Center1 => 0b01,
Alignment::Center2 => 0b10,
Alignment::Center3 => 0b11,
};
self.tim.cr1.modify(|_, w| w.cms().bits(word));
}
pub fn set_resolution(&mut self, word: $res) {
self.tim.arr.write(|w| w.arr().bits(word));
}
pub fn get_max_duty(&self) -> $res {
self.tim.arr.read().arr().bits()
}
pub fn set_polarity(&mut self, channel: Channel, polarity: Polarity) {
match channel {
Channel::One => self.tim.ccer.modify(|_, w| w.cc1p().bit(polarity.bit())),
Channel::Two => self.tim.ccer.modify(|_, w| w.cc2p().bit(polarity.bit())),
Channel::Three => self.tim.ccer.modify(|_, w| w.cc3p().bit(polarity.bit())),
Channel::Four => self.tim.ccer.modify(|_, w| w.cc4p().bit(polarity.bit())),
}
}
pub fn disable(&mut self, channel: Channel) {
match channel {
Channel::One => self.tim.ccer.modify(|_, w| w.cc1e().clear_bit()),
Channel::Two => self.tim.ccer.modify(|_, w| w.cc2e().clear_bit()),
Channel::Three => self.tim.ccer.modify(|_, w| w.cc3e().clear_bit()),
Channel::Four => self.tim.ccer.modify(|_, w| w.cc4e().clear_bit()),
}
}
pub fn enable(&mut self, channel: Channel) {
match channel {
Channel::One => self.tim.ccer.modify(|_, w| w.cc1e().set_bit()),
Channel::Two => self.tim.ccer.modify(|_, w| w.cc2e().set_bit()),
Channel::Three => self.tim.ccer.modify(|_, w| w.cc3e().set_bit()),
Channel::Four => self.tim.ccer.modify(|_, w| w.cc4e().set_bit()),
}
}
}
)+
}
}
macro_rules! gp_timer {
($({
$TIMX:ident: ($tim:ident, $timXen:ident, $timXrst:ident),
$APB:ident: ($apb:ident, $pclkX:ident),
$res:ident,
},)+) => {
$(
impl PclkSrc for $TIMX {
fn get_clk(clocks: &Clocks) -> Hertz {
clocks.$pclkX()
}
}
impl Periodic for Timer<$TIMX> {}
impl CountDown for Timer<$TIMX> {
type Time = Hertz;
fn start<T>(&mut self, timeout: T)
where
T: Into<Hertz>,
{
self.stop();
let frequency = timeout.into().0;
let timer_clock = $TIMX::get_clk(&self.clocks);
let ticks = timer_clock.0 * if self.clocks.ppre1() == 1 { 1 } else { 2 }
/ frequency;
let psc = u16((ticks - 1) / (1 << 16)).unwrap();
self.tim.psc.write(|w| w.psc().bits(psc));
let arr = u16(ticks / u32(psc + 1)).unwrap();
self.tim.arr.write(|w| unsafe { w.bits(u32(arr)) });
self.tim.egr.write(|w| w.ug().update());
self.clear_update_interrupt_flag();
self.tim.cr1.modify(|_, w| w.cen().enabled());
}
fn wait(&mut self) -> nb::Result<(), Void> {
if self.tim.sr.read().uif().is_clear() {
Err(nb::Error::WouldBlock)
} else {
self.clear_update_interrupt_flag();
Ok(())
}
}
}
impl Timer<$TIMX> {
pub fn $tim<T>(tim: $TIMX, timeout: T, clocks: Clocks, $apb: &mut $APB) -> Self
where
T: Into<Hertz>,
{
$apb.enr().modify(|_, w| w.$timXen().enabled());
$apb.rstr().modify(|_, w| w.$timXrst().reset());
$apb.rstr().modify(|_, w| w.$timXrst().clear_bit());
let mut timer = Timer { clocks, tim };
timer.start(timeout);
timer
}
pub fn listen(&mut self, event: Event) {
match event {
Event::Update => self.tim.dier.write(|w| w.uie().enabled()),
}
}
pub fn unlisten(&mut self, event: Event) {
match event {
Event::Update => self.tim.dier.write(|w| w.uie().disabled()),
}
}
pub fn stop(&mut self) {
self.tim.cr1.modify(|_, w| w.cen().disabled());
}
pub fn clear_update_interrupt_flag(&mut self) {
self.tim.sr.modify(|_, w| w.uif().clear());
}
pub fn release(mut self) -> $TIMX {
self.stop();
self.tim
}
pub fn set_alignment(&mut self, alignment: Alignment) {
let word = match alignment {
Alignment::Edge => 0b00,
Alignment::Center1 => 0b01,
Alignment::Center2 => 0b10,
Alignment::Center3 => 0b11,
};
self.tim.cr1.modify(|_, w| w.cms().bits(word));
}
pub fn set_resolution(&mut self, word: $res) {
self.tim.arr.write(|w| w.arr().bits(word));
}
pub fn get_max_duty(&self) -> $res {
self.tim.arr.read().arr().bits()
}
pub fn set_polarity(&mut self, channel: Channel, polarity: Polarity) {
match channel {
Channel::One => self.tim.ccer.modify(|_, w| w.cc1p().bit(polarity.bit())),
Channel::Two => self.tim.ccer.modify(|_, w| w.cc2p().bit(polarity.bit())),
Channel::Three => self.tim.ccer.modify(|_, w| w.cc3p().bit(polarity.bit())),
Channel::Four => self.tim.ccer.modify(|_, w| w.cc4p().bit(polarity.bit())),
}
}
pub fn set_complementary_polarity(&mut self, channel: Channel, polarity: Polarity) {
match channel {
Channel::One => self.tim.ccer.modify(|_, w| w.cc1np().bit(polarity.bit())),
Channel::Two => self.tim.ccer.modify(|_, w| w.cc2np().bit(polarity.bit())),
Channel::Three => self.tim.ccer.modify(|_, w| w.cc3np().bit(polarity.bit())),
Channel::Four => self.tim.ccer.modify(|_, w| w.cc4np().bit(polarity.bit())),
}
}
pub fn disable(&mut self, channel: Channel) {
match channel {
Channel::One => self.tim.ccer.modify(|_, w| w.cc1e().clear_bit()),
Channel::Two => self.tim.ccer.modify(|_, w| w.cc2e().clear_bit()),
Channel::Three => self.tim.ccer.modify(|_, w| w.cc3e().clear_bit()),
Channel::Four => self.tim.ccer.modify(|_, w| w.cc4e().clear_bit()),
}
}
pub fn enable(&mut self, channel: Channel) {
match channel {
Channel::One => self.tim.ccer.modify(|_, w| w.cc1e().set_bit()),
Channel::Two => self.tim.ccer.modify(|_, w| w.cc2e().set_bit()),
Channel::Three => self.tim.ccer.modify(|_, w| w.cc3e().set_bit()),
Channel::Four => self.tim.ccer.modify(|_, w| w.cc4e().set_bit()),
}
}
pub fn set_capture_compare(&mut self, channel: Channel, mode: CaptureCompare) {
match channel {
Channel::One => self.tim.ccmr1_output().modify( unsafe { |_, w| w.cc1s().bits(mode as u8)} ),
Channel::Two => self.tim.ccmr1_output().modify(unsafe {|_, w| w.cc2s().bits(mode as u8)}),
Channel::Three => self.tim.ccmr2_output().modify(unsafe {|_, w| w.cc3s().bits(mode as u8)}),
Channel::Four => self.tim.ccmr2_output().modify(unsafe {|_, w| w.cc4s().bits(mode as u8)}),
}
}
pub fn set_output_compare(&mut self, channel: Channel, mode: OutputCompare) {
match channel {
Channel::One => {
self.tim.ccmr1_output().modify(|_, w| w.oc1m().bits(mode as u8));
self.tim.ccmr1_output().modify(|_, w| w.oc1m_3().bit(mode.left_bit()));
}
Channel::Two => {
self.tim.ccmr1_output().modify(|_, w| w.oc2m().bits(mode as u8));
self.tim.ccmr1_output().modify(|_, w| w.oc2m_3().bit(mode.left_bit()));
}
Channel::Three => {
self.tim.ccmr2_output().modify(|_, w| w.oc3m().bits(mode as u8));
self.tim.ccmr2_output().modify(|_, w| w.oc3m_3().bit(mode.left_bit()));
}
Channel::Four => {
self.tim.ccmr2_output().modify(|_, w| w.oc4m().bits(mode as u8));
self.tim.ccmr2_output().modify(|_, w| w.oc4m_3().bit(mode.left_bit()));
}
}
}
pub fn set_preload(&mut self, channel: Channel, value: bool) {
match channel {
Channel::One => self.tim.ccmr1_output().modify(|_, w| w.oc1pe().bit(value)),
Channel::Two => self.tim.ccmr1_output().modify(|_, w| w.oc2pe().bit(value)),
Channel::Three => self.tim.ccmr2_output().modify(|_, w| w.oc3pe().bit(value)),
Channel::Four => self.tim.ccmr2_output().modify(|_, w| w.oc4pe().bit(value)),
}
}
pub fn get_duty(&self, channel: Channel) -> $res {
match channel {
Channel::One => self.tim.ccr1.read().ccr().bits(),
Channel::Two => self.tim.ccr2.read().ccr().bits(),
Channel::Three => self.tim.ccr3.read().ccr().bits(),
Channel::Four => self.tim.ccr4.read().ccr().bits(),
}
}
pub fn set_duty(&mut self, channel: Channel, duty: $res) {
match channel {
Channel::One => self.tim.ccr1.write(|w| w.ccr().bits(duty)),
Channel::Two => self.tim.ccr2.write(|w| w.ccr().bits(duty)),
Channel::Three => self.tim.ccr3.write(|w| w.ccr().bits(duty)),
Channel::Four => self.tim.ccr4.write(|w| w.ccr().bits(duty)),
}
}
}
)+
}
}
macro_rules! gp_timer2 {
($({
$TIMX:ident: ($tim:ident, $timXen:ident, $timXrst:ident),
$APB:ident: ($apb:ident, $pclkX:ident),
$res:ident,
},)+) => {
$(
impl PclkSrc for $TIMX {
fn get_clk(clocks: &Clocks) -> Hertz {
clocks.$pclkX()
}
}
impl Periodic for Timer<$TIMX> {}
impl CountDown for Timer<$TIMX> {
type Time = Hertz;
fn start<T>(&mut self, timeout: T)
where
T: Into<Hertz>,
{
self.stop();
let frequency = timeout.into().0;
let timer_clock = $TIMX::get_clk(&self.clocks);
let ticks = timer_clock.0 * if self.clocks.ppre1() == 1 { 1 } else { 2 }
/ frequency;
let psc = u16((ticks - 1) / (1 << 16)).unwrap();
self.tim.psc.write(|w| w.psc().bits(psc));
let arr = u16(ticks / u32(psc + 1)).unwrap();
self.tim.arr.write(|w| unsafe { w.bits(u32(arr)) });
self.tim.egr.write(|w| w.ug().update());
self.clear_update_interrupt_flag();
self.tim.cr1.modify(|_, w| w.cen().enabled());
}
fn wait(&mut self) -> nb::Result<(), Void> {
if self.tim.sr.read().uif().is_clear() {
Err(nb::Error::WouldBlock)
} else {
self.clear_update_interrupt_flag();
Ok(())
}
}
}
impl Timer<$TIMX> {
pub fn $tim<T>(tim: $TIMX, timeout: T, clocks: Clocks, $apb: &mut $APB) -> Self
where
T: Into<Hertz>,
{
$apb.enr().modify(|_, w| w.$timXen().enabled());
$apb.rstr().modify(|_, w| w.$timXrst().reset());
$apb.rstr().modify(|_, w| w.$timXrst().clear_bit());
let mut timer = Timer { clocks, tim };
timer.start(timeout);
timer
}
pub fn listen(&mut self, event: Event) {
match event {
Event::Update => self.tim.dier.write(|w| w.uie().enabled()),
}
}
pub fn unlisten(&mut self, event: Event) {
match event {
Event::Update => self.tim.dier.write(|w| w.uie().disabled()),
}
}
pub fn stop(&mut self) {
self.tim.cr1.modify(|_, w| w.cen().disabled());
}
pub fn clear_update_interrupt_flag(&mut self) {
self.tim.sr.modify(|_, w| w.uif().clear());
}
pub fn release(mut self) -> $TIMX {
self.stop();
self.tim
}
pub fn set_resolution(&mut self, word: $res) {
self.tim.arr.write(|w| unsafe { w.arr().bits(word) } );
}
pub fn get_max_duty(&self) -> $res {
self.tim.arr.read().arr().bits()
}
pub fn set_polarity(&mut self, polarity: Polarity) {
self.tim.ccer.modify(|_, w| w.cc1p().bit(polarity.bit()))
}
pub fn set_complementary_polarity(&mut self, polarity: Polarity) {
self.tim.ccer.modify(|_, w| w.cc1np().bit(polarity.bit()))
}
pub fn disable(&mut self) {
self.tim.ccer.modify(|_, w| w.cc1e().clear_bit())
}
pub fn enable(&mut self) {
self.tim.ccer.modify(|_, w| w.cc1e().set_bit())
}
}
)+
}
}
#[cfg(any(feature = "stm32f301", feature = "stm32f318"))]
basic_timer! {
{
TIM6: (tim6, tim6en, tim6rst),
APB1: (apb1, pclk1),
u16,
},
}
#[cfg(feature = "stm32f302")]
basic_timer! {
{
TIM6: (tim6, tim6en, tim6rst),
APB1: (apb1,pclk1),
u16,
},
}
#[cfg(feature = "stm32f303")]
basic_timer! {
{
TIM6: (tim6, tim6en, tim6rst),
APB1: (apb1, pclk1),
u16,
},
{
TIM7: (tim7, tim7en, tim7rst),
APB1: (apb1, pclk1),
u16,
},
}
#[cfg(feature = "stm32f334")]
basic_timer! {
{
TIM6: (tim6, tim6en, tim6rst),
APB1: (apb1, pclk1),
u16,
},
{
TIM7: (tim7, tim7en, tim7rst),
APB1: (apb1, pclk1),
u16,
},
}
#[cfg(any(feature = "stm32f373", feature = "stm32f378"))]
basic_timer! {
{
TIM6: (tim6, tim6en, tim6rst),
APB1: (apb1, pclk1),
u16,
},
{
TIM7: (tim7, tim7en, tim7rst),
APB1: (apb1, pclk1),
u16,
},
}
#[cfg(any(feature = "stm32f328", feature = "stm32f358", feature = "stm32f398"))]
basic_timer! {
{
TIM6: (tim6, tim6en, tim6rst),
APB1: (apb1, pclk1),
u16,
},
{
TIM7: (tim7, tim7en, tim7rst),
APB1: (apb1, pclk1),
u16,
},
}
#[cfg(any(feature = "stm32f301", feature = "stm32f318"))]
advanced_timer! {
{
TIM1: (tim1, tim1en, tim1rst),
APB2: (apb2, pclk2),
u16,
},
}
#[cfg(feature = "stm32f302")]
advanced_timer! {
{
TIM1: (tim1, tim1en, tim1rst),
APB2: (apb2, pclk2),
u16,
},
}
#[cfg(feature = "stm32f303")]
advanced_timer! {
{
TIM1: (tim1, tim1en, tim1rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM8: (tim8, tim8en, tim8rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM20: (tim20, tim20en, tim20rst),
APB2: (apb2, pclk2),
u16,
},
}
#[cfg(feature = "stm32f334")]
advanced_timer! {
{
TIM1: (tim1, tim1en, tim1rst),
APB2: (apb2, pclk2),
u16,
},
}
#[cfg(any(feature = "stm32f373", feature = "stm32f378"))]
advanced_timer! {
}
#[cfg(any(feature = "stm32f328", feature = "stm32f358", feature = "stm32f398"))]
advanced_timer! {
{
TIM1: (tim1, tim1en, tim1rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM8: (tim8, tim8en, tim8rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM20: (tim20, tim20en, tim20rst),
APB2: (apb2, pclk2),
u16,
},
}
#[cfg(any(feature = "stm32f301", feature = "stm32f318"))]
gp_timer! {
{
TIM2: (tim2, tim2en, tim2rst),
APB1: (apb1, pclk1),
u16,
},
{
TIM15: (tim15, tim15en, tim15rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM16: (tim16, tim16en, tim16rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM17: (tim17, tim17en, tim17rst),
APB2: (apb2, pclk2),
u16,
},
}
#[cfg(feature = "stm32f302")]
gp_timer! {
{
TIM2: (tim2, tim2en, tim2rst),
APB1: (apb1, pclk1),
u16,
},
{
TIM15: (tim15, tim15en, tim15rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM16: (tim16, tim16en, tim16rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM17: (tim17, tim17en, tim17rst),
APB2: (apb2, pclk2),
u16,
},
}
#[cfg(feature = "stm32f303")]
gp_timer! {
{
TIM2: (tim2, tim2en, tim2rst),
APB1: (apb1, pclk1),
u32,
},
{
TIM3: (tim3, tim3en, tim3rst),
APB1: (apb1, pclk1),
u16,
},
{
TIM4: (tim4, tim4en, tim4rst),
APB1: (apb1, pclk1),
u16,
},
}
#[cfg(feature = "stm32f334")]
gp_timer! {
{
TIM2: (tim2, tim2en, tim2rst),
APB1: (apb1, pclk1),
u16,
},
{
TIM3: (tim3, tim3en, tim3rst),
APB1: (apb1, pclk1),
u16,
},
}
#[cfg(any(feature = "stm32f373", feature = "stm32f378"))]
gp_timer! {
{
TIM2: (tim2, tim2en, tim2rst),
APB1: (apb1, pclk1),
u16,
},
{
TIM3: (tim3, tim3en, tim3rst),
APB1: (apb1, pclk1),
u16,
},
{
TIM4: (tim4, tim4en, tim4rst),
APB1: (apb1, pclk1),
u16,
},
}
#[cfg(any(feature = "stm32f328", feature = "stm32f358", feature = "stm32f398"))]
gp_timer! {
{
TIM2: (tim2, tim2en, tim2rst),
APB1: (apb1, pclk1),
u16,
},
{
TIM3: (tim3, tim3en, tim3rst),
APB1: (apb1, pclk1),
u16,
},
{
TIM4: (tim4, tim4en, tim4rst),
APB1: (apb1, pclk1),
u16,
},
}
#[cfg(any(feature = "stm32f301", feature = "stm32f318"))]
gp_timer2! {
{
TIM16: (tim16, tim16en, tim16rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM17: (tim17, tim17en, tim17rst),
APB2: (apb2, pclk2),
u16,
},
}
#[cfg(feature = "stm32f302")]
gp_timer2! {
{
TIM16: (tim16, tim16en, tim16rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM17: (tim17, tim17en, tim17rst),
APB2: (apb2, pclk2),
u16,
},
}
#[cfg(feature = "stm32f303")]
gp_timer2! {
{
TIM16: (tim16, tim16en, tim16rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM17: (tim17, tim17en, tim17rst),
APB2: (apb2, pclk2),
u16,
},
}
#[cfg(feature = "stm32f334")]
gp_timer2! {
{
TIM16: (tim16, tim16en, tim16rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM17: (tim17, tim17en, tim17rst),
APB2: (apb2, pclk2),
u16,
}
}
#[cfg(any(feature = "stm32f373", feature = "stm32f378"))]
gp_timer2! {
{
TIM16: (tim16, tim16en, tim16rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM17: (tim17, tim17en, tim17rst),
APB2: (apb2, pclk2),
u16,
}
}
#[cfg(any(feature = "stm32f328", feature = "stm32f358", feature = "stm32f398"))]
gp_timer2! {
{
TIM16: (tim16, tim16en, tim16rst),
APB2: (apb2, pclk2),
u16,
},
{
TIM17: (tim17, tim17en, tim17rst),
APB2: (apb2, pclk2),
u16,
}
}