#[doc = "Reader of register CFGR3"]
pub type R = crate::R<u32, super::CFGR3>;
#[doc = "Writer for register CFGR3"]
pub type W = crate::W<u32, super::CFGR3>;
#[doc = "Register CFGR3 `reset()`'s with value 0"]
impl crate::ResetValue for super::CFGR3 {
type Type = u32;
#[inline(always)]
fn reset_value() -> Self::Type {
0
}
}
#[doc = "USART1 clock source selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
#[repr(u8)]
pub enum USART1SW_A {
#[doc = "0: PCLK selected as USART clock source"]
PCLK = 0,
#[doc = "1: SYSCLK selected as USART clock source"]
SYSCLK = 1,
#[doc = "2: LSE selected as USART clock source"]
LSE = 2,
#[doc = "3: HSI selected as USART clock source"]
HSI = 3,
}
impl From<USART1SW_A> for u8 {
#[inline(always)]
fn from(variant: USART1SW_A) -> Self {
variant as _
}
}
#[doc = "Reader of field `USART1SW`"]
pub type USART1SW_R = crate::R<u8, USART1SW_A>;
impl USART1SW_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> USART1SW_A {
match self.bits {
0 => USART1SW_A::PCLK,
1 => USART1SW_A::SYSCLK,
2 => USART1SW_A::LSE,
3 => USART1SW_A::HSI,
_ => unreachable!(),
}
}
#[doc = "Checks if the value of the field is `PCLK`"]
#[inline(always)]
pub fn is_pclk(&self) -> bool {
*self == USART1SW_A::PCLK
}
#[doc = "Checks if the value of the field is `SYSCLK`"]
#[inline(always)]
pub fn is_sysclk(&self) -> bool {
*self == USART1SW_A::SYSCLK
}
#[doc = "Checks if the value of the field is `LSE`"]
#[inline(always)]
pub fn is_lse(&self) -> bool {
*self == USART1SW_A::LSE
}
#[doc = "Checks if the value of the field is `HSI`"]
#[inline(always)]
pub fn is_hsi(&self) -> bool {
*self == USART1SW_A::HSI
}
}
#[doc = "Write proxy for field `USART1SW`"]
pub struct USART1SW_W<'a> {
w: &'a mut W,
}
impl<'a> USART1SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: USART1SW_A) -> &'a mut W {
{
self.bits(variant.into())
}
}
#[doc = "PCLK selected as USART clock source"]
#[inline(always)]
pub fn pclk(self) -> &'a mut W {
self.variant(USART1SW_A::PCLK)
}
#[doc = "SYSCLK selected as USART clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(USART1SW_A::SYSCLK)
}
#[doc = "LSE selected as USART clock source"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(USART1SW_A::LSE)
}
#[doc = "HSI selected as USART clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(USART1SW_A::HSI)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !0x03) | ((value as u32) & 0x03);
self.w
}
}
#[doc = "I2C1 clock source selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum I2C1SW_A {
#[doc = "0: HSI clock selected as I2C clock source"]
HSI = 0,
#[doc = "1: SYSCLK clock selected as I2C clock source"]
SYSCLK = 1,
}
impl From<I2C1SW_A> for bool {
#[inline(always)]
fn from(variant: I2C1SW_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `I2C1SW`"]
pub type I2C1SW_R = crate::R<bool, I2C1SW_A>;
impl I2C1SW_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> I2C1SW_A {
match self.bits {
false => I2C1SW_A::HSI,
true => I2C1SW_A::SYSCLK,
}
}
#[doc = "Checks if the value of the field is `HSI`"]
#[inline(always)]
pub fn is_hsi(&self) -> bool {
*self == I2C1SW_A::HSI
}
#[doc = "Checks if the value of the field is `SYSCLK`"]
#[inline(always)]
pub fn is_sysclk(&self) -> bool {
*self == I2C1SW_A::SYSCLK
}
}
#[doc = "Write proxy for field `I2C1SW`"]
pub struct I2C1SW_W<'a> {
w: &'a mut W,
}
impl<'a> I2C1SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2C1SW_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "HSI clock selected as I2C clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(I2C1SW_A::HSI)
}
#[doc = "SYSCLK clock selected as I2C clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(I2C1SW_A::SYSCLK)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 4)) | (((value as u32) & 0x01) << 4);
self.w
}
}
#[doc = "I2C2 clock source selection"]
pub type I2C2SW_A = I2C1SW_A;
#[doc = "Reader of field `I2C2SW`"]
pub type I2C2SW_R = crate::R<bool, I2C1SW_A>;
#[doc = "Write proxy for field `I2C2SW`"]
pub struct I2C2SW_W<'a> {
w: &'a mut W,
}
impl<'a> I2C2SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2C2SW_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "HSI clock selected as I2C clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(I2C1SW_A::HSI)
}
#[doc = "SYSCLK clock selected as I2C clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(I2C1SW_A::SYSCLK)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 5)) | (((value as u32) & 0x01) << 5);
self.w
}
}
#[doc = "USART2 clock source selection"]
pub type USART2SW_A = USART1SW_A;
#[doc = "Reader of field `USART2SW`"]
pub type USART2SW_R = crate::R<u8, USART1SW_A>;
#[doc = "Write proxy for field `USART2SW`"]
pub struct USART2SW_W<'a> {
w: &'a mut W,
}
impl<'a> USART2SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: USART2SW_A) -> &'a mut W {
{
self.bits(variant.into())
}
}
#[doc = "PCLK selected as USART clock source"]
#[inline(always)]
pub fn pclk(self) -> &'a mut W {
self.variant(USART1SW_A::PCLK)
}
#[doc = "SYSCLK selected as USART clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(USART1SW_A::SYSCLK)
}
#[doc = "LSE selected as USART clock source"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(USART1SW_A::LSE)
}
#[doc = "HSI selected as USART clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(USART1SW_A::HSI)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 16)) | (((value as u32) & 0x03) << 16);
self.w
}
}
#[doc = "USART3 clock source selection"]
pub type USART3SW_A = USART1SW_A;
#[doc = "Reader of field `USART3SW`"]
pub type USART3SW_R = crate::R<u8, USART1SW_A>;
#[doc = "Write proxy for field `USART3SW`"]
pub struct USART3SW_W<'a> {
w: &'a mut W,
}
impl<'a> USART3SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: USART3SW_A) -> &'a mut W {
{
self.bits(variant.into())
}
}
#[doc = "PCLK selected as USART clock source"]
#[inline(always)]
pub fn pclk(self) -> &'a mut W {
self.variant(USART1SW_A::PCLK)
}
#[doc = "SYSCLK selected as USART clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(USART1SW_A::SYSCLK)
}
#[doc = "LSE selected as USART clock source"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(USART1SW_A::LSE)
}
#[doc = "HSI selected as USART clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(USART1SW_A::HSI)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 18)) | (((value as u32) & 0x03) << 18);
self.w
}
}
#[doc = "Timer1 clock source selection\n\nValue on reset: 0"]
#[derive(Clone, Copy, Debug, PartialEq)]
pub enum TIM1SW_A {
#[doc = "0: PCLK2 clock (doubled frequency when prescaled)"]
PCLK2 = 0,
#[doc = "1: PLL vco output (running up to 144 MHz)"]
PLL = 1,
}
impl From<TIM1SW_A> for bool {
#[inline(always)]
fn from(variant: TIM1SW_A) -> Self {
variant as u8 != 0
}
}
#[doc = "Reader of field `TIM1SW`"]
pub type TIM1SW_R = crate::R<bool, TIM1SW_A>;
impl TIM1SW_R {
#[doc = r"Get enumerated values variant"]
#[inline(always)]
pub fn variant(&self) -> TIM1SW_A {
match self.bits {
false => TIM1SW_A::PCLK2,
true => TIM1SW_A::PLL,
}
}
#[doc = "Checks if the value of the field is `PCLK2`"]
#[inline(always)]
pub fn is_pclk2(&self) -> bool {
*self == TIM1SW_A::PCLK2
}
#[doc = "Checks if the value of the field is `PLL`"]
#[inline(always)]
pub fn is_pll(&self) -> bool {
*self == TIM1SW_A::PLL
}
}
#[doc = "Write proxy for field `TIM1SW`"]
pub struct TIM1SW_W<'a> {
w: &'a mut W,
}
impl<'a> TIM1SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM1SW_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SW_A::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SW_A::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8);
self.w
}
}
#[doc = "Timer8 clock source selection"]
pub type TIM8SW_A = TIM1SW_A;
#[doc = "Reader of field `TIM8SW`"]
pub type TIM8SW_R = crate::R<bool, TIM1SW_A>;
#[doc = "Write proxy for field `TIM8SW`"]
pub struct TIM8SW_W<'a> {
w: &'a mut W,
}
impl<'a> TIM8SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM8SW_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SW_A::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SW_A::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9);
self.w
}
}
#[doc = "UART4 clock source selection"]
pub type UART4SW_A = USART1SW_A;
#[doc = "Reader of field `UART4SW`"]
pub type UART4SW_R = crate::R<u8, USART1SW_A>;
#[doc = "Write proxy for field `UART4SW`"]
pub struct UART4SW_W<'a> {
w: &'a mut W,
}
impl<'a> UART4SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: UART4SW_A) -> &'a mut W {
{
self.bits(variant.into())
}
}
#[doc = "PCLK selected as USART clock source"]
#[inline(always)]
pub fn pclk(self) -> &'a mut W {
self.variant(USART1SW_A::PCLK)
}
#[doc = "SYSCLK selected as USART clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(USART1SW_A::SYSCLK)
}
#[doc = "LSE selected as USART clock source"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(USART1SW_A::LSE)
}
#[doc = "HSI selected as USART clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(USART1SW_A::HSI)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 20)) | (((value as u32) & 0x03) << 20);
self.w
}
}
#[doc = "UART5 clock source selection"]
pub type UART5SW_A = USART1SW_A;
#[doc = "Reader of field `UART5SW`"]
pub type UART5SW_R = crate::R<u8, USART1SW_A>;
#[doc = "Write proxy for field `UART5SW`"]
pub struct UART5SW_W<'a> {
w: &'a mut W,
}
impl<'a> UART5SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: UART5SW_A) -> &'a mut W {
{
self.bits(variant.into())
}
}
#[doc = "PCLK selected as USART clock source"]
#[inline(always)]
pub fn pclk(self) -> &'a mut W {
self.variant(USART1SW_A::PCLK)
}
#[doc = "SYSCLK selected as USART clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(USART1SW_A::SYSCLK)
}
#[doc = "LSE selected as USART clock source"]
#[inline(always)]
pub fn lse(self) -> &'a mut W {
self.variant(USART1SW_A::LSE)
}
#[doc = "HSI selected as USART clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(USART1SW_A::HSI)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bits(self, value: u8) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x03 << 22)) | (((value as u32) & 0x03) << 22);
self.w
}
}
#[doc = "I2C3 clock source selection"]
pub type I2C3SW_A = I2C1SW_A;
#[doc = "Reader of field `I2C3SW`"]
pub type I2C3SW_R = crate::R<bool, I2C1SW_A>;
#[doc = "Write proxy for field `I2C3SW`"]
pub struct I2C3SW_W<'a> {
w: &'a mut W,
}
impl<'a> I2C3SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: I2C3SW_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "HSI clock selected as I2C clock source"]
#[inline(always)]
pub fn hsi(self) -> &'a mut W {
self.variant(I2C1SW_A::HSI)
}
#[doc = "SYSCLK clock selected as I2C clock source"]
#[inline(always)]
pub fn sysclk(self) -> &'a mut W {
self.variant(I2C1SW_A::SYSCLK)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 6)) | (((value as u32) & 0x01) << 6);
self.w
}
}
#[doc = "Timer20 clock source selection"]
pub type TIM20SW_A = TIM1SW_A;
#[doc = "Reader of field `TIM20SW`"]
pub type TIM20SW_R = crate::R<bool, TIM1SW_A>;
#[doc = "Write proxy for field `TIM20SW`"]
pub struct TIM20SW_W<'a> {
w: &'a mut W,
}
impl<'a> TIM20SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM20SW_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SW_A::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SW_A::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15);
self.w
}
}
#[doc = "Timer15 clock source selection"]
pub type TIM15SW_A = TIM1SW_A;
#[doc = "Reader of field `TIM15SW`"]
pub type TIM15SW_R = crate::R<bool, TIM1SW_A>;
#[doc = "Write proxy for field `TIM15SW`"]
pub struct TIM15SW_W<'a> {
w: &'a mut W,
}
impl<'a> TIM15SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM15SW_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SW_A::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SW_A::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10);
self.w
}
}
#[doc = "Timer16 clock source selection"]
pub type TIM16SW_A = TIM1SW_A;
#[doc = "Reader of field `TIM16SW`"]
pub type TIM16SW_R = crate::R<bool, TIM1SW_A>;
#[doc = "Write proxy for field `TIM16SW`"]
pub struct TIM16SW_W<'a> {
w: &'a mut W,
}
impl<'a> TIM16SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM16SW_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SW_A::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SW_A::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11);
self.w
}
}
#[doc = "Timer17 clock source selection"]
pub type TIM17SW_A = TIM1SW_A;
#[doc = "Reader of field `TIM17SW`"]
pub type TIM17SW_R = crate::R<bool, TIM1SW_A>;
#[doc = "Write proxy for field `TIM17SW`"]
pub struct TIM17SW_W<'a> {
w: &'a mut W,
}
impl<'a> TIM17SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM17SW_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SW_A::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SW_A::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13);
self.w
}
}
#[doc = "Timer2 clock source selection"]
pub type TIM2SW_A = TIM1SW_A;
#[doc = "Reader of field `TIM2SW`"]
pub type TIM2SW_R = crate::R<bool, TIM1SW_A>;
#[doc = "Write proxy for field `TIM2SW`"]
pub struct TIM2SW_W<'a> {
w: &'a mut W,
}
impl<'a> TIM2SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM2SW_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SW_A::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SW_A::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24);
self.w
}
}
#[doc = "Timer34 clock source selection"]
pub type TIM34SW_A = TIM1SW_A;
#[doc = "Reader of field `TIM34SW`"]
pub type TIM34SW_R = crate::R<bool, TIM1SW_A>;
#[doc = "Write proxy for field `TIM34SW`"]
pub struct TIM34SW_W<'a> {
w: &'a mut W,
}
impl<'a> TIM34SW_W<'a> {
#[doc = r"Writes `variant` to the field"]
#[inline(always)]
pub fn variant(self, variant: TIM34SW_A) -> &'a mut W {
{
self.bit(variant.into())
}
}
#[doc = "PCLK2 clock (doubled frequency when prescaled)"]
#[inline(always)]
pub fn pclk2(self) -> &'a mut W {
self.variant(TIM1SW_A::PCLK2)
}
#[doc = "PLL vco output (running up to 144 MHz)"]
#[inline(always)]
pub fn pll(self) -> &'a mut W {
self.variant(TIM1SW_A::PLL)
}
#[doc = r"Sets the field bit"]
#[inline(always)]
pub fn set_bit(self) -> &'a mut W {
self.bit(true)
}
#[doc = r"Clears the field bit"]
#[inline(always)]
pub fn clear_bit(self) -> &'a mut W {
self.bit(false)
}
#[doc = r"Writes raw bits to the field"]
#[inline(always)]
pub fn bit(self, value: bool) -> &'a mut W {
self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25);
self.w
}
}
impl R {
#[doc = "Bits 0:1 - USART1 clock source selection"]
#[inline(always)]
pub fn usart1sw(&self) -> USART1SW_R {
USART1SW_R::new((self.bits & 0x03) as u8)
}
#[doc = "Bit 4 - I2C1 clock source selection"]
#[inline(always)]
pub fn i2c1sw(&self) -> I2C1SW_R {
I2C1SW_R::new(((self.bits >> 4) & 0x01) != 0)
}
#[doc = "Bit 5 - I2C2 clock source selection"]
#[inline(always)]
pub fn i2c2sw(&self) -> I2C2SW_R {
I2C2SW_R::new(((self.bits >> 5) & 0x01) != 0)
}
#[doc = "Bits 16:17 - USART2 clock source selection"]
#[inline(always)]
pub fn usart2sw(&self) -> USART2SW_R {
USART2SW_R::new(((self.bits >> 16) & 0x03) as u8)
}
#[doc = "Bits 18:19 - USART3 clock source selection"]
#[inline(always)]
pub fn usart3sw(&self) -> USART3SW_R {
USART3SW_R::new(((self.bits >> 18) & 0x03) as u8)
}
#[doc = "Bit 8 - Timer1 clock source selection"]
#[inline(always)]
pub fn tim1sw(&self) -> TIM1SW_R {
TIM1SW_R::new(((self.bits >> 8) & 0x01) != 0)
}
#[doc = "Bit 9 - Timer8 clock source selection"]
#[inline(always)]
pub fn tim8sw(&self) -> TIM8SW_R {
TIM8SW_R::new(((self.bits >> 9) & 0x01) != 0)
}
#[doc = "Bits 20:21 - UART4 clock source selection"]
#[inline(always)]
pub fn uart4sw(&self) -> UART4SW_R {
UART4SW_R::new(((self.bits >> 20) & 0x03) as u8)
}
#[doc = "Bits 22:23 - UART5 clock source selection"]
#[inline(always)]
pub fn uart5sw(&self) -> UART5SW_R {
UART5SW_R::new(((self.bits >> 22) & 0x03) as u8)
}
#[doc = "Bit 6 - I2C3 clock source selection"]
#[inline(always)]
pub fn i2c3sw(&self) -> I2C3SW_R {
I2C3SW_R::new(((self.bits >> 6) & 0x01) != 0)
}
#[doc = "Bit 15 - Timer20 clock source selection"]
#[inline(always)]
pub fn tim20sw(&self) -> TIM20SW_R {
TIM20SW_R::new(((self.bits >> 15) & 0x01) != 0)
}
#[doc = "Bit 10 - Timer15 clock source selection"]
#[inline(always)]
pub fn tim15sw(&self) -> TIM15SW_R {
TIM15SW_R::new(((self.bits >> 10) & 0x01) != 0)
}
#[doc = "Bit 11 - Timer16 clock source selection"]
#[inline(always)]
pub fn tim16sw(&self) -> TIM16SW_R {
TIM16SW_R::new(((self.bits >> 11) & 0x01) != 0)
}
#[doc = "Bit 13 - Timer17 clock source selection"]
#[inline(always)]
pub fn tim17sw(&self) -> TIM17SW_R {
TIM17SW_R::new(((self.bits >> 13) & 0x01) != 0)
}
#[doc = "Bit 24 - Timer2 clock source selection"]
#[inline(always)]
pub fn tim2sw(&self) -> TIM2SW_R {
TIM2SW_R::new(((self.bits >> 24) & 0x01) != 0)
}
#[doc = "Bit 25 - Timer34 clock source selection"]
#[inline(always)]
pub fn tim34sw(&self) -> TIM34SW_R {
TIM34SW_R::new(((self.bits >> 25) & 0x01) != 0)
}
}
impl W {
#[doc = "Bits 0:1 - USART1 clock source selection"]
#[inline(always)]
pub fn usart1sw(&mut self) -> USART1SW_W {
USART1SW_W { w: self }
}
#[doc = "Bit 4 - I2C1 clock source selection"]
#[inline(always)]
pub fn i2c1sw(&mut self) -> I2C1SW_W {
I2C1SW_W { w: self }
}
#[doc = "Bit 5 - I2C2 clock source selection"]
#[inline(always)]
pub fn i2c2sw(&mut self) -> I2C2SW_W {
I2C2SW_W { w: self }
}
#[doc = "Bits 16:17 - USART2 clock source selection"]
#[inline(always)]
pub fn usart2sw(&mut self) -> USART2SW_W {
USART2SW_W { w: self }
}
#[doc = "Bits 18:19 - USART3 clock source selection"]
#[inline(always)]
pub fn usart3sw(&mut self) -> USART3SW_W {
USART3SW_W { w: self }
}
#[doc = "Bit 8 - Timer1 clock source selection"]
#[inline(always)]
pub fn tim1sw(&mut self) -> TIM1SW_W {
TIM1SW_W { w: self }
}
#[doc = "Bit 9 - Timer8 clock source selection"]
#[inline(always)]
pub fn tim8sw(&mut self) -> TIM8SW_W {
TIM8SW_W { w: self }
}
#[doc = "Bits 20:21 - UART4 clock source selection"]
#[inline(always)]
pub fn uart4sw(&mut self) -> UART4SW_W {
UART4SW_W { w: self }
}
#[doc = "Bits 22:23 - UART5 clock source selection"]
#[inline(always)]
pub fn uart5sw(&mut self) -> UART5SW_W {
UART5SW_W { w: self }
}
#[doc = "Bit 6 - I2C3 clock source selection"]
#[inline(always)]
pub fn i2c3sw(&mut self) -> I2C3SW_W {
I2C3SW_W { w: self }
}
#[doc = "Bit 15 - Timer20 clock source selection"]
#[inline(always)]
pub fn tim20sw(&mut self) -> TIM20SW_W {
TIM20SW_W { w: self }
}
#[doc = "Bit 10 - Timer15 clock source selection"]
#[inline(always)]
pub fn tim15sw(&mut self) -> TIM15SW_W {
TIM15SW_W { w: self }
}
#[doc = "Bit 11 - Timer16 clock source selection"]
#[inline(always)]
pub fn tim16sw(&mut self) -> TIM16SW_W {
TIM16SW_W { w: self }
}
#[doc = "Bit 13 - Timer17 clock source selection"]
#[inline(always)]
pub fn tim17sw(&mut self) -> TIM17SW_W {
TIM17SW_W { w: self }
}
#[doc = "Bit 24 - Timer2 clock source selection"]
#[inline(always)]
pub fn tim2sw(&mut self) -> TIM2SW_W {
TIM2SW_W { w: self }
}
#[doc = "Bit 25 - Timer34 clock source selection"]
#[inline(always)]
pub fn tim34sw(&mut self) -> TIM34SW_W {
TIM34SW_W { w: self }
}
}