Expand description

Support for the ADC (Analog to Digital Converter) peripheral.

Structs

Represents an Analog to Digital Converter (ADC) peripheral.

Initial configuration data for the ADC peripheral.

Enums

ADC interrupts. See L44 RM, section 16.5: ADC interrupts. Set in the IER register, and cleared in the ISR register.

ADC data register alignment

ADC Clock mode (L44 RM, Section 16.4.3) The input clock is the same for the three ADCs and can be selected between two different clock sources (see Figure 40: ADC clock scheme):

Select single-ended, or differential inputs. Sets bits in the ADC[x]_DIFSEL register.

ADC operation mode

Sets ADC clock prescaler; ADCx_CCR register, PRESC field.

ADC sampling time. Sets ADC_SMPRx register, SMPy field.