Struct stm32_hal2::spi::Spi

pub struct Spi<R> { /* fields omitted */ }

Represents a Serial Peripheral Interface (SPI) peripheral.

Implementations

impl<R> Spi<R> where
    R: Deref<Target = RegisterBlock>, 

pub fn new(
    regs: R,
    device: SpiDevice,
    cfg: SpiConfig,
    baud_rate: BaudRate
) -> Self

Configures the SPI peripheral to operate in full duplex master mode

pub fn reclock(&mut self, baud_rate: BaudRate)

Change the baud rate of the SPI

pub fn disable(&mut self)

L44 RM, section 40.4.9: “Procedure for disabling the SPI” When SPI is disabled, it is mandatory to follow the disable procedures described in this paragraph. It is important to do this before the system enters a low-power mode when the peripheral clock is stopped. Ongoing transactions can be corrupted in this case. In some modes the disable procedure is the only way to stop continuous communication running.

pub fn read(&mut self) -> Result<u8, Error>

Read a single byte if available, or block until it’s available. See L44 RM, section 40.4.9: Data transmission and reception procedures.

pub fn write_one(&mut self, byte: u8) -> Result<(), Error>

Write a single byte if available, or block until it’s available. See L44 RM, section 40.4.9: Data transmission and reception procedures.

pub fn write(&mut self, words: &[u8]) -> Result<(), Error>

Write multiple bytes on the SPI line, blocking until complete. See L44 RM, section 40.4.9: Data transmission and reception procedures.

pub fn transfer<'w>(&mut self, words: &'w mut [u8]) -> Result<(), Error>

Read multiple bytes to a buffer, blocking until complete. See L44 RM, section 40.4.9: Data transmission and reception procedures.

pub unsafe fn write_dma<D>(
    &mut self,
    buf: &[u8],
    channel: DmaChannel,
    dma: &mut Dma<D>
) where
    D: Deref<Target = RegisterBlock>, 

Transmit data using DMA. See L44 RM, section 40.4.9: Communication using DMA. Note that the channel argument has no effect on F3 and L4.

pub unsafe fn read_dma<D>(
    &mut self,
    buf: &mut [u8],
    channel: DmaChannel,
    dma: &mut Dma<D>
) where
    D: Deref<Target = RegisterBlock>, 

Receive data using DMA. See L44 RM, section 40.4.9: Communication using DMA. Note taht the channel argument has no effect on F3 and L4.

pub fn stop_dma<D>(&mut self, channel: DmaChannel, dma: &mut Dma<D>) where
    D: Deref<Target = RegisterBlock>, 

Stop a DMA transfer. Stops the channel, and disables the txdmaen and rxdmaen bits. Run this after each transfer completes - you may wish to do this in an interrupt (eg DMA transfer complete) instead of blocking.

pub fn enable_interrupt(&mut self, interrupt_type: SpiInterrupt)

Enable an interrupt. Note that unlike on other peripherals, there’s no explicit way to clear these. RM: “Writing to the transmit data register always clears the TXE bit. The TXE flag is set by hardware.”