[−][src]Module rza1::vdc50

This is supported on crate feature vdc5 only.

VDC50

Modules

adj0_bkstr_set	`vdc5` ADJ0_BKSTR_SET
adj0_enh_lti1	`vdc5` ADJ0_ENH_LTI1
adj0_enh_lti2	`vdc5` ADJ0_ENH_LTI2
adj0_enh_shp1	`vdc5` ADJ0_ENH_SHP1
adj0_enh_shp2	`vdc5` ADJ0_ENH_SHP2
adj0_enh_shp3	`vdc5` ADJ0_ENH_SHP3
adj0_enh_shp4	`vdc5` ADJ0_ENH_SHP4
adj0_enh_shp5	`vdc5` ADJ0_ENH_SHP5
adj0_enh_shp6	`vdc5` ADJ0_ENH_SHP6
adj0_enh_tim1	`vdc5` ADJ0_ENH_TIM1
adj0_enh_tim2	`vdc5` ADJ0_ENH_TIM2
adj0_enh_tim3	`vdc5` ADJ0_ENH_TIM3
adj0_mtx_cbb_adj0	`vdc5` ADJ0_MTX_CBB_ADJ0
adj0_mtx_cbb_adj1	`vdc5` ADJ0_MTX_CBB_ADJ1
adj0_mtx_crr_adj0	`vdc5` ADJ0_MTX_CRR_ADJ0
adj0_mtx_crr_adj1	`vdc5` ADJ0_MTX_CRR_ADJ1
adj0_mtx_mode	`vdc5` ADJ0_MTX_MODE
adj0_mtx_yg_adj0	`vdc5` ADJ0_MTX_YG_ADJ0
adj0_mtx_yg_adj1	`vdc5` ADJ0_MTX_YG_ADJ1
adj0_update	`vdc5` ADJ0_UPDATE
adj1_bkstr_set	`vdc5` ADJ1_BKSTR_SET
adj1_enh_lti1	`vdc5` ADJ1_ENH_LTI1
adj1_enh_lti2	`vdc5` ADJ1_ENH_LTI2
adj1_enh_shp1	`vdc5` ADJ1_ENH_SHP1
adj1_enh_shp2	`vdc5` ADJ1_ENH_SHP2
adj1_enh_shp3	`vdc5` ADJ1_ENH_SHP3
adj1_enh_shp4	`vdc5` ADJ1_ENH_SHP4
adj1_enh_shp5	`vdc5` ADJ1_ENH_SHP5
adj1_enh_shp6	`vdc5` ADJ1_ENH_SHP6
adj1_enh_tim1	`vdc5` ADJ1_ENH_TIM1
adj1_enh_tim2	`vdc5` ADJ1_ENH_TIM2
adj1_enh_tim3	`vdc5` ADJ1_ENH_TIM3
adj1_mtx_cbb_adj0	`vdc5` ADJ1_MTX_CBB_ADJ0
adj1_mtx_cbb_adj1	`vdc5` ADJ1_MTX_CBB_ADJ1
adj1_mtx_crr_adj0	`vdc5` ADJ1_MTX_CRR_ADJ0
adj1_mtx_crr_adj1	`vdc5` ADJ1_MTX_CRR_ADJ1
adj1_mtx_mode	`vdc5` ADJ1_MTX_MODE
adj1_mtx_yg_adj0	`vdc5` ADJ1_MTX_YG_ADJ0
adj1_mtx_yg_adj1	`vdc5` ADJ1_MTX_YG_ADJ1
adj1_update	`vdc5` ADJ1_UPDATE
gam_b_area1	`vdc5` GAM_B_AREA1
gam_b_area2	`vdc5` GAM_B_AREA2
gam_b_area3	`vdc5` GAM_B_AREA3
gam_b_area4	`vdc5` GAM_B_AREA4
gam_b_area5	`vdc5` GAM_B_AREA5
gam_b_area6	`vdc5` GAM_B_AREA6
gam_b_area7	`vdc5` GAM_B_AREA7
gam_b_area8	`vdc5` GAM_B_AREA8
gam_b_lut1	`vdc5` GAM_B_LUT1
gam_b_lut2	`vdc5` GAM_B_LUT2
gam_b_lut3	`vdc5` GAM_B_LUT3
gam_b_lut4	`vdc5` GAM_B_LUT4
gam_b_lut5	`vdc5` GAM_B_LUT5
gam_b_lut6	`vdc5` GAM_B_LUT6
gam_b_lut7	`vdc5` GAM_B_LUT7
gam_b_lut8	`vdc5` GAM_B_LUT8
gam_b_lut9	`vdc5` GAM_B_LUT9
gam_b_lut10	`vdc5` GAM_B_LUT10
gam_b_lut11	`vdc5` GAM_B_LUT11
gam_b_lut12	`vdc5` GAM_B_LUT12
gam_b_lut13	`vdc5` GAM_B_LUT13
gam_b_lut14	`vdc5` GAM_B_LUT14
gam_b_lut15	`vdc5` GAM_B_LUT15
gam_b_lut16	`vdc5` GAM_B_LUT16
gam_b_update	`vdc5` GAM_B_UPDATE
gam_g_area1	`vdc5` GAM_G_AREA1
gam_g_area2	`vdc5` GAM_G_AREA2
gam_g_area3	`vdc5` GAM_G_AREA3
gam_g_area4	`vdc5` GAM_G_AREA4
gam_g_area5	`vdc5` GAM_G_AREA5
gam_g_area6	`vdc5` GAM_G_AREA6
gam_g_area7	`vdc5` GAM_G_AREA7
gam_g_area8	`vdc5` GAM_G_AREA8
gam_g_lut1	`vdc5` GAM_G_LUT1
gam_g_lut2	`vdc5` GAM_G_LUT2
gam_g_lut3	`vdc5` GAM_G_LUT3
gam_g_lut4	`vdc5` GAM_G_LUT4
gam_g_lut5	`vdc5` GAM_G_LUT5
gam_g_lut6	`vdc5` GAM_G_LUT6
gam_g_lut7	`vdc5` GAM_G_LUT7
gam_g_lut8	`vdc5` GAM_G_LUT8
gam_g_lut9	`vdc5` GAM_G_LUT9
gam_g_lut10	`vdc5` GAM_G_LUT10
gam_g_lut11	`vdc5` GAM_G_LUT11
gam_g_lut12	`vdc5` GAM_G_LUT12
gam_g_lut13	`vdc5` GAM_G_LUT13
gam_g_lut14	`vdc5` GAM_G_LUT14
gam_g_lut15	`vdc5` GAM_G_LUT15
gam_g_lut16	`vdc5` GAM_G_LUT16
gam_g_update	`vdc5` GAM_G_UPDATE
gam_r_area1	`vdc5` GAM_R_AREA1
gam_r_area2	`vdc5` GAM_R_AREA2
gam_r_area3	`vdc5` GAM_R_AREA3
gam_r_area4	`vdc5` GAM_R_AREA4
gam_r_area5	`vdc5` GAM_R_AREA5
gam_r_area6	`vdc5` GAM_R_AREA6
gam_r_area7	`vdc5` GAM_R_AREA7
gam_r_area8	`vdc5` GAM_R_AREA8
gam_r_lut1	`vdc5` GAM_R_LUT1
gam_r_lut2	`vdc5` GAM_R_LUT2
gam_r_lut3	`vdc5` GAM_R_LUT3
gam_r_lut4	`vdc5` GAM_R_LUT4
gam_r_lut5	`vdc5` GAM_R_LUT5
gam_r_lut6	`vdc5` GAM_R_LUT6
gam_r_lut7	`vdc5` GAM_R_LUT7
gam_r_lut8	`vdc5` GAM_R_LUT8
gam_r_lut9	`vdc5` GAM_R_LUT9
gam_r_lut10	`vdc5` GAM_R_LUT10
gam_r_lut11	`vdc5` GAM_R_LUT11
gam_r_lut12	`vdc5` GAM_R_LUT12
gam_r_lut13	`vdc5` GAM_R_LUT13
gam_r_lut14	`vdc5` GAM_R_LUT14
gam_r_lut15	`vdc5` GAM_R_LUT15
gam_r_lut16	`vdc5` GAM_R_LUT16
gam_r_update	`vdc5` GAM_R_UPDATE
gam_sw	`vdc5` GAM_SW
gr0_ab1	`vdc5` GR0_AB1
gr0_ab2	`vdc5` GR0_AB2
gr0_ab3	`vdc5` GR0_AB3
gr0_ab7	`vdc5` GR0_AB7
gr0_ab8	`vdc5` GR0_AB8
gr0_ab9	`vdc5` GR0_AB9
gr0_ab10	`vdc5` GR0_AB10
gr0_ab11	`vdc5` GR0_AB11
gr0_base	`vdc5` GR0_BASE
gr0_clut	`vdc5` GR0_CLUT
gr0_flm1	`vdc5` GR0_FLM1
gr0_flm2	`vdc5` GR0_FLM2
gr0_flm3	`vdc5` GR0_FLM3
gr0_flm4	`vdc5` GR0_FLM4
gr0_flm5	`vdc5` GR0_FLM5
gr0_flm6	`vdc5` GR0_FLM6
gr0_flm_rd	`vdc5` GR0_FLM_RD
gr0_update	`vdc5` GR0_UPDATE
gr1_ab1	`vdc5` GR1_AB1
gr1_ab2	`vdc5` GR1_AB2
gr1_ab3	`vdc5` GR1_AB3
gr1_ab4	`vdc5` GR1_AB4
gr1_ab5	`vdc5` GR1_AB5
gr1_ab6	`vdc5` GR1_AB6
gr1_ab7	`vdc5` GR1_AB7
gr1_ab8	`vdc5` GR1_AB8
gr1_ab9	`vdc5` GR1_AB9
gr1_ab10	`vdc5` GR1_AB10
gr1_ab11	`vdc5` GR1_AB11
gr1_base	`vdc5` GR1_BASE
gr1_clut	`vdc5` GR1_CLUT
gr1_flm1	`vdc5` GR1_FLM1
gr1_flm2	`vdc5` GR1_FLM2
gr1_flm3	`vdc5` GR1_FLM3
gr1_flm4	`vdc5` GR1_FLM4
gr1_flm5	`vdc5` GR1_FLM5
gr1_flm6	`vdc5` GR1_FLM6
gr1_flm_rd	`vdc5` GR1_FLM_RD
gr1_mon	`vdc5` GR1_MON
gr1_update	`vdc5` GR1_UPDATE
gr2_ab1	`vdc5` GR2_AB1
gr2_ab2	`vdc5` GR2_AB2
gr2_ab3	`vdc5` GR2_AB3
gr2_ab4	`vdc5` GR2_AB4
gr2_ab5	`vdc5` GR2_AB5
gr2_ab6	`vdc5` GR2_AB6
gr2_ab7	`vdc5` GR2_AB7
gr2_ab8	`vdc5` GR2_AB8
gr2_ab9	`vdc5` GR2_AB9
gr2_ab10	`vdc5` GR2_AB10
gr2_ab11	`vdc5` GR2_AB11
gr2_base	`vdc5` GR2_BASE
gr2_clut	`vdc5` GR2_CLUT
gr2_flm1	`vdc5` GR2_FLM1
gr2_flm2	`vdc5` GR2_FLM2
gr2_flm3	`vdc5` GR2_FLM3
gr2_flm4	`vdc5` GR2_FLM4
gr2_flm5	`vdc5` GR2_FLM5
gr2_flm6	`vdc5` GR2_FLM6
gr2_flm_rd	`vdc5` GR2_FLM_RD
gr2_mon	`vdc5` GR2_MON
gr2_update	`vdc5` GR2_UPDATE
gr3_ab1	`vdc5` GR3_AB1
gr3_ab2	`vdc5` GR3_AB2
gr3_ab3	`vdc5` GR3_AB3
gr3_ab4	`vdc5` GR3_AB4
gr3_ab5	`vdc5` GR3_AB5
gr3_ab6	`vdc5` GR3_AB6
gr3_ab7	`vdc5` GR3_AB7
gr3_ab8	`vdc5` GR3_AB8
gr3_ab9	`vdc5` GR3_AB9
gr3_ab10	`vdc5` GR3_AB10
gr3_ab11	`vdc5` GR3_AB11
gr3_base	`vdc5` GR3_BASE
gr3_clut_int	`vdc5` GR3_CLUT_INT
gr3_flm1	`vdc5` GR3_FLM1
gr3_flm2	`vdc5` GR3_FLM2
gr3_flm3	`vdc5` GR3_FLM3
gr3_flm4	`vdc5` GR3_FLM4
gr3_flm5	`vdc5` GR3_FLM5
gr3_flm6	`vdc5` GR3_FLM6
gr3_flm_rd	`vdc5` GR3_FLM_RD
gr3_mon	`vdc5` GR3_MON
gr3_update	`vdc5` GR3_UPDATE
gr_oir_ab1	`vdc5` GR_OIR_AB1
gr_oir_ab2	`vdc5` GR_OIR_AB2
gr_oir_ab3	`vdc5` GR_OIR_AB3
gr_oir_ab7	`vdc5` GR_OIR_AB7
gr_oir_ab8	`vdc5` GR_OIR_AB8
gr_oir_ab9	`vdc5` GR_OIR_AB9
gr_oir_ab10	`vdc5` GR_OIR_AB10
gr_oir_ab11	`vdc5` GR_OIR_AB11
gr_oir_base	`vdc5` GR_OIR_BASE
gr_oir_clut	`vdc5` GR_OIR_CLUT
gr_oir_flm1	`vdc5` GR_OIR_FLM1
gr_oir_flm2	`vdc5` GR_OIR_FLM2
gr_oir_flm3	`vdc5` GR_OIR_FLM3
gr_oir_flm4	`vdc5` GR_OIR_FLM4
gr_oir_flm5	`vdc5` GR_OIR_FLM5
gr_oir_flm6	`vdc5` GR_OIR_FLM6
gr_oir_flm_rd	`vdc5` GR_OIR_FLM_RD
gr_oir_mon	`vdc5` GR_OIR_MON
gr_oir_update	`vdc5` GR_OIR_UPDATE
gr_vin_ab1	`vdc5` GR_VIN_AB1
gr_vin_ab2	`vdc5` GR_VIN_AB2
gr_vin_ab3	`vdc5` GR_VIN_AB3
gr_vin_ab4	`vdc5` GR_VIN_AB4
gr_vin_ab5	`vdc5` GR_VIN_AB5
gr_vin_ab6	`vdc5` GR_VIN_AB6
gr_vin_ab7	`vdc5` GR_VIN_AB7
gr_vin_base	`vdc5` GR_VIN_BASE
gr_vin_mon	`vdc5` GR_VIN_MON
gr_vin_update	`vdc5` GR_VIN_UPDATE
imgcnt_drc_reg	`vdc5` IMGCNT_DRC_REG
imgcnt_mtx_cbb_adj0	`vdc5` IMGCNT_MTX_CBB_ADJ0
imgcnt_mtx_cbb_adj1	`vdc5` IMGCNT_MTX_CBB_ADJ1
imgcnt_mtx_crr_adj0	`vdc5` IMGCNT_MTX_CRR_ADJ0
imgcnt_mtx_crr_adj1	`vdc5` IMGCNT_MTX_CRR_ADJ1
imgcnt_mtx_mode	`vdc5` IMGCNT_MTX_MODE
imgcnt_mtx_yg_adj0	`vdc5` IMGCNT_MTX_YG_ADJ0
imgcnt_mtx_yg_adj1	`vdc5` IMGCNT_MTX_YG_ADJ1
imgcnt_nr_cnt0	`vdc5` IMGCNT_NR_CNT0
imgcnt_nr_cnt1	`vdc5` IMGCNT_NR_CNT1
imgcnt_update	`vdc5` IMGCNT_UPDATE
inp_dly_adj	`vdc5` INP_DLY_ADJ
inp_ext_sync_cnt	`vdc5` INP_EXT_SYNC_CNT
inp_sel_cnt	`vdc5` INP_SEL_CNT
inp_update	`vdc5` INP_UPDATE
inp_vsync_ph_adj	`vdc5` INP_VSYNC_PH_ADJ
oir_scl0_ds1	`vdc5` OIR_SCL0_DS1
oir_scl0_ds2	`vdc5` OIR_SCL0_DS2
oir_scl0_ds3	`vdc5` OIR_SCL0_DS3
oir_scl0_ds7	`vdc5` OIR_SCL0_DS7
oir_scl0_frc1	`vdc5` OIR_SCL0_FRC1
oir_scl0_frc2	`vdc5` OIR_SCL0_FRC2
oir_scl0_frc3	`vdc5` OIR_SCL0_FRC3
oir_scl0_frc4	`vdc5` OIR_SCL0_FRC4
oir_scl0_frc5	`vdc5` OIR_SCL0_FRC5
oir_scl0_frc6	`vdc5` OIR_SCL0_FRC6
oir_scl0_frc7	`vdc5` OIR_SCL0_FRC7
oir_scl0_ovr1	`vdc5` OIR_SCL0_OVR1
oir_scl0_update	`vdc5` OIR_SCL0_UPDATE
oir_scl0_us1	`vdc5` OIR_SCL0_US1
oir_scl0_us2	`vdc5` OIR_SCL0_US2
oir_scl0_us3	`vdc5` OIR_SCL0_US3
oir_scl0_us8	`vdc5` OIR_SCL0_US8
oir_scl1_update	`vdc5` OIR_SCL1_UPDATE
oir_scl1_wr1	`vdc5` OIR_SCL1_WR1
oir_scl1_wr2	`vdc5` OIR_SCL1_WR2
oir_scl1_wr3	`vdc5` OIR_SCL1_WR3
oir_scl1_wr4	`vdc5` OIR_SCL1_WR4
oir_scl1_wr5	`vdc5` OIR_SCL1_WR5
oir_scl1_wr6	`vdc5` OIR_SCL1_WR6
oir_scl1_wr7	`vdc5` OIR_SCL1_WR7
out_bright1	`vdc5` OUT_BRIGHT1
out_bright2	`vdc5` OUT_BRIGHT2
out_clk_phase	`vdc5` OUT_CLK_PHASE
out_contrast	`vdc5` OUT_CONTRAST
out_pdtha	`vdc5` OUT_PDTHA
out_set	`vdc5` OUT_SET
out_update	`vdc5` OUT_UPDATE
sc0_scl0_ds1	`vdc5` SC0_SCL0_DS1
sc0_scl0_ds2	`vdc5` SC0_SCL0_DS2
sc0_scl0_ds3	`vdc5` SC0_SCL0_DS3
sc0_scl0_ds4	`vdc5` SC0_SCL0_DS4
sc0_scl0_ds5	`vdc5` SC0_SCL0_DS5
sc0_scl0_ds6	`vdc5` SC0_SCL0_DS6
sc0_scl0_ds7	`vdc5` SC0_SCL0_DS7
sc0_scl0_frc1	`vdc5` SC0_SCL0_FRC1
sc0_scl0_frc2	`vdc5` SC0_SCL0_FRC2
sc0_scl0_frc3	`vdc5` SC0_SCL0_FRC3
sc0_scl0_frc4	`vdc5` SC0_SCL0_FRC4
sc0_scl0_frc5	`vdc5` SC0_SCL0_FRC5
sc0_scl0_frc6	`vdc5` SC0_SCL0_FRC6
sc0_scl0_frc7	`vdc5` SC0_SCL0_FRC7
sc0_scl0_frc9	`vdc5` SC0_SCL0_FRC9
sc0_scl0_int	`vdc5` SC0_SCL0_INT
sc0_scl0_mon0	`vdc5` SC0_SCL0_MON0
sc0_scl0_ovr1	`vdc5` SC0_SCL0_OVR1
sc0_scl0_update	`vdc5` SC0_SCL0_UPDATE
sc0_scl0_us1	`vdc5` SC0_SCL0_US1
sc0_scl0_us2	`vdc5` SC0_SCL0_US2
sc0_scl0_us3	`vdc5` SC0_SCL0_US3
sc0_scl0_us4	`vdc5` SC0_SCL0_US4
sc0_scl0_us5	`vdc5` SC0_SCL0_US5
sc0_scl0_us6	`vdc5` SC0_SCL0_US6
sc0_scl0_us7	`vdc5` SC0_SCL0_US7
sc0_scl0_us8	`vdc5` SC0_SCL0_US8
sc0_scl1_mon1	`vdc5` SC0_SCL1_MON1
sc0_scl1_pbuf0	`vdc5` SC0_SCL1_PBUF0
sc0_scl1_pbuf1	`vdc5` SC0_SCL1_PBUF1
sc0_scl1_pbuf2	`vdc5` SC0_SCL1_PBUF2
sc0_scl1_pbuf3	`vdc5` SC0_SCL1_PBUF3
sc0_scl1_pbuf_cnt	`vdc5` SC0_SCL1_PBUF_CNT
sc0_scl1_pbuf_fld	`vdc5` SC0_SCL1_PBUF_FLD
sc0_scl1_update	`vdc5` SC0_SCL1_UPDATE
sc0_scl1_wr1	`vdc5` SC0_SCL1_WR1
sc0_scl1_wr2	`vdc5` SC0_SCL1_WR2
sc0_scl1_wr3	`vdc5` SC0_SCL1_WR3
sc0_scl1_wr4	`vdc5` SC0_SCL1_WR4
sc0_scl1_wr5	`vdc5` SC0_SCL1_WR5
sc0_scl1_wr6	`vdc5` SC0_SCL1_WR6
sc0_scl1_wr7	`vdc5` SC0_SCL1_WR7
sc0_scl1_wr8	`vdc5` SC0_SCL1_WR8
sc0_scl1_wr9	`vdc5` SC0_SCL1_WR9
sc0_scl1_wr10	`vdc5` SC0_SCL1_WR10
sc0_scl1_wr11	`vdc5` SC0_SCL1_WR11
sc1_scl0_ds1	`vdc5` SC1_SCL0_DS1
sc1_scl0_ds2	`vdc5` SC1_SCL0_DS2
sc1_scl0_ds3	`vdc5` SC1_SCL0_DS3
sc1_scl0_ds4	`vdc5` SC1_SCL0_DS4
sc1_scl0_ds5	`vdc5` SC1_SCL0_DS5
sc1_scl0_ds6	`vdc5` SC1_SCL0_DS6
sc1_scl0_ds7	`vdc5` SC1_SCL0_DS7
sc1_scl0_frc1	`vdc5` SC1_SCL0_FRC1
sc1_scl0_frc2	`vdc5` SC1_SCL0_FRC2
sc1_scl0_frc3	`vdc5` SC1_SCL0_FRC3
sc1_scl0_frc4	`vdc5` SC1_SCL0_FRC4
sc1_scl0_frc5	`vdc5` SC1_SCL0_FRC5
sc1_scl0_frc6	`vdc5` SC1_SCL0_FRC6
sc1_scl0_frc7	`vdc5` SC1_SCL0_FRC7
sc1_scl0_frc9	`vdc5` SC1_SCL0_FRC9
sc1_scl0_int	`vdc5` SC1_SCL0_INT
sc1_scl0_mon0	`vdc5` SC1_SCL0_MON0
sc1_scl0_ovr1	`vdc5` SC1_SCL0_OVR1
sc1_scl0_update	`vdc5` SC1_SCL0_UPDATE
sc1_scl0_us1	`vdc5` SC1_SCL0_US1
sc1_scl0_us2	`vdc5` SC1_SCL0_US2
sc1_scl0_us3	`vdc5` SC1_SCL0_US3
sc1_scl0_us4	`vdc5` SC1_SCL0_US4
sc1_scl0_us5	`vdc5` SC1_SCL0_US5
sc1_scl0_us6	`vdc5` SC1_SCL0_US6
sc1_scl0_us7	`vdc5` SC1_SCL0_US7
sc1_scl0_us8	`vdc5` SC1_SCL0_US8
sc1_scl1_mon1	`vdc5` SC1_SCL1_MON1
sc1_scl1_pbuf0	`vdc5` SC1_SCL1_PBUF0
sc1_scl1_pbuf1	`vdc5` SC1_SCL1_PBUF1
sc1_scl1_pbuf2	`vdc5` SC1_SCL1_PBUF2
sc1_scl1_pbuf3	`vdc5` SC1_SCL1_PBUF3
sc1_scl1_pbuf_cnt	`vdc5` SC1_SCL1_PBUF_CNT
sc1_scl1_pbuf_fld	`vdc5` SC1_SCL1_PBUF_FLD
sc1_scl1_update	`vdc5` SC1_SCL1_UPDATE
sc1_scl1_wr1	`vdc5` SC1_SCL1_WR1
sc1_scl1_wr2	`vdc5` SC1_SCL1_WR2
sc1_scl1_wr3	`vdc5` SC1_SCL1_WR3
sc1_scl1_wr4	`vdc5` SC1_SCL1_WR4
sc1_scl1_wr5	`vdc5` SC1_SCL1_WR5
sc1_scl1_wr6	`vdc5` SC1_SCL1_WR6
sc1_scl1_wr7	`vdc5` SC1_SCL1_WR7
sc1_scl1_wr8	`vdc5` SC1_SCL1_WR8
sc1_scl1_wr9	`vdc5` SC1_SCL1_WR9
sc1_scl1_wr10	`vdc5` SC1_SCL1_WR10
sc1_scl1_wr11	`vdc5` SC1_SCL1_WR11
syscnt_clut	`vdc5` SYSCNT_CLUT
syscnt_int1	`vdc5` SYSCNT_INT1
syscnt_int2	`vdc5` SYSCNT_INT2
syscnt_int3	`vdc5` SYSCNT_INT3
syscnt_int4	`vdc5` SYSCNT_INT4
syscnt_int5	`vdc5` SYSCNT_INT5
syscnt_int6	`vdc5` SYSCNT_INT6
syscnt_panel_clk	`vdc5` SYSCNT_PANEL_CLK
tcon_tim	`vdc5` TCON_TIM
tcon_tim_cpv1	`vdc5` TCON_TIM_CPV1
tcon_tim_cpv2	`vdc5` TCON_TIM_CPV2
tcon_tim_de	`vdc5` TCON_TIM_DE
tcon_tim_pola1	`vdc5` TCON_TIM_POLA1
tcon_tim_pola2	`vdc5` TCON_TIM_POLA2
tcon_tim_polb1	`vdc5` TCON_TIM_POLB1
tcon_tim_polb2	`vdc5` TCON_TIM_POLB2
tcon_tim_stb1	`vdc5` TCON_TIM_STB1
tcon_tim_stb2	`vdc5` TCON_TIM_STB2
tcon_tim_sth1	`vdc5` TCON_TIM_STH1
tcon_tim_sth2	`vdc5` TCON_TIM_STH2
tcon_tim_stva1	`vdc5` TCON_TIM_STVA1
tcon_tim_stva2	`vdc5` TCON_TIM_STVA2
tcon_tim_stvb1	`vdc5` TCON_TIM_STVB1
tcon_tim_stvb2	`vdc5` TCON_TIM_STVB2
tcon_update	`vdc5` TCON_UPDATE

Structs

ADJ0_BKSTR_SET	`vdc5` ADJ0_BKSTR_SET
ADJ0_ENH_LTI1	`vdc5` ADJ0_ENH_LTI1
ADJ0_ENH_LTI2	`vdc5` ADJ0_ENH_LTI2
ADJ0_ENH_SHP1	`vdc5` ADJ0_ENH_SHP1
ADJ0_ENH_SHP2	`vdc5` ADJ0_ENH_SHP2
ADJ0_ENH_SHP3	`vdc5` ADJ0_ENH_SHP3
ADJ0_ENH_SHP4	`vdc5` ADJ0_ENH_SHP4
ADJ0_ENH_SHP5	`vdc5` ADJ0_ENH_SHP5
ADJ0_ENH_SHP6	`vdc5` ADJ0_ENH_SHP6
ADJ0_ENH_TIM1	`vdc5` ADJ0_ENH_TIM1
ADJ0_ENH_TIM2	`vdc5` ADJ0_ENH_TIM2
ADJ0_ENH_TIM3	`vdc5` ADJ0_ENH_TIM3
ADJ0_MTX_CBB_ADJ0	`vdc5` ADJ0_MTX_CBB_ADJ0
ADJ0_MTX_CBB_ADJ1	`vdc5` ADJ0_MTX_CBB_ADJ1
ADJ0_MTX_CRR_ADJ0	`vdc5` ADJ0_MTX_CRR_ADJ0
ADJ0_MTX_CRR_ADJ1	`vdc5` ADJ0_MTX_CRR_ADJ1
ADJ0_MTX_MODE	`vdc5` ADJ0_MTX_MODE
ADJ0_MTX_YG_ADJ0	`vdc5` ADJ0_MTX_YG_ADJ0
ADJ0_MTX_YG_ADJ1	`vdc5` ADJ0_MTX_YG_ADJ1
ADJ0_UPDATE	`vdc5` ADJ0_UPDATE
ADJ1_BKSTR_SET	`vdc5` ADJ1_BKSTR_SET
ADJ1_ENH_LTI1	`vdc5` ADJ1_ENH_LTI1
ADJ1_ENH_LTI2	`vdc5` ADJ1_ENH_LTI2
ADJ1_ENH_SHP1	`vdc5` ADJ1_ENH_SHP1
ADJ1_ENH_SHP2	`vdc5` ADJ1_ENH_SHP2
ADJ1_ENH_SHP3	`vdc5` ADJ1_ENH_SHP3
ADJ1_ENH_SHP4	`vdc5` ADJ1_ENH_SHP4
ADJ1_ENH_SHP5	`vdc5` ADJ1_ENH_SHP5
ADJ1_ENH_SHP6	`vdc5` ADJ1_ENH_SHP6
ADJ1_ENH_TIM1	`vdc5` ADJ1_ENH_TIM1
ADJ1_ENH_TIM2	`vdc5` ADJ1_ENH_TIM2
ADJ1_ENH_TIM3	`vdc5` ADJ1_ENH_TIM3
ADJ1_MTX_CBB_ADJ0	`vdc5` ADJ1_MTX_CBB_ADJ0
ADJ1_MTX_CBB_ADJ1	`vdc5` ADJ1_MTX_CBB_ADJ1
ADJ1_MTX_CRR_ADJ0	`vdc5` ADJ1_MTX_CRR_ADJ0
ADJ1_MTX_CRR_ADJ1	`vdc5` ADJ1_MTX_CRR_ADJ1
ADJ1_MTX_MODE	`vdc5` ADJ1_MTX_MODE
ADJ1_MTX_YG_ADJ0	`vdc5` ADJ1_MTX_YG_ADJ0
ADJ1_MTX_YG_ADJ1	`vdc5` ADJ1_MTX_YG_ADJ1
ADJ1_UPDATE	`vdc5` ADJ1_UPDATE
GAM_B_AREA1	`vdc5` GAM_B_AREA1
GAM_B_AREA2	`vdc5` GAM_B_AREA2
GAM_B_AREA3	`vdc5` GAM_B_AREA3
GAM_B_AREA4	`vdc5` GAM_B_AREA4
GAM_B_AREA5	`vdc5` GAM_B_AREA5
GAM_B_AREA6	`vdc5` GAM_B_AREA6
GAM_B_AREA7	`vdc5` GAM_B_AREA7
GAM_B_AREA8	`vdc5` GAM_B_AREA8
GAM_B_LUT1	`vdc5` GAM_B_LUT1
GAM_B_LUT2	`vdc5` GAM_B_LUT2
GAM_B_LUT3	`vdc5` GAM_B_LUT3
GAM_B_LUT4	`vdc5` GAM_B_LUT4
GAM_B_LUT5	`vdc5` GAM_B_LUT5
GAM_B_LUT6	`vdc5` GAM_B_LUT6
GAM_B_LUT7	`vdc5` GAM_B_LUT7
GAM_B_LUT8	`vdc5` GAM_B_LUT8
GAM_B_LUT9	`vdc5` GAM_B_LUT9
GAM_B_LUT10	`vdc5` GAM_B_LUT10
GAM_B_LUT11	`vdc5` GAM_B_LUT11
GAM_B_LUT12	`vdc5` GAM_B_LUT12
GAM_B_LUT13	`vdc5` GAM_B_LUT13
GAM_B_LUT14	`vdc5` GAM_B_LUT14
GAM_B_LUT15	`vdc5` GAM_B_LUT15
GAM_B_LUT16	`vdc5` GAM_B_LUT16
GAM_B_UPDATE	`vdc5` GAM_B_UPDATE
GAM_G_AREA1	`vdc5` GAM_G_AREA1
GAM_G_AREA2	`vdc5` GAM_G_AREA2
GAM_G_AREA3	`vdc5` GAM_G_AREA3
GAM_G_AREA4	`vdc5` GAM_G_AREA4
GAM_G_AREA5	`vdc5` GAM_G_AREA5
GAM_G_AREA6	`vdc5` GAM_G_AREA6
GAM_G_AREA7	`vdc5` GAM_G_AREA7
GAM_G_AREA8	`vdc5` GAM_G_AREA8
GAM_G_LUT1	`vdc5` GAM_G_LUT1
GAM_G_LUT2	`vdc5` GAM_G_LUT2
GAM_G_LUT3	`vdc5` GAM_G_LUT3
GAM_G_LUT4	`vdc5` GAM_G_LUT4
GAM_G_LUT5	`vdc5` GAM_G_LUT5
GAM_G_LUT6	`vdc5` GAM_G_LUT6
GAM_G_LUT7	`vdc5` GAM_G_LUT7
GAM_G_LUT8	`vdc5` GAM_G_LUT8
GAM_G_LUT9	`vdc5` GAM_G_LUT9
GAM_G_LUT10	`vdc5` GAM_G_LUT10
GAM_G_LUT11	`vdc5` GAM_G_LUT11
GAM_G_LUT12	`vdc5` GAM_G_LUT12
GAM_G_LUT13	`vdc5` GAM_G_LUT13
GAM_G_LUT14	`vdc5` GAM_G_LUT14
GAM_G_LUT15	`vdc5` GAM_G_LUT15
GAM_G_LUT16	`vdc5` GAM_G_LUT16
GAM_G_UPDATE	`vdc5` GAM_G_UPDATE
GAM_R_AREA1	`vdc5` GAM_R_AREA1
GAM_R_AREA2	`vdc5` GAM_R_AREA2
GAM_R_AREA3	`vdc5` GAM_R_AREA3
GAM_R_AREA4	`vdc5` GAM_R_AREA4
GAM_R_AREA5	`vdc5` GAM_R_AREA5
GAM_R_AREA6	`vdc5` GAM_R_AREA6
GAM_R_AREA7	`vdc5` GAM_R_AREA7
GAM_R_AREA8	`vdc5` GAM_R_AREA8
GAM_R_LUT1	`vdc5` GAM_R_LUT1
GAM_R_LUT2	`vdc5` GAM_R_LUT2
GAM_R_LUT3	`vdc5` GAM_R_LUT3
GAM_R_LUT4	`vdc5` GAM_R_LUT4
GAM_R_LUT5	`vdc5` GAM_R_LUT5
GAM_R_LUT6	`vdc5` GAM_R_LUT6
GAM_R_LUT7	`vdc5` GAM_R_LUT7
GAM_R_LUT8	`vdc5` GAM_R_LUT8
GAM_R_LUT9	`vdc5` GAM_R_LUT9
GAM_R_LUT10	`vdc5` GAM_R_LUT10
GAM_R_LUT11	`vdc5` GAM_R_LUT11
GAM_R_LUT12	`vdc5` GAM_R_LUT12
GAM_R_LUT13	`vdc5` GAM_R_LUT13
GAM_R_LUT14	`vdc5` GAM_R_LUT14
GAM_R_LUT15	`vdc5` GAM_R_LUT15
GAM_R_LUT16	`vdc5` GAM_R_LUT16
GAM_R_UPDATE	`vdc5` GAM_R_UPDATE
GAM_SW	`vdc5` GAM_SW
GR0_AB1	`vdc5` GR0_AB1
GR0_AB2	`vdc5` GR0_AB2
GR0_AB3	`vdc5` GR0_AB3
GR0_AB7	`vdc5` GR0_AB7
GR0_AB8	`vdc5` GR0_AB8
GR0_AB9	`vdc5` GR0_AB9
GR0_AB10	`vdc5` GR0_AB10
GR0_AB11	`vdc5` GR0_AB11
GR0_BASE	`vdc5` GR0_BASE
GR0_CLUT	`vdc5` GR0_CLUT
GR0_FLM1	`vdc5` GR0_FLM1
GR0_FLM2	`vdc5` GR0_FLM2
GR0_FLM3	`vdc5` GR0_FLM3
GR0_FLM4	`vdc5` GR0_FLM4
GR0_FLM5	`vdc5` GR0_FLM5
GR0_FLM6	`vdc5` GR0_FLM6
GR0_FLM_RD	`vdc5` GR0_FLM_RD
GR0_UPDATE	`vdc5` GR0_UPDATE
GR1_AB1	`vdc5` GR1_AB1
GR1_AB2	`vdc5` GR1_AB2
GR1_AB3	`vdc5` GR1_AB3
GR1_AB4	`vdc5` GR1_AB4
GR1_AB5	`vdc5` GR1_AB5
GR1_AB6	`vdc5` GR1_AB6
GR1_AB7	`vdc5` GR1_AB7
GR1_AB8	`vdc5` GR1_AB8
GR1_AB9	`vdc5` GR1_AB9
GR1_AB10	`vdc5` GR1_AB10
GR1_AB11	`vdc5` GR1_AB11
GR1_BASE	`vdc5` GR1_BASE
GR1_CLUT	`vdc5` GR1_CLUT
GR1_FLM1	`vdc5` GR1_FLM1
GR1_FLM2	`vdc5` GR1_FLM2
GR1_FLM3	`vdc5` GR1_FLM3
GR1_FLM4	`vdc5` GR1_FLM4
GR1_FLM5	`vdc5` GR1_FLM5
GR1_FLM6	`vdc5` GR1_FLM6
GR1_FLM_RD	`vdc5` GR1_FLM_RD
GR1_MON	`vdc5` GR1_MON
GR1_UPDATE	`vdc5` GR1_UPDATE
GR2_AB1	`vdc5` GR2_AB1
GR2_AB2	`vdc5` GR2_AB2
GR2_AB3	`vdc5` GR2_AB3
GR2_AB4	`vdc5` GR2_AB4
GR2_AB5	`vdc5` GR2_AB5
GR2_AB6	`vdc5` GR2_AB6
GR2_AB7	`vdc5` GR2_AB7
GR2_AB8	`vdc5` GR2_AB8
GR2_AB9	`vdc5` GR2_AB9
GR2_AB10	`vdc5` GR2_AB10
GR2_AB11	`vdc5` GR2_AB11
GR2_BASE	`vdc5` GR2_BASE
GR2_CLUT	`vdc5` GR2_CLUT
GR2_FLM1	`vdc5` GR2_FLM1
GR2_FLM2	`vdc5` GR2_FLM2
GR2_FLM3	`vdc5` GR2_FLM3
GR2_FLM4	`vdc5` GR2_FLM4
GR2_FLM5	`vdc5` GR2_FLM5
GR2_FLM6	`vdc5` GR2_FLM6
GR2_FLM_RD	`vdc5` GR2_FLM_RD
GR2_MON	`vdc5` GR2_MON
GR2_UPDATE	`vdc5` GR2_UPDATE
GR3_AB1	`vdc5` GR3_AB1
GR3_AB2	`vdc5` GR3_AB2
GR3_AB3	`vdc5` GR3_AB3
GR3_AB4	`vdc5` GR3_AB4
GR3_AB5	`vdc5` GR3_AB5
GR3_AB6	`vdc5` GR3_AB6
GR3_AB7	`vdc5` GR3_AB7
GR3_AB8	`vdc5` GR3_AB8
GR3_AB9	`vdc5` GR3_AB9
GR3_AB10	`vdc5` GR3_AB10
GR3_AB11	`vdc5` GR3_AB11
GR3_BASE	`vdc5` GR3_BASE
GR3_CLUT_INT	`vdc5` GR3_CLUT_INT
GR3_FLM1	`vdc5` GR3_FLM1
GR3_FLM2	`vdc5` GR3_FLM2
GR3_FLM3	`vdc5` GR3_FLM3
GR3_FLM4	`vdc5` GR3_FLM4
GR3_FLM5	`vdc5` GR3_FLM5
GR3_FLM6	`vdc5` GR3_FLM6
GR3_FLM_RD	`vdc5` GR3_FLM_RD
GR3_MON	`vdc5` GR3_MON
GR3_UPDATE	`vdc5` GR3_UPDATE
GR_OIR_AB1	`vdc5` GR_OIR_AB1
GR_OIR_AB2	`vdc5` GR_OIR_AB2
GR_OIR_AB3	`vdc5` GR_OIR_AB3
GR_OIR_AB7	`vdc5` GR_OIR_AB7
GR_OIR_AB8	`vdc5` GR_OIR_AB8
GR_OIR_AB9	`vdc5` GR_OIR_AB9
GR_OIR_AB10	`vdc5` GR_OIR_AB10
GR_OIR_AB11	`vdc5` GR_OIR_AB11
GR_OIR_BASE	`vdc5` GR_OIR_BASE
GR_OIR_CLUT	`vdc5` GR_OIR_CLUT
GR_OIR_FLM1	`vdc5` GR_OIR_FLM1
GR_OIR_FLM2	`vdc5` GR_OIR_FLM2
GR_OIR_FLM3	`vdc5` GR_OIR_FLM3
GR_OIR_FLM4	`vdc5` GR_OIR_FLM4
GR_OIR_FLM5	`vdc5` GR_OIR_FLM5
GR_OIR_FLM6	`vdc5` GR_OIR_FLM6
GR_OIR_FLM_RD	`vdc5` GR_OIR_FLM_RD
GR_OIR_MON	`vdc5` GR_OIR_MON
GR_OIR_UPDATE	`vdc5` GR_OIR_UPDATE
GR_VIN_AB1	`vdc5` GR_VIN_AB1
GR_VIN_AB2	`vdc5` GR_VIN_AB2
GR_VIN_AB3	`vdc5` GR_VIN_AB3
GR_VIN_AB4	`vdc5` GR_VIN_AB4
GR_VIN_AB5	`vdc5` GR_VIN_AB5
GR_VIN_AB6	`vdc5` GR_VIN_AB6
GR_VIN_AB7	`vdc5` GR_VIN_AB7
GR_VIN_BASE	`vdc5` GR_VIN_BASE
GR_VIN_MON	`vdc5` GR_VIN_MON
GR_VIN_UPDATE	`vdc5` GR_VIN_UPDATE
IMGCNT_DRC_REG	`vdc5` IMGCNT_DRC_REG
IMGCNT_MTX_CBB_ADJ0	`vdc5` IMGCNT_MTX_CBB_ADJ0
IMGCNT_MTX_CBB_ADJ1	`vdc5` IMGCNT_MTX_CBB_ADJ1
IMGCNT_MTX_CRR_ADJ0	`vdc5` IMGCNT_MTX_CRR_ADJ0
IMGCNT_MTX_CRR_ADJ1	`vdc5` IMGCNT_MTX_CRR_ADJ1
IMGCNT_MTX_MODE	`vdc5` IMGCNT_MTX_MODE
IMGCNT_MTX_YG_ADJ0	`vdc5` IMGCNT_MTX_YG_ADJ0
IMGCNT_MTX_YG_ADJ1	`vdc5` IMGCNT_MTX_YG_ADJ1
IMGCNT_NR_CNT0	`vdc5` IMGCNT_NR_CNT0
IMGCNT_NR_CNT1	`vdc5` IMGCNT_NR_CNT1
IMGCNT_UPDATE	`vdc5` IMGCNT_UPDATE
INP_DLY_ADJ	`vdc5` INP_DLY_ADJ
INP_EXT_SYNC_CNT	`vdc5` INP_EXT_SYNC_CNT
INP_SEL_CNT	`vdc5` INP_SEL_CNT
INP_UPDATE	`vdc5` INP_UPDATE
INP_VSYNC_PH_ADJ	`vdc5` INP_VSYNC_PH_ADJ
OIR_SCL0_DS1	`vdc5` OIR_SCL0_DS1
OIR_SCL0_DS2	`vdc5` OIR_SCL0_DS2
OIR_SCL0_DS3	`vdc5` OIR_SCL0_DS3
OIR_SCL0_DS7	`vdc5` OIR_SCL0_DS7
OIR_SCL0_FRC1	`vdc5` OIR_SCL0_FRC1
OIR_SCL0_FRC2	`vdc5` OIR_SCL0_FRC2
OIR_SCL0_FRC3	`vdc5` OIR_SCL0_FRC3
OIR_SCL0_FRC4	`vdc5` OIR_SCL0_FRC4
OIR_SCL0_FRC5	`vdc5` OIR_SCL0_FRC5
OIR_SCL0_FRC6	`vdc5` OIR_SCL0_FRC6
OIR_SCL0_FRC7	`vdc5` OIR_SCL0_FRC7
OIR_SCL0_OVR1	`vdc5` OIR_SCL0_OVR1
OIR_SCL0_UPDATE	`vdc5` OIR_SCL0_UPDATE
OIR_SCL0_US1	`vdc5` OIR_SCL0_US1
OIR_SCL0_US2	`vdc5` OIR_SCL0_US2
OIR_SCL0_US3	`vdc5` OIR_SCL0_US3
OIR_SCL0_US8	`vdc5` OIR_SCL0_US8
OIR_SCL1_UPDATE	`vdc5` OIR_SCL1_UPDATE
OIR_SCL1_WR1	`vdc5` OIR_SCL1_WR1
OIR_SCL1_WR2	`vdc5` OIR_SCL1_WR2
OIR_SCL1_WR3	`vdc5` OIR_SCL1_WR3
OIR_SCL1_WR4	`vdc5` OIR_SCL1_WR4
OIR_SCL1_WR5	`vdc5` OIR_SCL1_WR5
OIR_SCL1_WR6	`vdc5` OIR_SCL1_WR6
OIR_SCL1_WR7	`vdc5` OIR_SCL1_WR7
OUT_BRIGHT1	`vdc5` OUT_BRIGHT1
OUT_BRIGHT2	`vdc5` OUT_BRIGHT2
OUT_CLK_PHASE	`vdc5` OUT_CLK_PHASE
OUT_CONTRAST	`vdc5` OUT_CONTRAST
OUT_PDTHA	`vdc5` OUT_PDTHA
OUT_SET	`vdc5` OUT_SET
OUT_UPDATE	`vdc5` OUT_UPDATE
RegisterBlock	`vdc5` Register block
SC0_SCL0_DS1	`vdc5` SC0_SCL0_DS1
SC0_SCL0_DS2	`vdc5` SC0_SCL0_DS2
SC0_SCL0_DS3	`vdc5` SC0_SCL0_DS3
SC0_SCL0_DS4	`vdc5` SC0_SCL0_DS4
SC0_SCL0_DS5	`vdc5` SC0_SCL0_DS5
SC0_SCL0_DS6	`vdc5` SC0_SCL0_DS6
SC0_SCL0_DS7	`vdc5` SC0_SCL0_DS7
SC0_SCL0_FRC1	`vdc5` SC0_SCL0_FRC1
SC0_SCL0_FRC2	`vdc5` SC0_SCL0_FRC2
SC0_SCL0_FRC3	`vdc5` SC0_SCL0_FRC3
SC0_SCL0_FRC4	`vdc5` SC0_SCL0_FRC4
SC0_SCL0_FRC5	`vdc5` SC0_SCL0_FRC5
SC0_SCL0_FRC6	`vdc5` SC0_SCL0_FRC6
SC0_SCL0_FRC7	`vdc5` SC0_SCL0_FRC7
SC0_SCL0_FRC9	`vdc5` SC0_SCL0_FRC9
SC0_SCL0_INT	`vdc5` SC0_SCL0_INT
SC0_SCL0_MON0	`vdc5` SC0_SCL0_MON0
SC0_SCL0_OVR1	`vdc5` SC0_SCL0_OVR1
SC0_SCL0_UPDATE	`vdc5` SC0_SCL0_UPDATE
SC0_SCL0_US1	`vdc5` SC0_SCL0_US1
SC0_SCL0_US2	`vdc5` SC0_SCL0_US2
SC0_SCL0_US3	`vdc5` SC0_SCL0_US3
SC0_SCL0_US4	`vdc5` SC0_SCL0_US4
SC0_SCL0_US5	`vdc5` SC0_SCL0_US5
SC0_SCL0_US6	`vdc5` SC0_SCL0_US6
SC0_SCL0_US7	`vdc5` SC0_SCL0_US7
SC0_SCL0_US8	`vdc5` SC0_SCL0_US8
SC0_SCL1_MON1	`vdc5` SC0_SCL1_MON1
SC0_SCL1_PBUF0	`vdc5` SC0_SCL1_PBUF0
SC0_SCL1_PBUF1	`vdc5` SC0_SCL1_PBUF1
SC0_SCL1_PBUF2	`vdc5` SC0_SCL1_PBUF2
SC0_SCL1_PBUF3	`vdc5` SC0_SCL1_PBUF3
SC0_SCL1_PBUF_CNT	`vdc5` SC0_SCL1_PBUF_CNT
SC0_SCL1_PBUF_FLD	`vdc5` SC0_SCL1_PBUF_FLD
SC0_SCL1_UPDATE	`vdc5` SC0_SCL1_UPDATE
SC0_SCL1_WR1	`vdc5` SC0_SCL1_WR1
SC0_SCL1_WR2	`vdc5` SC0_SCL1_WR2
SC0_SCL1_WR3	`vdc5` SC0_SCL1_WR3
SC0_SCL1_WR4	`vdc5` SC0_SCL1_WR4
SC0_SCL1_WR5	`vdc5` SC0_SCL1_WR5
SC0_SCL1_WR6	`vdc5` SC0_SCL1_WR6
SC0_SCL1_WR7	`vdc5` SC0_SCL1_WR7
SC0_SCL1_WR8	`vdc5` SC0_SCL1_WR8
SC0_SCL1_WR9	`vdc5` SC0_SCL1_WR9
SC0_SCL1_WR10	`vdc5` SC0_SCL1_WR10
SC0_SCL1_WR11	`vdc5` SC0_SCL1_WR11
SC1_SCL0_DS1	`vdc5` SC1_SCL0_DS1
SC1_SCL0_DS2	`vdc5` SC1_SCL0_DS2
SC1_SCL0_DS3	`vdc5` SC1_SCL0_DS3
SC1_SCL0_DS4	`vdc5` SC1_SCL0_DS4
SC1_SCL0_DS5	`vdc5` SC1_SCL0_DS5
SC1_SCL0_DS6	`vdc5` SC1_SCL0_DS6
SC1_SCL0_DS7	`vdc5` SC1_SCL0_DS7
SC1_SCL0_FRC1	`vdc5` SC1_SCL0_FRC1
SC1_SCL0_FRC2	`vdc5` SC1_SCL0_FRC2
SC1_SCL0_FRC3	`vdc5` SC1_SCL0_FRC3
SC1_SCL0_FRC4	`vdc5` SC1_SCL0_FRC4
SC1_SCL0_FRC5	`vdc5` SC1_SCL0_FRC5
SC1_SCL0_FRC6	`vdc5` SC1_SCL0_FRC6
SC1_SCL0_FRC7	`vdc5` SC1_SCL0_FRC7
SC1_SCL0_FRC9	`vdc5` SC1_SCL0_FRC9
SC1_SCL0_INT	`vdc5` SC1_SCL0_INT
SC1_SCL0_MON0	`vdc5` SC1_SCL0_MON0
SC1_SCL0_OVR1	`vdc5` SC1_SCL0_OVR1
SC1_SCL0_UPDATE	`vdc5` SC1_SCL0_UPDATE
SC1_SCL0_US1	`vdc5` SC1_SCL0_US1
SC1_SCL0_US2	`vdc5` SC1_SCL0_US2
SC1_SCL0_US3	`vdc5` SC1_SCL0_US3
SC1_SCL0_US4	`vdc5` SC1_SCL0_US4
SC1_SCL0_US5	`vdc5` SC1_SCL0_US5
SC1_SCL0_US6	`vdc5` SC1_SCL0_US6
SC1_SCL0_US7	`vdc5` SC1_SCL0_US7
SC1_SCL0_US8	`vdc5` SC1_SCL0_US8
SC1_SCL1_MON1	`vdc5` SC1_SCL1_MON1
SC1_SCL1_PBUF0	`vdc5` SC1_SCL1_PBUF0
SC1_SCL1_PBUF1	`vdc5` SC1_SCL1_PBUF1
SC1_SCL1_PBUF2	`vdc5` SC1_SCL1_PBUF2
SC1_SCL1_PBUF3	`vdc5` SC1_SCL1_PBUF3
SC1_SCL1_PBUF_CNT	`vdc5` SC1_SCL1_PBUF_CNT
SC1_SCL1_PBUF_FLD	`vdc5` SC1_SCL1_PBUF_FLD
SC1_SCL1_UPDATE	`vdc5` SC1_SCL1_UPDATE
SC1_SCL1_WR1	`vdc5` SC1_SCL1_WR1
SC1_SCL1_WR2	`vdc5` SC1_SCL1_WR2
SC1_SCL1_WR3	`vdc5` SC1_SCL1_WR3
SC1_SCL1_WR4	`vdc5` SC1_SCL1_WR4
SC1_SCL1_WR5	`vdc5` SC1_SCL1_WR5
SC1_SCL1_WR6	`vdc5` SC1_SCL1_WR6
SC1_SCL1_WR7	`vdc5` SC1_SCL1_WR7
SC1_SCL1_WR8	`vdc5` SC1_SCL1_WR8
SC1_SCL1_WR9	`vdc5` SC1_SCL1_WR9
SC1_SCL1_WR10	`vdc5` SC1_SCL1_WR10
SC1_SCL1_WR11	`vdc5` SC1_SCL1_WR11
SYSCNT_CLUT	`vdc5` SYSCNT_CLUT
SYSCNT_INT1	`vdc5` SYSCNT_INT1
SYSCNT_INT2	`vdc5` SYSCNT_INT2
SYSCNT_INT3	`vdc5` SYSCNT_INT3
SYSCNT_INT4	`vdc5` SYSCNT_INT4
SYSCNT_INT5	`vdc5` SYSCNT_INT5
SYSCNT_INT6	`vdc5` SYSCNT_INT6
SYSCNT_PANEL_CLK	`vdc5` SYSCNT_PANEL_CLK
TCON_TIM	`vdc5` TCON_TIM
TCON_TIM_CPV1	`vdc5` TCON_TIM_CPV1
TCON_TIM_CPV2	`vdc5` TCON_TIM_CPV2
TCON_TIM_DE	`vdc5` TCON_TIM_DE
TCON_TIM_POLA1	`vdc5` TCON_TIM_POLA1
TCON_TIM_POLA2	`vdc5` TCON_TIM_POLA2
TCON_TIM_POLB1	`vdc5` TCON_TIM_POLB1
TCON_TIM_POLB2	`vdc5` TCON_TIM_POLB2
TCON_TIM_STB1	`vdc5` TCON_TIM_STB1
TCON_TIM_STB2	`vdc5` TCON_TIM_STB2
TCON_TIM_STH1	`vdc5` TCON_TIM_STH1
TCON_TIM_STH2	`vdc5` TCON_TIM_STH2
TCON_TIM_STVA1	`vdc5` TCON_TIM_STVA1
TCON_TIM_STVA2	`vdc5` TCON_TIM_STVA2
TCON_TIM_STVB1	`vdc5` TCON_TIM_STVB1
TCON_TIM_STVB2	`vdc5` TCON_TIM_STVB2
TCON_UPDATE	`vdc5` TCON_UPDATE