Crate raw_cpuid[−][src]

Expand description

A library to parse the x86 CPUID instruction, written in rust with no external dependencies. The implementation closely resembles the Intel CPUID manual description. The library does only depend on libcore.

The code should be in sync with the latest March 2018 revision of the Intel Architectures Software Developer’s Manual.

Example

use raw_cpuid::CpuId;

let cpuid = CpuId::new();

match cpuid.get_vendor_info() {
    Some(vf) => assert!(vf.as_string() == "GenuineIntel"),
    None => ()
}

let has_sse = match cpuid.get_feature_info() {
    Some(finfo) => finfo.has_sse(),
    None => false
};

if has_sse {
    println!("CPU supports SSE!");
}

match cpuid.get_cache_parameters() {
    Some(cparams) => {
        for cache in cparams {
        let size = cache.associativity() * cache.physical_line_partitions() * cache.coherency_line_size() * cache.sets();
        println!("L{}-Cache size is {}", cache.level(), size);
        }
    }
    None => println!("No cache parameter information available"),
}

Modules

Uses Rust’s cpuid function from the arch module.

Macros

Macro which queries cpuid directly.

Structs

Describes any kind of cache (TLB, Data and Instruction caches plus prefetchers).

Used to iterate over cache information contained in cpuid instruction.

CacheParametersIter

Main type used to query for information about the CPU we’re running on.

Low-level data-structure to store result of cpuid instruction.

Deterministic Address Translation Structure

Deterministic Address Translation Structure Iterator

DirectCacheAccessInfo

EBX:EAX and EDX:ECX provide information on the Enclave Page Cache (EPC) section

ExtendedFeatures

ExtendedFunctionInfo

ExtendedStateInfo

ExtendedStateIter

ExtendedTopologyIter

Iterates over the system topology in order to retrieve more system information at each level of the topology.

ExtendedTopologyLevel

Gives detailed information about the current level in the topology (how many cores, what type etc.).

Information about Hypervisor (https://lwn.net/Articles/301888/)

L2 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID = 2).

L3 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID = 1).

L3MonitoringInfo

MemBwAllocationInfo

Memory Bandwidth Allocation Enumeration Sub-leaf (EAX = 10H, ECX = ResID = 3).

MemoryEncryptionInfo

MonitorMwaitInfo

PerformanceMonitoringInfo

ProcessorFrequencyInfo

Processor Frequency Information

ProcessorSerial

ProcessorTraceInfo

RdtAllocationInfo

RdtMonitoringInfo

Intel SGX Capability Enumeration Leaf, sub-leaf 0 (EAX = 12H, ECX = 0 and ECX = 1)

Iterator over the SGX sub-leafs (ECX >= 2).

SoCVendorAttributesIter

ThermalPowerInfo

Time Stamp Counter and Nominal Core Crystal Clock Information Leaf.

Vendor Info String, that can be for example “AuthenticAMD” or “GenuineIntel”.

Enums

What type of cache are we dealing with?

Deterministic Address Translation cache type (EDX bits 04 – 00)

Identifies the different Hypervisor products.

L2Associativity

Intel SGX EPC Enumeration Leaf, sub-leaves (EAX = 12H, ECX = 2 or higher)

What type of core we have at this level in the topology (real CPU or hyper-threaded).

Constants

CACHE_INFO_TABLE

This table is taken from Intel manual (Section CPUID instruction).