Crate raw_cpuid[−][src]

Modules

Uses Rust's cpuid function from the arch module.

Macro which queries cpuid directly.

CacheInfo	Describes any kind of cache (TLB, Data and Instruction caches plus prefetchers).
CacheInfoIter	Used to iterate over cache information contained in cpuid instruction.
CacheParameter
CacheParametersIter
CpuId	Main type used to query for information about the CPU we're running on.
CpuIdResult	Low-level data-structure to store result of cpuid instruction.
DatInfo	Deterministic Address Translation Structure
DatIter	Deterministic Address Translation Structure Iterator
DirectCacheAccessInfo
EpcSection	EBX:EAX and EDX:ECX provide information on the Enclave Page Cache (EPC) section
ExtendedFeatures
ExtendedFunctionInfo
ExtendedState
ExtendedStateInfo
ExtendedStateIter
ExtendedTopologyIter
ExtendedTopologyLevel
FeatureInfo
L2CatInfo	L2 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID = 2).
L3CatInfo	L3 Cache Allocation Technology Enumeration Sub-leaf (EAX = 10H, ECX = ResID = 1).
L3MonitoringInfo
MemBwAllocationInfo	Memory Bandwidth Allocation Enumeration Sub-leaf (EAX = 10H, ECX = ResID = 3).
MonitorMwaitInfo
PerformanceMonitoringInfo
ProcessorFrequencyInfo	Processor Frequency Information
ProcessorSerial
ProcessorTraceInfo
RdtAllocationInfo
RdtMonitoringInfo
SgxInfo	Intel SGX Capability Enumeration Leaf, sub-leaf 0 (EAX = 12H, ECX = 0 and ECX = 1)
SgxSectionIter	Iterator over the SGX sub-leafs (ECX >= 2).
SoCVendorAttributesIter
SoCVendorBrand
SoCVendorInfo
ThermalPowerInfo
TscInfo	Time Stamp Counter and Nominal Core Crystal Clock Information Leaf.
VendorInfo

CacheInfoType
CacheType
DatType	Deterministic Address Translation cache type (EDX bits 04 -- 00)
L2Associativity
SgxSectionInfo	Intel SGX EPC Enumeration Leaf, sub-leaves (EAX = 12H, ECX = 2 or higher)
TopologyType

This table is taken from Intel manual (Section CPUID instruction).