Crate raw_cpuid

A library to parse the x86 CPUID instruction, written in rust with no external dependencies. The implementation closely resembles the Intel CPUID manual description. The library works with no_std.

Example

use raw_cpuid::CpuId;
let cpuid = CpuId::new();

if let Some(vf) = cpuid.get_vendor_info() {
    assert!(vf.as_str() == "GenuineIntel" || vf.as_str() == "AuthenticAMD");
}

let has_sse = cpuid.get_feature_info().map_or(false, |finfo| finfo.has_sse());
if has_sse {
    println!("CPU supports SSE!");
}

if let Some(cparams) = cpuid.get_cache_parameters() {
    for cache in cparams {
        let size = cache.associativity() * cache.physical_line_partitions() * cache.coherency_line_size() * cache.sets();
        println!("L{}-Cache size is {}", cache.level(), size);
    }
} else {
    println!("No cache parameter information available")
}

Platform support

CPU vendors may choose to not support certain functions/leafs in cpuid or only support them partially. We highlight this with the following emojis throughout the documentation:

• ✅: This struct/function is fully supported by the vendor.
• 🟡: This struct is partially supported by the vendor, refer to individual functions for more information.
• ❌: This struct/function is not supported by the vendor. When queried on this platform, we will return None/false/0 (or some other sane default).
• ❓: This struct/function is not supported by the vendor according to the manual, but the in practice it still may return valid information.

Note that the presence of a ✅ does not guarantee that a specific feature will exist for your CPU – just that it is potentially supported by the vendor on some of its chips. You will still have to query it at runtime.

Modules

native_cpuid

Uses Rust’s cpuid function from the arch module.

Macros

cpuid

Macro which queries cpuid directly.

Structs

ApmInfo

Processor Power Management and RAS Capabilities (LEAF=0x8000_0007).

CacheInfo

Describes any kind of cache (TLB, Data and Instruction caches plus prefetchers).

CacheInfoIter

Iterates over cache information (LEAF=0x02).

CacheParameter

Information about an individual cache in the hierarchy.

CacheParametersIter

Iterator over caches (LEAF=0x04).

CpuId

The main type used to query information about the CPU we’re running on.

CpuIdResult

Low-level data-structure to store result of cpuid instruction.

DatInfo

Deterministic Address Translation Structure

DatIter

Deterministic Address Translation Structure Iterator (LEAF=0x18).

DirectCacheAccessInfo

Direct cache access info (LEAF=0x09).

EpcSection

EBX:EAX and EDX:ECX provide information on the Enclave Page Cache (EPC) section

ExtendedFeatures

Structured Extended Feature Identifiers (LEAF=0x07).

ExtendedProcessorFeatureIdentifiers

Extended Processor and Processor Feature Identifiers (LEAF=0x8000_0001)

ExtendedState

ExtendedState subleaf structure for things that need to be restored.

ExtendedStateInfo

Information for saving/restoring extended register state (LEAF=0x0D).

ExtendedStateIter

Yields ExtendedState structs.

ExtendedTopologyIter

Information about topology (LEAF=0x0B).

ExtendedTopologyLevel

Gives information about the current level in the topology.

FeatureInfo

Processor and Processor Feature Identifiers (LEAF=0x01).

HypervisorInfo

Information about Hypervisor (LEAF=0x4000_0001)

L1CacheTlbInfo

L1 Cache and TLB Information (LEAF=0x8000_0005).

L2And3CacheTlbInfo

L2/L3 Cache and TLB Information (LEAF=0x8000_0006).

L2CatInfo

L2 Cache Allocation Technology Enumeration Sub-leaf (LEAF=0x10, SUBLEAF=2).

L3CatInfo

L3 Cache Allocation Technology Enumeration Sub-leaf (LEAF=0x10, SUBLEAF=1).

L3MonitoringInfo

Information about L3 cache monitoring.

MemBwAllocationInfo

Memory Bandwidth Allocation Enumeration Sub-leaf (LEAF=0x10, SUBLEAF=3).

MemoryEncryptionInfo

Encrypted Memory Capabilities

MonitorMwaitInfo

Information about how monitor/mwait works on this CPU (LEAF=0x05).

PerformanceMonitoringInfo

Info about performance monitoring – how many counters etc. (LEAF=0x0A)

ProcessorBrandString

Processor name (LEAF=0x8000_0002..=0x8000_0004).

ProcessorCapacityAndFeatureInfo

Processor Capacity Parameters and Extended Feature Identification (LEAF=0x8000_0008).

ProcessorFrequencyInfo

Processor Frequency Information (LEAF=0x16).

ProcessorSerial

Processor Serial Number (LEAF=0x3).

ProcessorTraceInfo

Intel Processor Trace Information (LEAF=0x14).

RdtAllocationInfo

Quality of service enforcement information (LEAF=0x10).

RdtMonitoringInfo

Intel Resource Director Technology RDT (LEAF=0x0F).

SgxInfo

Intel SGX Capability Enumeration Leaf (LEAF=0x12).

SgxSectionIter

Iterator over the SGX sub-leafs (ECX >= 2).

SoCVendorAttributesIter

Iterator for SoC vendor attributes.

SoCVendorBrand

A vendor brand string as queried from the cpuid leaf.

SoCVendorInfo

SoC vendor specific information (LEAF=0x17).

SvmFeatures

Information about the SVM features that the processory supports (LEAF=0x8000_000A).

ThermalPowerInfo

Query information about thermal and power management features of the CPU (LEAF=0x06).

TscInfo

Time Stamp Counter/Core Crystal Clock Information (LEAF=0x15).

VendorInfo

Vendor Info String (LEAF=0x0)

Enums

Associativity

Info about cache Associativity.

CacheInfoType

What type of cache are we dealing with?

CacheType

Info about a what a given cache caches (instructions, data, etc.)

DatType

Deterministic Address Translation cache type (EDX bits 04 – 00)

ExtendedRegisterStateLocation

Where the extended register state is stored.

ExtendedRegisterType

What kidn of extended register state this is.

Hypervisor

Identifies the different Hypervisor products.

SgxSectionInfo

Intel SGX EPC Enumeration Leaf

TopologyType

What type of core we have at this level in the topology (real CPU or hyper-threaded).

Constants

CACHE_INFO_TABLE

This table is taken from Intel manual (Section CPUID instruction).