Module probe_rs::architecture::arm::armv7m
source · Expand description
Register types and the core interface for armv7-M
Structs
Application Interrupt and Reset Control Register, AIRCR (see armv7-M Architecture Reference Manual B3.2.6)
The state of a core that can be used to persist core state across calls to multiple different cores.
Debug Core Register Data Register, DCRDR (see armv7-M Architecture Reference Manual C1.6.3)
Debug Exception and Monitor Control Register, DEMCR (see armv7-M Architecture Reference Manual C1.6.5)
Debug Halting Control and Status Register, DHCSR (see armv7-M Architecture Reference Manual C1.6.2)
Flash Patch Control Register, FP_CTRL (see armv7-M Architecture Reference Manual C1.11.3)
Flash Patch Comparator register, FP_COMPn (see armv7-M Architecture Reference Manual C1.11.5)
The FP_COMPn register bit assignments for FPB Version 2 where the Flash Patch is not implemented (see
FpRev1CompX).