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use probe_rs_target::{Architecture, ChipFamily};
use super::{Core, MemoryRegion, RawFlashAlgorithm, RegistryError, TargetDescriptionSource};
use crate::architecture::arm::sequences::nxp::LPC55S69;
use crate::architecture::arm::sequences::ArmDebugSequence;
use crate::architecture::riscv::sequences::esp32c3::ESP32C3;
use crate::architecture::riscv::sequences::{DefaultRiscvSequence, RiscvDebugSequence};
use crate::flashing::FlashLoader;
use std::sync::Arc;
use crate::architecture::arm::sequences::DefaultArmSequence;
#[derive(Clone)]
pub struct Target {
pub name: String,
pub cores: Vec<Core>,
pub flash_algorithms: Vec<RawFlashAlgorithm>,
pub memory_map: Vec<MemoryRegion>,
pub(crate) source: TargetDescriptionSource,
pub debug_sequence: DebugSequence,
}
impl std::fmt::Debug for Target {
fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
write!(
f,
"Target {{
identifier: {:?},
flash_algorithms: {:?},
memory_map: {:?},
}}",
self.name, self.flash_algorithms, self.memory_map
)
}
}
pub type TargetParseError = serde_yaml::Error;
impl Target {
pub(crate) fn new(
family: &ChipFamily,
chip_name: impl AsRef<str>,
) -> Result<Target, RegistryError> {
family
.validate()
.map_err(|e| RegistryError::InvalidChipFamilyDefinition(family.clone(), e))?;
let chip = family
.variants
.iter()
.find(|chip| chip.name == chip_name.as_ref())
.ok_or_else(|| RegistryError::ChipNotFound(chip_name.as_ref().to_string()))?;
let mut flash_algorithms = Vec::new();
for algo_name in chip.flash_algorithms.iter() {
let algo = family.get_algorithm(algo_name).expect(
"The required flash algorithm was not found. This is a bug. Please report it.",
);
flash_algorithms.push(algo.clone());
}
let mut debug_sequence = match chip.cores[0].core_type.architecture() {
Architecture::Arm => DebugSequence::Arm(DefaultArmSequence::create()),
Architecture::Riscv => DebugSequence::Riscv(DefaultRiscvSequence::create()),
};
if chip.name.starts_with("LPC55S69") {
log::warn!("Using custom sequence for LPC55S69");
debug_sequence = DebugSequence::Arm(LPC55S69::create());
} else if chip.name.starts_with("esp32c3") {
log::warn!("Using custom sequence for ESP32c3");
debug_sequence = DebugSequence::Riscv(ESP32C3::create());
}
Ok(Target {
name: chip.name.clone(),
cores: chip.cores.clone(),
flash_algorithms,
source: family.source.clone(),
memory_map: chip.memory_map.clone(),
debug_sequence,
})
}
pub fn architecture(&self) -> Architecture {
let target_arch = self.cores[0].core_type.architecture();
assert!(
self.cores
.iter()
.map(|core| core.core_type.architecture())
.all(|core_arch| core_arch == target_arch),
"Not all cores of the target are of the same architecture. Probe-rs doesn't support this (yet). If you see this, it is a bug. Please file an issue."
);
target_arch
}
pub fn source(&self) -> &TargetDescriptionSource {
&self.source
}
pub fn flash_loader(&self) -> FlashLoader {
FlashLoader::new(self.memory_map.clone(), self.source.clone())
}
pub(crate) fn flash_algorithm_by_name(&self, name: &str) -> Option<&RawFlashAlgorithm> {
self.flash_algorithms.iter().find(|a| a.name == name)
}
pub(crate) fn core_index_by_name(&self, name: &str) -> Option<usize> {
self.cores.iter().position(|c| c.name == name)
}
pub(crate) fn get_memory_region_by_address(&self, address: u32) -> Option<&MemoryRegion> {
self.memory_map.iter().find(|region| match region {
MemoryRegion::Ram(rr) if rr.range.contains(&address) => true,
MemoryRegion::Generic(gr) if gr.range.contains(&address) => true,
MemoryRegion::Nvm(nr) if nr.range.contains(&address) => true,
_ => false,
})
}
}
#[derive(Debug, Clone)]
pub enum TargetSelector {
Unspecified(String),
Specified(Target),
Auto,
}
impl From<&str> for TargetSelector {
fn from(value: &str) -> Self {
TargetSelector::Unspecified(value.into())
}
}
impl From<&String> for TargetSelector {
fn from(value: &String) -> Self {
TargetSelector::Unspecified(value.into())
}
}
impl From<String> for TargetSelector {
fn from(value: String) -> Self {
TargetSelector::Unspecified(value)
}
}
impl From<()> for TargetSelector {
fn from(_value: ()) -> Self {
TargetSelector::Auto
}
}
impl From<Target> for TargetSelector {
fn from(target: Target) -> Self {
TargetSelector::Specified(target)
}
}
#[derive(Clone)]
pub enum DebugSequence {
Arm(Arc<dyn ArmDebugSequence>),
Riscv(Arc<dyn RiscvDebugSequence>),
}