[−][src]Trait probe_rs::CoreInterface
Required methods
pub fn wait_for_core_halted(&mut self, timeout: Duration) -> Result<(), Error>
Wait until the core is halted. If the core does not halt on its own,
a DebugProbeError::Timeout
error will be returned.
pub fn core_halted(&mut self) -> Result<bool, Error>
Check if the core is halted. If the core does not halt on its own,
a CoreError::Timeout
error will be returned.
pub fn status(&mut self) -> Result<CoreStatus, Error>
pub fn halt(&mut self, timeout: Duration) -> Result<CoreInformation, Error>
Try to halt the core. This function ensures the core is actually halted, and
returns a CoreError::Timeout
otherwise.
pub fn run(&mut self) -> Result<(), Error>
pub fn reset(&mut self) -> Result<(), Error>
Reset the core, and then continue to execute instructions. If the core
should be halted after reset, use the reset_and_halt
function.
pub fn reset_and_halt(
&mut self,
timeout: Duration
) -> Result<CoreInformation, Error>
&mut self,
timeout: Duration
) -> Result<CoreInformation, Error>
Reset the core, and then immediately halt. To continue execution after
reset, use the reset
function.
pub fn step(&mut self) -> Result<CoreInformation, Error>
Steps one instruction and then enters halted state again.
pub fn read_core_reg(
&mut self,
address: CoreRegisterAddress
) -> Result<u32, Error>
&mut self,
address: CoreRegisterAddress
) -> Result<u32, Error>
pub fn write_core_reg(
&mut self,
address: CoreRegisterAddress,
value: u32
) -> Result<()>
&mut self,
address: CoreRegisterAddress,
value: u32
) -> Result<()>
pub fn get_available_breakpoint_units(&mut self) -> Result<u32, Error>
pub fn enable_breakpoints(&mut self, state: bool) -> Result<(), Error>
pub fn set_breakpoint(
&mut self,
bp_unit_index: usize,
addr: u32
) -> Result<(), Error>
&mut self,
bp_unit_index: usize,
addr: u32
) -> Result<(), Error>
pub fn clear_breakpoint(&mut self, unit_index: usize) -> Result<(), Error>
pub fn registers(&self) -> &'static RegisterFile
pub fn hw_breakpoints_enabled(&self) -> bool
pub fn architecture(&self) -> Architecture
Get the Architecture
of the Core.
Implementors
impl<'probe> CoreInterface for M0<'probe>
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pub fn wait_for_core_halted(&mut self, timeout: Duration) -> Result<(), Error>
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pub fn core_halted(&mut self) -> Result<bool, Error>
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pub fn halt(&mut self, timeout: Duration) -> Result<CoreInformation, Error>
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pub fn run(&mut self) -> Result<(), Error>
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pub fn step(&mut self) -> Result<CoreInformation, Error>
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pub fn reset(&mut self) -> Result<(), Error>
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pub fn reset_and_halt(
&mut self,
timeout: Duration
) -> Result<CoreInformation, Error>
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&mut self,
timeout: Duration
) -> Result<CoreInformation, Error>
pub fn get_available_breakpoint_units(&mut self) -> Result<u32, Error>
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pub fn enable_breakpoints(&mut self, state: bool) -> Result<(), Error>
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pub fn set_breakpoint(
&mut self,
bp_register_index: usize,
addr: u32
) -> Result<(), Error>
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&mut self,
bp_register_index: usize,
addr: u32
) -> Result<(), Error>
pub fn registers(&self) -> &'static RegisterFile
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pub fn clear_breakpoint(&mut self, bp_unit_index: usize) -> Result<(), Error>
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pub fn hw_breakpoints_enabled(&self) -> bool
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pub fn architecture(&self) -> Architecture
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pub fn status(&mut self) -> Result<CoreStatus, Error>
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pub fn read_core_reg(
&mut self,
address: CoreRegisterAddress
) -> Result<u32, Error>
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&mut self,
address: CoreRegisterAddress
) -> Result<u32, Error>
pub fn write_core_reg(
&mut self,
address: CoreRegisterAddress,
value: u32
) -> Result<()>
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&mut self,
address: CoreRegisterAddress,
value: u32
) -> Result<()>
impl<'probe> CoreInterface for M4<'probe>
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pub fn wait_for_core_halted(&mut self, timeout: Duration) -> Result<(), Error>
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pub fn core_halted(&mut self) -> Result<bool, Error>
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pub fn status(&mut self) -> Result<CoreStatus, Error>
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pub fn read_core_reg(
&mut self,
address: CoreRegisterAddress
) -> Result<u32, Error>
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&mut self,
address: CoreRegisterAddress
) -> Result<u32, Error>
pub fn write_core_reg(
&mut self,
address: CoreRegisterAddress,
value: u32
) -> Result<()>
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&mut self,
address: CoreRegisterAddress,
value: u32
) -> Result<()>
pub fn halt(&mut self, timeout: Duration) -> Result<CoreInformation, Error>
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pub fn run(&mut self) -> Result<(), Error>
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pub fn step(&mut self) -> Result<CoreInformation, Error>
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pub fn reset(&mut self) -> Result<(), Error>
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pub fn reset_and_halt(
&mut self,
timeout: Duration
) -> Result<CoreInformation, Error>
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&mut self,
timeout: Duration
) -> Result<CoreInformation, Error>
pub fn get_available_breakpoint_units(&mut self) -> Result<u32, Error>
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pub fn enable_breakpoints(&mut self, state: bool) -> Result<(), Error>
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pub fn set_breakpoint(
&mut self,
bp_unit_index: usize,
addr: u32
) -> Result<(), Error>
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&mut self,
bp_unit_index: usize,
addr: u32
) -> Result<(), Error>
pub fn registers(&self) -> &'static RegisterFile
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pub fn clear_breakpoint(&mut self, bp_unit_index: usize) -> Result<(), Error>
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pub fn hw_breakpoints_enabled(&self) -> bool
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pub fn architecture(&self) -> Architecture
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impl<'probe> CoreInterface for M33<'probe>
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pub fn wait_for_core_halted(&mut self, timeout: Duration) -> Result<(), Error>
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pub fn core_halted(&mut self) -> Result<bool, Error>
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pub fn halt(&mut self, timeout: Duration) -> Result<CoreInformation, Error>
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pub fn run(&mut self) -> Result<(), Error>
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pub fn reset(&mut self) -> Result<(), Error>
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pub fn reset_and_halt(
&mut self,
timeout: Duration
) -> Result<CoreInformation, Error>
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&mut self,
timeout: Duration
) -> Result<CoreInformation, Error>
pub fn step(&mut self) -> Result<CoreInformation, Error>
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pub fn read_core_reg(
&mut self,
address: CoreRegisterAddress
) -> Result<u32, Error>
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&mut self,
address: CoreRegisterAddress
) -> Result<u32, Error>
pub fn write_core_reg(
&mut self,
address: CoreRegisterAddress,
value: u32
) -> Result<()>
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&mut self,
address: CoreRegisterAddress,
value: u32
) -> Result<()>
pub fn get_available_breakpoint_units(&mut self) -> Result<u32, Error>
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pub fn enable_breakpoints(&mut self, state: bool) -> Result<(), Error>
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pub fn set_breakpoint(
&mut self,
bp_unit_index: usize,
addr: u32
) -> Result<(), Error>
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&mut self,
bp_unit_index: usize,
addr: u32
) -> Result<(), Error>
pub fn registers(&self) -> &'static RegisterFile
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pub fn clear_breakpoint(&mut self, bp_unit_index: usize) -> Result<(), Error>
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pub fn hw_breakpoints_enabled(&self) -> bool
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pub fn architecture(&self) -> Architecture
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pub fn status(&mut self) -> Result<CoreStatus, Error>
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impl<'probe> CoreInterface for Riscv32<'probe>
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pub fn wait_for_core_halted(&mut self, timeout: Duration) -> Result<(), Error>
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pub fn core_halted(&mut self) -> Result<bool, Error>
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pub fn halt(&mut self, timeout: Duration) -> Result<CoreInformation, Error>
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pub fn run(&mut self) -> Result<(), Error>
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pub fn reset(&mut self) -> Result<(), Error>
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pub fn reset_and_halt(
&mut self,
_timeout: Duration
) -> Result<CoreInformation, Error>
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&mut self,
_timeout: Duration
) -> Result<CoreInformation, Error>
pub fn step(&mut self) -> Result<CoreInformation, Error>
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pub fn read_core_reg(
&mut self,
address: CoreRegisterAddress
) -> Result<u32, Error>
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&mut self,
address: CoreRegisterAddress
) -> Result<u32, Error>
pub fn write_core_reg(
&mut self,
address: CoreRegisterAddress,
value: u32
) -> Result<()>
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&mut self,
address: CoreRegisterAddress,
value: u32
) -> Result<()>
pub fn get_available_breakpoint_units(&mut self) -> Result<u32, Error>
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pub fn enable_breakpoints(&mut self, _state: bool) -> Result<(), Error>
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pub fn set_breakpoint(
&mut self,
bp_unit_index: usize,
addr: u32
) -> Result<(), Error>
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&mut self,
bp_unit_index: usize,
addr: u32
) -> Result<(), Error>