Module nrf52::uarte0

UART with EasyDMA

Modules

baudrate	Baud rate. Accuracy depends on the HFCLK source selected.
config	Configuration of parity and hardware flow control
enable	Enable UART
errorsrc	Error source
events_cts	CTS is activated (set low). Clear To Send.
events_endrx	Receive buffer is filled up
events_endtx	Last TX byte transmitted
events_error	Error detected
events_ncts	CTS is deactivated (set high). Not Clear To Send.
events_rxdrdy	Data received in RXD (but potentially not yet transferred to Data RAM)
events_rxstarted	UART receiver has started
events_rxto	Receiver timeout
events_txdrdy	Data sent from TXD
events_txstarted	UART transmitter has started
events_txstopped	Transmitter stopped
inten	Enable or disable interrupt
intenclr	Disable interrupt
intenset	Enable interrupt
shorts	Shortcut register
tasks_flushrx	Flush RX FIFO into RX buffer
tasks_startrx	Start UART receiver
tasks_starttx	Start UART transmitter
tasks_stoprx	Stop UART receiver
tasks_stoptx	Stop UART transmitter

Structs

BAUDRATE	Baud rate. Accuracy depends on the HFCLK source selected.
CONFIG	Configuration of parity and hardware flow control
ENABLE	Enable UART
ERRORSRC	Error source
EVENTS_CTS	CTS is activated (set low). Clear To Send.
EVENTS_ENDRX	Receive buffer is filled up
EVENTS_ENDTX	Last TX byte transmitted
EVENTS_ERROR	Error detected
EVENTS_NCTS	CTS is deactivated (set high). Not Clear To Send.
EVENTS_RXDRDY	Data received in RXD (but potentially not yet transferred to Data RAM)
EVENTS_RXSTARTED	UART receiver has started
EVENTS_RXTO	Receiver timeout
EVENTS_TXDRDY	Data sent from TXD
EVENTS_TXSTARTED	UART transmitter has started
EVENTS_TXSTOPPED	Transmitter stopped
INTEN	Enable or disable interrupt
INTENCLR	Disable interrupt
INTENSET	Enable interrupt
RegisterBlock	Register block
SHORTS	Shortcut register
TASKS_FLUSHRX	Flush RX FIFO into RX buffer
TASKS_STARTRX	Start UART receiver
TASKS_STARTTX	Start UART transmitter
TASKS_STOPRX	Stop UART receiver
TASKS_STOPTX	Stop UART transmitter