Module msp432p401r::eusci_a3::ucax_ctlw0 [−][src]
eUSCI_Ax Control Word Register 0
Structs
R | Register |
UC7BIT_R | Field |
UC7BIT_W | Field |
UCAXCTLW0_SPEC | eUSCI_Ax Control Word Register 0 |
UCBRKIE_R | Field |
UCBRKIE_W | Field |
UCDORM_R | Field |
UCDORM_W | Field |
UCMODE_R | Field |
UCMODE_W | Field |
UCMSB_R | Field |
UCMSB_W | Field |
UCPAR_R | Field |
UCPAR_W | Field |
UCPEN_R | Field |
UCPEN_W | Field |
UCRXEIE_R | Field |
UCRXEIE_W | Field |
UCSPB_R | Field |
UCSPB_W | Field |
UCSSEL_R | Field |
UCSSEL_W | Field |
UCSWRST_R | Field |
UCSWRST_W | Field |
UCSYNC_R | Field |
UCSYNC_W | Field |
UCTXADDR_R | Field |
UCTXADDR_W | Field |
UCTXBRK_R | Field |
UCTXBRK_W | Field |
W | Register |
Enums
UC7BIT_A | Character length |
UCBRKIE_A | Receive break character interrupt enable |
UCDORM_A | Dormant |
UCMODE_A | eUSCI_A mode |
UCMSB_A | MSB first select |
UCPAR_A | Parity select |
UCPEN_A | Parity enable |
UCRXEIE_A | Receive erroneous-character interrupt enable |
UCSPB_A | Stop bit select |
UCSSEL_A | eUSCI_A clock source select |
UCSWRST_A | Software reset enable |
UCSYNC_A | Synchronous mode enable |
UCTXADDR_A | Transmit address |
UCTXBRK_A | Transmit break |