[][src]Module msp432p401r::dma

DMA

Modules

dma_altbase

Channel Alternate Control Data Base Pointer Register

dma_altclr

Channel Primary-Alternate Clear Register

dma_altset

Channel Primary-Alternate Set Register

dma_cfg

Configuration Register

dma_ch_srccfg

Channel n Source Configuration Register

dma_ctlbase

Channel Control Data Base Pointer Register

dma_device_cfg

Device Configuration Status

dma_enaclr

Channel Enable Clear Register

dma_enaset

Channel Enable Set Register

dma_errclr

Bus Error Clear Register

dma_int0_clrflg

Interrupt 0 Source Channel Clear Flag Register

dma_int0_srcflg

Interrupt 0 Source Channel Flag Register

dma_int1_srccfg

Interrupt 1 Source Channel Configuration

dma_int2_srccfg

Interrupt 2 Source Channel Configuration Register

dma_int3_srccfg

Interrupt 3 Source Channel Configuration Register

dma_prioclr

Channel Priority Clear Register

dma_prioset

Channel Priority Set Register

dma_reqmaskclr

Channel Request Mask Clear Register

dma_reqmaskset

Channel Request Mask Set Register

dma_stat

Status Register

dma_sw_chtrig

Software Channel Trigger Register

dma_swreq

Channel Software Request Register

dma_useburstclr

Channel Useburst Clear Register

dma_useburstset

Channel Useburst Set Register

dma_waitstat

Channel Wait on Request Status Register

Structs

RegisterBlock

Register block

Type Definitions

DMA_ALTBASE

Channel Alternate Control Data Base Pointer Register

DMA_ALTCLR

Channel Primary-Alternate Clear Register

DMA_ALTSET

Channel Primary-Alternate Set Register

DMA_CFG

Configuration Register

DMA_CH_SRCCFG

Channel n Source Configuration Register

DMA_CTLBASE

Channel Control Data Base Pointer Register

DMA_DEVICE_CFG

Device Configuration Status

DMA_ENACLR

Channel Enable Clear Register

DMA_ENASET

Channel Enable Set Register

DMA_ERRCLR

Bus Error Clear Register

DMA_INT0_CLRFLG

Interrupt 0 Source Channel Clear Flag Register

DMA_INT0_SRCFLG

Interrupt 0 Source Channel Flag Register

DMA_INT1_SRCCFG

Interrupt 1 Source Channel Configuration

DMA_INT2_SRCCFG

Interrupt 2 Source Channel Configuration Register

DMA_INT3_SRCCFG

Interrupt 3 Source Channel Configuration Register

DMA_PRIOCLR

Channel Priority Clear Register

DMA_PRIOSET

Channel Priority Set Register

DMA_REQMASKCLR

Channel Request Mask Clear Register

DMA_REQMASKSET

Channel Request Mask Set Register

DMA_STAT

Status Register

DMA_SWREQ

Channel Software Request Register

DMA_SW_CHTRIG

Software Channel Trigger Register

DMA_USEBURSTCLR

Channel Useburst Clear Register

DMA_USEBURSTSET

Channel Useburst Set Register

DMA_WAITSTAT

Channel Wait on Request Status Register