Crate moore_vhdl_syntax

A lexical analyzer and parser for VHDL source files as per IEEE 1076-2008.

Modules

ast

This module implements an abstract syntax tree for VHDL. It is emitted by the parser.

lexer

A VHDL lexer. This module implements lexical analysis of VHDL source files. It converts a stream of input bytes into a stream of language tokens such as identifiers, literals, and symbols.

parser

A VHDL parser.

Functions

parse