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// Copyright (c) 2017 Fabian Schuiki

//! The medium-level intermediate representation for SystemVerilog.
//!
//! Represents a fully typed SystemVerilog design with all implicit operations
//! converted into explicit nodes.

#![deny(missing_docs)]

pub mod lower;
mod lvalue;
mod rvalue;

pub use lvalue::*;
pub use rvalue::*;