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#[doc = r" Value read from the register"] pub struct R { bits: u32, } #[doc = r" Value to write to the register"] pub struct W { bits: u32, } impl super::ISFR { #[doc = r" Modifies the contents of the register"] #[inline] pub fn modify<F>(&self, f: F) where for<'w> F: FnOnce(&R, &'w mut W) -> &'w mut W, { let bits = self.register.get(); let r = R { bits: bits }; let mut w = W { bits: bits }; f(&r, &mut w); self.register.set(w.bits); } #[doc = r" Reads the contents of the register"] #[inline] pub fn read(&self) -> R { R { bits: self.register.get(), } } #[doc = r" Writes to the register"] #[inline] pub fn write<F>(&self, f: F) where F: FnOnce(&mut W) -> &mut W, { let mut w = W::reset_value(); f(&mut w); self.register.set(w.bits); } #[doc = r" Writes the reset value to the register"] #[inline] pub fn reset(&self) { self.write(|w| w) } } #[doc = "Possible values of the field `ISF`"] #[derive(Clone, Copy, Debug, PartialEq)] pub enum ISFR { #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, #[doc = r" Reserved"] _Reserved(u32), } impl ISFR { #[doc = r" Value of the field as raw bits"] #[inline] pub fn bits(&self) -> u32 { match *self { ISFR::_0 => 0, ISFR::_1 => 1, ISFR::_Reserved(bits) => bits, } } #[allow(missing_docs)] #[doc(hidden)] #[inline] pub fn _from(value: u32) -> ISFR { match value { 0 => ISFR::_0, 1 => ISFR::_1, i => ISFR::_Reserved(i), } } #[doc = "Checks if the value of the field is `_0`"] #[inline] pub fn is_0(&self) -> bool { *self == ISFR::_0 } #[doc = "Checks if the value of the field is `_1`"] #[inline] pub fn is_1(&self) -> bool { *self == ISFR::_1 } } #[doc = "Values that can be written to the field `ISF`"] pub enum ISFW { #[doc = "Configured interrupt is not detected."] _0, #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] _1, } impl ISFW { #[allow(missing_docs)] #[doc(hidden)] #[inline] pub fn _bits(&self) -> u32 { match *self { ISFW::_0 => 0, ISFW::_1 => 1, } } } #[doc = r" Proxy"] pub struct _ISFW<'a> { w: &'a mut W, } impl<'a> _ISFW<'a> { #[doc = r" Writes `variant` to the field"] #[inline] pub fn variant(self, variant: ISFW) -> &'a mut W { unsafe { self.bits(variant._bits()) } } #[doc = "Configured interrupt is not detected."] #[inline] pub fn _0(self) -> &'a mut W { self.variant(ISFW::_0) } #[doc = "Configured interrupt is detected. If the pin is configured to generate a DMA request, then the corresponding flag will be cleared automatically at the completion of the requested DMA transfer. Otherwise, the flag remains set until a logic 1 is written to the flag. If the pin is configured for a level sensitive interrupt and the pin remains asserted, then the flag is set again immediately after it is cleared."] #[inline] pub fn _1(self) -> &'a mut W { self.variant(ISFW::_1) } #[doc = r" Writes raw bits to the field"] #[inline] pub unsafe fn bits(self, value: u32) -> &'a mut W { const MASK: u32 = 4294967295; const OFFSET: u8 = 0; self.w.bits &= !((MASK as u32) << OFFSET); self.w.bits |= ((value & MASK) as u32) << OFFSET; self.w } } impl R { #[doc = r" Value of the register as raw bits"] #[inline] pub fn bits(&self) -> u32 { self.bits } #[doc = "Bits 0:31 - Interrupt Status Flag"] #[inline] pub fn isf(&self) -> ISFR { ISFR::_from({ const MASK: u32 = 4294967295; const OFFSET: u8 = 0; ((self.bits >> OFFSET) & MASK as u32) as u32 }) } } impl W { #[doc = r" Reset value of the register"] #[inline] pub fn reset_value() -> W { W { bits: 0 } } #[doc = r" Writes raw bits to the register"] #[inline] pub unsafe fn bits(&mut self, bits: u32) -> &mut Self { self.bits = bits; self } #[doc = "Bits 0:31 - Interrupt Status Flag"] #[inline] pub fn isf(&mut self) -> _ISFW { _ISFW { w: self } } }