Struct I2S 

pub struct I2S { /* private fields */ }

Implementations

impl I2S

pub fn new(i2s: I2S, pins: Pins) -> I2S

Takes ownership of the raw I2S peripheral, returning a safe wrapper in controller mode.

pub fn enable(&self) -> &I2S

Enables the I2S module.

pub fn disable(&self) -> &I2S

Disables the I2S module.

pub fn start(&self) -> &I2S

Starts I2S transfer.

pub fn stop(&self) -> &I2S

Stops the I2S transfer and waits until it has stopped.

pub fn set_tx_enabled(&self, enabled: bool) -> &I2S

Enables/disables I2S transmission (TX).

pub fn set_rx_enabled(&self, enabled: bool) -> &I2S

Enables/disables I2S reception (RX).

pub fn set_mck_frequency(&self, freq: MckFreq) -> &I2S

Sets MCK generator frequency.

pub fn set_ratio(&self, ratio: Ratio) -> &I2S

Sets MCK / LRCK ratio.

pub fn set_sample_width(&self, width: SampleWidth) -> &I2S

Sets sample width.

pub fn set_align(&self, align: Align) -> &I2S

Sets the sample alignment within a frame.

pub fn set_format(&self, format: Format) -> &I2S

Sets the frame format.

pub fn set_channels(&self, channels: Channels) -> &I2S

Sets the I2S channel configuration.

pub fn channels(&self) -> Channels

Returns the I2S channel configuration.

pub fn rx<W, B>(self, buffer: B) -> Result<Transfer<B>, Error>

where W: SupportedWordSize, B: WriteBuffer<Word = W> + 'static,

Receives data into the given buffer until it’s filled. Buffer address must be 4 byte aligned and located in RAM. Returns a value that represents the in-progress DMA transfer.

pub fn transfer<W, TxB, RxB>( self, tx_buffer: TxB, rx_buffer: RxB, ) -> Result<TransferFullDuplex<TxB, RxB>, Error>

where W: SupportedWordSize, TxB: ReadBuffer<Word = W> + 'static, RxB: WriteBuffer<Word = W> + 'static,

Full duplex DMA transfer. Transmits the given tx_buffer while simultaneously receiving data into the given rx_buffer until it is filled. The buffers must be of equal size and their addresses must be 4 byte aligned and located in RAM. Returns a value that represents the in-progress DMA transfer.

pub fn tx<W, B>(self, buffer: B) -> Result<Transfer<B>, Error>

where W: SupportedWordSize, B: ReadBuffer<Word = W> + 'static,

Transmits the given tx_buffer. Buffer address must be 4 byte aligned and located in RAM. Returns a value that represents the in-progress DMA transfer.

pub fn set_tx_ptr(&self, addr: u32) -> Result<(), Error>

Sets the transmit buffer RAM start address.

pub unsafe fn set_rx_ptr(&self, addr: u32) -> Result<(), Error>

Sets the receive buffer RAM start address.

Safety

addr must be the address of writeable static memory of sufficient size to hold the specified receive buffer.

pub unsafe fn set_buffersize(&self, n_32bit: u32) -> Result<(), Error>

Sets the size (in 32bit words) of the receive and transmit buffers.

Safety

n_32bit must be no longer than the DMA buffer pointed to by this struct.

pub fn is_event_triggered(&self, event: I2SEvent) -> bool

Checks if an event has been triggered.

pub fn reset_event(&self, event: I2SEvent)

Marks event as handled.

pub fn enable_interrupt(&self, event: I2SEvent) -> &I2S

Enables interrupt triggering on the specified event.

pub fn disable_interrupt(&self, event: I2SEvent) -> &I2S

Disables interrupt triggering on the specified event.

pub fn event_stopped(&self) -> &Reg<EVENTS_STOPPED_SPEC>

Returns reference to Stopped event endpoint for PPI.

pub fn event_rx_ptr_updated(&self) -> &Reg<EVENTS_RXPTRUPD_SPEC>

Returns reference to RxPtrUpdated event endpoint for PPI.

pub fn event_tx_ptr_updated(&self) -> &Reg<EVENTS_TXPTRUPD_SPEC>

Returns reference to TxPtrUpdated event endpoint for PPI.

pub fn task_start(&self) -> &Reg<TASKS_START_SPEC>

Returns reference to Start task endpoint for PPI.

pub fn task_stop(&self) -> &Reg<TASKS_STOP_SPEC>

Returns reference to Stop task endpoint for PPI.

pub fn free(self) -> (I2S, Pins)

Consumes self and returns back the raw peripheral.