Module lpc845_pac::usart0

LPC84x USARTs

Modules

addr	Address register for automatic address matching.
brg	Baud Rate Generator register. 16-bit integer baud rate divisor value.
cfg	USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
ctl	USART Control register. USART control settings that are more likely to change during operation.
intenclr	Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
intenset	Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
intstat	Interrupt status register. Reflects interrupts that are currently enabled.
osr	Oversample selection register for asynchronous communication.
rxdat	Receiver Data register. Contains the last character received.
rxdatstat	Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
stat	USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
txdat	Transmit Data register. Data to be transmitted is written here.

Structs

ADDR	Address register for automatic address matching.
BRG	Baud Rate Generator register. 16-bit integer baud rate divisor value.
CFG	USART Configuration register. Basic USART configuration settings that typically are not changed during operation.
CTL	USART Control register. USART control settings that are more likely to change during operation.
INTENCLR	Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared.
INTENSET	Interrupt Enable read and Set register. Contains an individual interrupt enable bit for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set.
INTSTAT	Interrupt status register. Reflects interrupts that are currently enabled.
OSR	Oversample selection register for asynchronous communication.
RXDAT	Receiver Data register. Contains the last character received.
RXDATSTAT	Receiver Data with Status register. Combines the last character received with the current USART receive status. Allows DMA or software to recover incoming data and status together.
RegisterBlock	Register block
STAT	USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them.
TXDAT	Transmit Data register. Data to be transmitted is written here.