[−][src]Module lpc81x_pac::i2c
I2C-bus interface
Modules
cfg | Configuration for shared functions. |
div | Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME and SLVTIME registers. |
intenclr | Interrupt Enable Clear register. |
intenset | Interrupt Enable Set and read register. |
intstat | Interrupt Status register for Master, Slave, and Monitor functions. |
monrxdat | Monitor receiver data register. |
mstctl | Master control register. |
mstdat | Combined Master receiver and transmitter data register. |
msttime | Master timing configuration. |
slvadr | Slave address 0. |
slvctl | Slave control register. |
slvdat | Combined Slave receiver and transmitter data register. |
slvqual0 | Slave Qualification for address 0. |
stat | Status register for Master, Slave, and Monitor functions. |
timeout | Time-out value register. |
Structs
CFG | Configuration for shared functions. |
DIV | Clock pre-divider for the entire I2C block. This determines what time increments are used for the MSTTIME and SLVTIME registers. |
INTENCLR | Interrupt Enable Clear register. |
INTENSET | Interrupt Enable Set and read register. |
INTSTAT | Interrupt Status register for Master, Slave, and Monitor functions. |
MONRXDAT | Monitor receiver data register. |
MSTCTL | Master control register. |
MSTDAT | Combined Master receiver and transmitter data register. |
MSTTIME | Master timing configuration. |
RegisterBlock | Register block |
SLVADR | Slave address 0. |
SLVCTL | Slave control register. |
SLVDAT | Combined Slave receiver and transmitter data register. |
SLVQUAL0 | Slave Qualification for address 0. |
STAT | Status register for Master, Slave, and Monitor functions. |
TIMEOUT | Time-out value register. |