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#[doc = "Reader of register DEVCMDSTAT"] pub type R = crate::R<u32, super::DEVCMDSTAT>; #[doc = "Writer for register DEVCMDSTAT"] pub type W = crate::W<u32, super::DEVCMDSTAT>; #[doc = "Register DEVCMDSTAT `reset()`'s with value 0x0800"] impl crate::ResetValue for super::DEVCMDSTAT { type Type = u32; #[inline(always)] fn reset_value() -> Self::Type { 0x0800 } } #[doc = "Reader of field `DEV_ADDR`"] pub type DEV_ADDR_R = crate::R<u8, u8>; #[doc = "Write proxy for field `DEV_ADDR`"] pub struct DEV_ADDR_W<'a> { w: &'a mut W, } impl<'a> DEV_ADDR_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !0x7f) | ((value as u32) & 0x7f); self.w } } #[doc = "Reader of field `DEV_EN`"] pub type DEV_EN_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DEV_EN`"] pub struct DEV_EN_W<'a> { w: &'a mut W, } impl<'a> DEV_EN_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 7)) | (((value as u32) & 0x01) << 7); self.w } } #[doc = "Reader of field `SETUP`"] pub type SETUP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `SETUP`"] pub struct SETUP_W<'a> { w: &'a mut W, } impl<'a> SETUP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 8)) | (((value as u32) & 0x01) << 8); self.w } } #[doc = "Reader of field `FORCE_NEEDCLK`"] pub type FORCE_NEEDCLK_R = crate::R<bool, bool>; #[doc = "Write proxy for field `FORCE_NEEDCLK`"] pub struct FORCE_NEEDCLK_W<'a> { w: &'a mut W, } impl<'a> FORCE_NEEDCLK_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 9)) | (((value as u32) & 0x01) << 9); self.w } } #[doc = "Reader of field `FORCE_VBUS`"] pub type FORCE_VBUS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `FORCE_VBUS`"] pub struct FORCE_VBUS_W<'a> { w: &'a mut W, } impl<'a> FORCE_VBUS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 10)) | (((value as u32) & 0x01) << 10); self.w } } #[doc = "Reader of field `LPM_SUP`"] pub type LPM_SUP_R = crate::R<bool, bool>; #[doc = "Write proxy for field `LPM_SUP`"] pub struct LPM_SUP_W<'a> { w: &'a mut W, } impl<'a> LPM_SUP_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 11)) | (((value as u32) & 0x01) << 11); self.w } } #[doc = "Reader of field `INTONNAK_AO`"] pub type INTONNAK_AO_R = crate::R<bool, bool>; #[doc = "Write proxy for field `INTONNAK_AO`"] pub struct INTONNAK_AO_W<'a> { w: &'a mut W, } impl<'a> INTONNAK_AO_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 12)) | (((value as u32) & 0x01) << 12); self.w } } #[doc = "Reader of field `INTONNAK_AI`"] pub type INTONNAK_AI_R = crate::R<bool, bool>; #[doc = "Write proxy for field `INTONNAK_AI`"] pub struct INTONNAK_AI_W<'a> { w: &'a mut W, } impl<'a> INTONNAK_AI_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 13)) | (((value as u32) & 0x01) << 13); self.w } } #[doc = "Reader of field `INTONNAK_CO`"] pub type INTONNAK_CO_R = crate::R<bool, bool>; #[doc = "Write proxy for field `INTONNAK_CO`"] pub struct INTONNAK_CO_W<'a> { w: &'a mut W, } impl<'a> INTONNAK_CO_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 14)) | (((value as u32) & 0x01) << 14); self.w } } #[doc = "Reader of field `INTONNAK_CI`"] pub type INTONNAK_CI_R = crate::R<bool, bool>; #[doc = "Write proxy for field `INTONNAK_CI`"] pub struct INTONNAK_CI_W<'a> { w: &'a mut W, } impl<'a> INTONNAK_CI_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 15)) | (((value as u32) & 0x01) << 15); self.w } } #[doc = "Reader of field `DCON`"] pub type DCON_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DCON`"] pub struct DCON_W<'a> { w: &'a mut W, } impl<'a> DCON_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 16)) | (((value as u32) & 0x01) << 16); self.w } } #[doc = "Reader of field `DSUS`"] pub type DSUS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DSUS`"] pub struct DSUS_W<'a> { w: &'a mut W, } impl<'a> DSUS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 17)) | (((value as u32) & 0x01) << 17); self.w } } #[doc = "Reader of field `LPM_SUS`"] pub type LPM_SUS_R = crate::R<bool, bool>; #[doc = "Write proxy for field `LPM_SUS`"] pub struct LPM_SUS_W<'a> { w: &'a mut W, } impl<'a> LPM_SUS_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 19)) | (((value as u32) & 0x01) << 19); self.w } } #[doc = "Reader of field `LPM_REWP`"] pub type LPM_REWP_R = crate::R<bool, bool>; #[doc = "Reader of field `Speed`"] pub type SPEED_R = crate::R<u8, u8>; #[doc = "Reader of field `DCON_C`"] pub type DCON_C_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DCON_C`"] pub struct DCON_C_W<'a> { w: &'a mut W, } impl<'a> DCON_C_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 24)) | (((value as u32) & 0x01) << 24); self.w } } #[doc = "Reader of field `DSUS_C`"] pub type DSUS_C_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DSUS_C`"] pub struct DSUS_C_W<'a> { w: &'a mut W, } impl<'a> DSUS_C_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 25)) | (((value as u32) & 0x01) << 25); self.w } } #[doc = "Reader of field `DRES_C`"] pub type DRES_C_R = crate::R<bool, bool>; #[doc = "Write proxy for field `DRES_C`"] pub struct DRES_C_W<'a> { w: &'a mut W, } impl<'a> DRES_C_W<'a> { #[doc = r"Sets the field bit"] #[inline(always)] pub fn set_bit(self) -> &'a mut W { self.bit(true) } #[doc = r"Clears the field bit"] #[inline(always)] pub fn clear_bit(self) -> &'a mut W { self.bit(false) } #[doc = r"Writes raw bits to the field"] #[inline(always)] pub fn bit(self, value: bool) -> &'a mut W { self.w.bits = (self.w.bits & !(0x01 << 26)) | (((value as u32) & 0x01) << 26); self.w } } #[doc = "Reader of field `VBUS_DEBOUNCED`"] pub type VBUS_DEBOUNCED_R = crate::R<bool, bool>; #[doc = "Reader of field `PHY_TEST_MODE`"] pub type PHY_TEST_MODE_R = crate::R<u8, u8>; #[doc = "Write proxy for field `PHY_TEST_MODE`"] pub struct PHY_TEST_MODE_W<'a> { w: &'a mut W, } impl<'a> PHY_TEST_MODE_W<'a> { #[doc = r"Writes raw bits to the field"] #[inline(always)] pub unsafe fn bits(self, value: u8) -> &'a mut W { self.w.bits = (self.w.bits & !(0x07 << 29)) | (((value as u32) & 0x07) << 29); self.w } } impl R { #[doc = "Bits 0:6 - USB device address."] #[inline(always)] pub fn dev_addr(&self) -> DEV_ADDR_R { DEV_ADDR_R::new((self.bits & 0x7f) as u8) } #[doc = "Bit 7 - USB device enable."] #[inline(always)] pub fn dev_en(&self) -> DEV_EN_R { DEV_EN_R::new(((self.bits >> 7) & 0x01) != 0) } #[doc = "Bit 8 - SETUP token received."] #[inline(always)] pub fn setup(&self) -> SETUP_R { SETUP_R::new(((self.bits >> 8) & 0x01) != 0) } #[doc = "Bit 9 - Forces the NEEDCLK output to always be on:."] #[inline(always)] pub fn force_needclk(&self) -> FORCE_NEEDCLK_R { FORCE_NEEDCLK_R::new(((self.bits >> 9) & 0x01) != 0) } #[doc = "Bit 10 - If this bit is set to 1, the VBUS voltage indicators from the PHY are overruled."] #[inline(always)] pub fn force_vbus(&self) -> FORCE_VBUS_R { FORCE_VBUS_R::new(((self.bits >> 10) & 0x01) != 0) } #[doc = "Bit 11 - LPM Supported:."] #[inline(always)] pub fn lpm_sup(&self) -> LPM_SUP_R { LPM_SUP_R::new(((self.bits >> 11) & 0x01) != 0) } #[doc = "Bit 12 - Interrupt on NAK for interrupt and bulk OUT EP:."] #[inline(always)] pub fn intonnak_ao(&self) -> INTONNAK_AO_R { INTONNAK_AO_R::new(((self.bits >> 12) & 0x01) != 0) } #[doc = "Bit 13 - Interrupt on NAK for interrupt and bulk IN EP:."] #[inline(always)] pub fn intonnak_ai(&self) -> INTONNAK_AI_R { INTONNAK_AI_R::new(((self.bits >> 13) & 0x01) != 0) } #[doc = "Bit 14 - Interrupt on NAK for control OUT EP:."] #[inline(always)] pub fn intonnak_co(&self) -> INTONNAK_CO_R { INTONNAK_CO_R::new(((self.bits >> 14) & 0x01) != 0) } #[doc = "Bit 15 - Interrupt on NAK for control IN EP:."] #[inline(always)] pub fn intonnak_ci(&self) -> INTONNAK_CI_R { INTONNAK_CI_R::new(((self.bits >> 15) & 0x01) != 0) } #[doc = "Bit 16 - Device status - connect."] #[inline(always)] pub fn dcon(&self) -> DCON_R { DCON_R::new(((self.bits >> 16) & 0x01) != 0) } #[doc = "Bit 17 - Device status - suspend."] #[inline(always)] pub fn dsus(&self) -> DSUS_R { DSUS_R::new(((self.bits >> 17) & 0x01) != 0) } #[doc = "Bit 19 - Device status - LPM Suspend."] #[inline(always)] pub fn lpm_sus(&self) -> LPM_SUS_R { LPM_SUS_R::new(((self.bits >> 19) & 0x01) != 0) } #[doc = "Bit 20 - LPM Remote Wake-up Enabled by USB host."] #[inline(always)] pub fn lpm_rewp(&self) -> LPM_REWP_R { LPM_REWP_R::new(((self.bits >> 20) & 0x01) != 0) } #[doc = "Bits 22:23 - This field indicates the speed at which the device operates: 00b: reserved 01b: full-speed 10b: high-speed 11b: super-speed (reserved for future use)."] #[inline(always)] pub fn speed(&self) -> SPEED_R { SPEED_R::new(((self.bits >> 22) & 0x03) as u8) } #[doc = "Bit 24 - Device status - connect change."] #[inline(always)] pub fn dcon_c(&self) -> DCON_C_R { DCON_C_R::new(((self.bits >> 24) & 0x01) != 0) } #[doc = "Bit 25 - Device status - suspend change."] #[inline(always)] pub fn dsus_c(&self) -> DSUS_C_R { DSUS_C_R::new(((self.bits >> 25) & 0x01) != 0) } #[doc = "Bit 26 - Device status - reset change."] #[inline(always)] pub fn dres_c(&self) -> DRES_C_R { DRES_C_R::new(((self.bits >> 26) & 0x01) != 0) } #[doc = "Bit 28 - This bit indicates if VBUS is detected or not."] #[inline(always)] pub fn vbus_debounced(&self) -> VBUS_DEBOUNCED_R { VBUS_DEBOUNCED_R::new(((self.bits >> 28) & 0x01) != 0) } #[doc = "Bits 29:31 - This field is written by firmware to put the PHY into a test mode as defined by the USB2."] #[inline(always)] pub fn phy_test_mode(&self) -> PHY_TEST_MODE_R { PHY_TEST_MODE_R::new(((self.bits >> 29) & 0x07) as u8) } } impl W { #[doc = "Bits 0:6 - USB device address."] #[inline(always)] pub fn dev_addr(&mut self) -> DEV_ADDR_W { DEV_ADDR_W { w: self } } #[doc = "Bit 7 - USB device enable."] #[inline(always)] pub fn dev_en(&mut self) -> DEV_EN_W { DEV_EN_W { w: self } } #[doc = "Bit 8 - SETUP token received."] #[inline(always)] pub fn setup(&mut self) -> SETUP_W { SETUP_W { w: self } } #[doc = "Bit 9 - Forces the NEEDCLK output to always be on:."] #[inline(always)] pub fn force_needclk(&mut self) -> FORCE_NEEDCLK_W { FORCE_NEEDCLK_W { w: self } } #[doc = "Bit 10 - If this bit is set to 1, the VBUS voltage indicators from the PHY are overruled."] #[inline(always)] pub fn force_vbus(&mut self) -> FORCE_VBUS_W { FORCE_VBUS_W { w: self } } #[doc = "Bit 11 - LPM Supported:."] #[inline(always)] pub fn lpm_sup(&mut self) -> LPM_SUP_W { LPM_SUP_W { w: self } } #[doc = "Bit 12 - Interrupt on NAK for interrupt and bulk OUT EP:."] #[inline(always)] pub fn intonnak_ao(&mut self) -> INTONNAK_AO_W { INTONNAK_AO_W { w: self } } #[doc = "Bit 13 - Interrupt on NAK for interrupt and bulk IN EP:."] #[inline(always)] pub fn intonnak_ai(&mut self) -> INTONNAK_AI_W { INTONNAK_AI_W { w: self } } #[doc = "Bit 14 - Interrupt on NAK for control OUT EP:."] #[inline(always)] pub fn intonnak_co(&mut self) -> INTONNAK_CO_W { INTONNAK_CO_W { w: self } } #[doc = "Bit 15 - Interrupt on NAK for control IN EP:."] #[inline(always)] pub fn intonnak_ci(&mut self) -> INTONNAK_CI_W { INTONNAK_CI_W { w: self } } #[doc = "Bit 16 - Device status - connect."] #[inline(always)] pub fn dcon(&mut self) -> DCON_W { DCON_W { w: self } } #[doc = "Bit 17 - Device status - suspend."] #[inline(always)] pub fn dsus(&mut self) -> DSUS_W { DSUS_W { w: self } } #[doc = "Bit 19 - Device status - LPM Suspend."] #[inline(always)] pub fn lpm_sus(&mut self) -> LPM_SUS_W { LPM_SUS_W { w: self } } #[doc = "Bit 24 - Device status - connect change."] #[inline(always)] pub fn dcon_c(&mut self) -> DCON_C_W { DCON_C_W { w: self } } #[doc = "Bit 25 - Device status - suspend change."] #[inline(always)] pub fn dsus_c(&mut self) -> DSUS_C_W { DSUS_C_W { w: self } } #[doc = "Bit 26 - Device status - reset change."] #[inline(always)] pub fn dres_c(&mut self) -> DRES_C_W { DRES_C_W { w: self } } #[doc = "Bits 29:31 - This field is written by firmware to put the PHY into a test mode as defined by the USB2."] #[inline(always)] pub fn phy_test_mode(&mut self) -> PHY_TEST_MODE_W { PHY_TEST_MODE_W { w: self } } }