[−][src]Module lpc55s6x_pac::hashcrypt
Hash-Crypt peripheral
Modules
| alias | no description available |
| config | Returns the configuration of this block in this chip - indicates what services are available. |
| cryptcfg | Crypto settings for AES and Salsa and ChaCha |
| ctrl | Is control register to enable and operate Hash and Crypto |
| indata | Input of 16 words at a time to load up buffer. |
| intenclr | Write 1 to clear interrupts. |
| intenset | Write 1 to enable interrupts; reads back with which are set. |
| lock | Lock register allows locking to the current security level or unlocking by the lock holding level. |
| mask | no description available |
| memaddr | Address to start memory access from (if available). |
| memctrl | Setup Master to access memory (if available) |
| outdata0 | no description available |
| outdata1 | no description available |
| status | Indicates status of Hash peripheral. |
Structs
| RegisterBlock | Register block |
Type Definitions
| ALIAS | no description available |
| CONFIG | Returns the configuration of this block in this chip - indicates what services are available. |
| CRYPTCFG | Crypto settings for AES and Salsa and ChaCha |
| CTRL | Is control register to enable and operate Hash and Crypto |
| INDATA | Input of 16 words at a time to load up buffer. |
| INTENCLR | Write 1 to clear interrupts. |
| INTENSET | Write 1 to enable interrupts; reads back with which are set. |
| LOCK | Lock register allows locking to the current security level or unlocking by the lock holding level. |
| MASK | no description available |
| MEMADDR | Address to start memory access from (if available). |
| MEMCTRL | Setup Master to access memory (if available) |
| OUTDATA0 | no description available |
| OUTDATA1 | no description available |
| STATUS | Indicates status of Hash peripheral. |