lpc550x 0.3.0

Register mappings for the NXP LPC550x/LPC55S0x family of Cortex-M33 microcontrollers
Documentation 
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#[doc = "Register `DMA1_OTRIG_INMUX[%s]` reader"]
pub struct R(crate::R<DMA1_OTRIG_INMUX_SPEC>);
impl core::ops::Deref for R {
    type Target = crate::R<DMA1_OTRIG_INMUX_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl From<crate::R<DMA1_OTRIG_INMUX_SPEC>> for R {
    #[inline(always)]
    fn from(reader: crate::R<DMA1_OTRIG_INMUX_SPEC>) -> Self {
        R(reader)
    }
}
#[doc = "Register `DMA1_OTRIG_INMUX[%s]` writer"]
pub struct W(crate::W<DMA1_OTRIG_INMUX_SPEC>);
impl core::ops::Deref for W {
    type Target = crate::W<DMA1_OTRIG_INMUX_SPEC>;
    #[inline(always)]
    fn deref(&self) -> &Self::Target {
        &self.0
    }
}
impl core::ops::DerefMut for W {
    #[inline(always)]
    fn deref_mut(&mut self) -> &mut Self::Target {
        &mut self.0
    }
}
impl From<crate::W<DMA1_OTRIG_INMUX_SPEC>> for W {
    #[inline(always)]
    fn from(writer: crate::W<DMA1_OTRIG_INMUX_SPEC>) -> Self {
        W(writer)
    }
}
#[doc = "Field `INP` reader - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9)."]
pub type INP_R = crate::FieldReader<u8, u8>;
#[doc = "Field `INP` writer - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9)."]
pub type INP_W<'a, const O: u8> = crate::FieldWriter<'a, u32, DMA1_OTRIG_INMUX_SPEC, u8, u8, 4, O>;
impl R {
    #[doc = "Bits 0:3 - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9)."]
    #[inline(always)]
    pub fn inp(&self) -> INP_R {
        INP_R::new((self.bits & 0x0f) as u8)
    }
}
impl W {
    #[doc = "Bits 0:3 - DMA trigger output number (decimal value) for DMA channel n (n = 0 to 9)."]
    #[inline(always)]
    pub fn inp(&mut self) -> INP_W<0> {
        INP_W::new(self)
    }
    #[doc = "Writes raw bits to the register."]
    #[inline(always)]
    pub unsafe fn bits(&mut self, bits: u32) -> &mut Self {
        self.0.bits(bits);
        self
    }
}
#[doc = "DMA1 output trigger selection to become DMA1 trigger.\n\nThis register you can [`read`](crate::generic::Reg::read), [`write_with_zero`](crate::generic::Reg::write_with_zero), [`reset`](crate::generic::Reg::reset), [`write`](crate::generic::Reg::write), [`modify`](crate::generic::Reg::modify). See [API](https://docs.rs/svd2rust/#read--modify--write-api).\n\nFor information about available fields see [dma1_otrig_inmux](index.html) module"]
pub struct DMA1_OTRIG_INMUX_SPEC;
impl crate::RegisterSpec for DMA1_OTRIG_INMUX_SPEC {
    type Ux = u32;
}
#[doc = "`read()` method returns [dma1_otrig_inmux::R](R) reader structure"]
impl crate::Readable for DMA1_OTRIG_INMUX_SPEC {
    type Reader = R;
}
#[doc = "`write(|w| ..)` method takes [dma1_otrig_inmux::W](W) writer structure"]
impl crate::Writable for DMA1_OTRIG_INMUX_SPEC {
    type Writer = W;
}
#[doc = "`reset()` method sets DMA1_OTRIG_INMUX[%s]
to value 0x0f"]
impl crate::Resettable for DMA1_OTRIG_INMUX_SPEC {
    #[inline(always)]
    fn reset_value() -> Self::Ux {
        0x0f
    }
}