Expand description
Peripheral access API for LPC55S69_CM33_CORE0 microcontrollers (generated using svd2rust v0.20.0 ( ))
You can find an overview of the generated API here.
API features to be included in the next
svd2rust release can be generated by cloning the svd2rust repository, checking out the above commit, and running cargo doc --open
.
Re-exports
pub use self::Interrupt as interrupt;
pub use flash_cfpa0 as flash_cfpa_scratch;
pub use flash_cfpa0 as flash_cfpa1;
pub use gint0 as gint1;
pub use pint as secpint;
pub use ctimer0 as ctimer1;
pub use ctimer0 as ctimer2;
pub use ctimer0 as ctimer3;
pub use ctimer0 as ctimer4;
pub use dma0 as dma1;
pub use flexcomm0 as flexcomm1;
pub use flexcomm0 as flexcomm2;
pub use flexcomm0 as flexcomm3;
pub use flexcomm0 as flexcomm4;
pub use flexcomm0 as flexcomm5;
pub use flexcomm0 as flexcomm6;
pub use flexcomm0 as flexcomm7;
pub use flexcomm0 as flexcomm8;
pub use i2c0 as i2c1;
pub use i2c0 as i2c2;
pub use i2c0 as i2c3;
pub use i2c0 as i2c4;
pub use i2c0 as i2c5;
pub use i2c0 as i2c6;
pub use i2c0 as i2c7;
pub use i2s0 as i2s1;
pub use i2s0 as i2s2;
pub use i2s0 as i2s3;
pub use i2s0 as i2s4;
pub use i2s0 as i2s5;
pub use i2s0 as i2s6;
pub use i2s0 as i2s7;
pub use spi0 as spi1;
pub use spi0 as spi2;
pub use spi0 as spi3;
pub use spi0 as spi4;
pub use spi0 as spi5;
pub use spi0 as spi6;
pub use spi0 as spi7;
pub use spi0 as spi8;
pub use usart0 as usart1;
pub use usart0 as usart2;
pub use usart0 as usart3;
pub use usart0 as usart4;
pub use usart0 as usart5;
pub use usart0 as usart6;
pub use usart0 as usart7;
pub use usb1 as usb0;
Modules
ADC
AHB secure controller
ANALOGCTRL
CASPER
CRC engine
Standard counter/timers (CTIMER0 to 4)
MCU Debugger Mailbox
DMA controller
FLASH
FLASH_CFPA
FLASH_CMPA
FLASH_KEY_STORE
Flexcomm serial communication
Common register and bit access and modify traits
Group GPIO input interrupt (GINT0/1)
General Purpose I/O (GPIO)
Hash-Crypt peripheral
I2C-bus interfaces
I2S interface
Input multiplexing (INPUT MUX)
I/O pin configuration (IOCON)
Mailbox
Multi-Rate Timer (MRT)
Synchronous OS/Event timer with Wakeup Timer
Pin interrupt and pattern match (PINT)
LPC80X Programmable Logic Unit (PLU)
PMC
Digital Signal Co-Processing companion to a Cortex-M v8M CPU core
PRINCE
PUFCTRL
RNG
NXP ROM patch unit. Undocumented by NXP, this peripheral is experimentally modeled following research by Oxide Computer Company: https://oxide.computer/blog/lpc55/.
Real-Time Clock (RTC)
Security Attribution Unit
no description available
SCTimer/PWM (SCT)
SDMMC
General Purpose I/O (GPIO)
Serial Peripheral Interfaces (SPI)
SYSCON
system controller
USARTs
USB1 High-speed Device Controller
USB0 Full-speed Host controller
USB1 High-speed Host Controller
Universal System Bus Physical Layer
Micro-tick Timer (UTICK)
Windowed Watchdog Timer (WWDT)
Structs
ADC
AHB secure controller
ANALOGCTRL
CASPER
Cache and branch predictor maintenance operations
CPUID
CRC engine
Standard counter/timers (CTIMER0 to 4)
Standard counter/timers (CTIMER0 to 4)
Standard counter/timers (CTIMER0 to 4)
Standard counter/timers (CTIMER0 to 4)
Standard counter/timers (CTIMER0 to 4)
Core peripherals
MCU Debugger Mailbox
Debug Control Block
DMA controller
DMA controller
Data Watchpoint and Trace unit
FLASH
FLASH_CFPA
FLASH_CFPA
FLASH_CFPA
FLASH_CMPA
FLASH_KEY_STORE
Flexcomm serial communication
Flexcomm serial communication
Flexcomm serial communication
Flexcomm serial communication
Flexcomm serial communication
Flexcomm serial communication
Flexcomm serial communication
Flexcomm serial communication
Flexcomm serial communication
Flash Patch and Breakpoint unit
Floating Point Unit
Group GPIO input interrupt (GINT0/1)
Group GPIO input interrupt (GINT0/1)
General Purpose I/O (GPIO)
Hash-Crypt peripheral
I2C-bus interfaces
I2C-bus interfaces
I2C-bus interfaces
I2C-bus interfaces
I2C-bus interfaces
I2C-bus interfaces
I2C-bus interfaces
I2C-bus interfaces
I2S interface
I2S interface
I2S interface
I2S interface
I2S interface
I2S interface
I2S interface
I2S interface
Input multiplexing (INPUT MUX)
I/O pin configuration (IOCON)
Instrumentation Trace Macrocell
Mailbox
Memory Protection Unit
Multi-Rate Timer (MRT)
Nested Vector Interrupt Controller
Synchronous OS/Event timer with Wakeup Timer
Pin interrupt and pattern match (PINT)
LPC80X Programmable Logic Unit (PLU)
PMC
Digital Signal Co-Processing companion to a Cortex-M v8M CPU core
PRINCE
PUFCTRL
All the peripherals
RNG
NXP ROM patch unit. Undocumented by NXP, this peripheral is experimentally modeled following research by Oxide Computer Company: https://oxide.computer/blog/lpc55/.
Real-Time Clock (RTC)
Security Attribution Unit
System Control Block
no description available
SCTimer/PWM (SCT)
SDMMC
General Purpose I/O (GPIO)
Pin interrupt and pattern match (PINT)
Serial Peripheral Interfaces (SPI)
Serial Peripheral Interfaces (SPI)
Serial Peripheral Interfaces (SPI)
Serial Peripheral Interfaces (SPI)
Serial Peripheral Interfaces (SPI)
Serial Peripheral Interfaces (SPI)
Serial Peripheral Interfaces (SPI)
Serial Peripheral Interfaces (SPI)
Serial Peripheral Interfaces (SPI)
SYSCON
system controller
SysTick: System Timer
Trace Port Interface Unit
USARTs
USARTs
USARTs
USARTs
USARTs
USARTs
USARTs
USARTs
USB1 High-speed Device Controller
USB1 High-speed Device Controller
USB0 Full-speed Host controller
USB1 High-speed Host Controller
Universal System Bus Physical Layer
Micro-tick Timer (UTICK)
Windowed Watchdog Timer (WWDT)
Enums
Enumeration of all the interrupts.
Constants
Number available in the NVIC for configuring priority